Lecture #4 1

Lecture #4 – VLSI DesignReview MOS Transistor Basics

Pinchoff Threshold Voltage VT

Current Equation Linear Saturation

Channel Length Modulation

2

DSDSTGS'nD V

2

1VVV

L

WkI

2TGS

'nD VV

2L

WkI

TGSDS VVV

DSTGS'nD VVV

L

WkI

Lecture #4 2

At ‘a’

2

DSDSTGS'nD V

2

1VVV

L

WkI

DSDSTGS'nD VV

2

1VV

L

WkI

At ‘b’

DSTGS'n

ONV

21

VVLW

k

1R

TGS'n

ONVV

LW

k

1R

1.5V

a

b

•• •c

At ‘c’ 2TGS

'n

D VVL

W

2

kI

2TGS'n

DSON

VVLW

k

V2R

Lecture #4 3

For NMOS

For PMOS

Lecture #4 4

Ron

|VGS| < |VT||VGS| > |VT|

|VGS|

Switch Model of CMOS Transistor

Lecture #4 5

VDD

VIN VOUT

VoutVin

Vin

Vout

VOH

VOL

VOHVOL

Vth

Vin = Vout

Switching Threshold

Nominal Voltage LevelsVth = ?

Inverter DC Operation Voltage Transfer

Characteristic

Lecture #4 6

Delay Definitions

tpHL tpLH

t

t

Vin

Vout

50%

50%

tr

10%

90%

tf

Lecture #4 7

CMOS Inverter Steady State Response

VDD

VOUT

VIN = VDD VIN = 0

RON

VOH = VDD

VOL= 0

Vth = Ronp) f(Ronn,

VDD

RON

VOUT

Threshold Voltage

Lecture #4 8

CMOS Circuit FabricationProcess Steps for Patterning through

Photolithography

Optically project the shadow of a pattern on to the chip

and transfer the pattern to the chip

Lecture #4 9

NMOS Transistor

Polysilicon Gate

Field Oxide

(Thick Oxide)

Gate Oxide

(Thin Oxide)

Lecture #4 10

Patterning Silicon

Si - Substarate

Silicon Di-oxide

Lecture #4 11

Lithography

Process used to transfer patterns to each layer of IC.Lithography sequence steps:Designer: - Drawing the layer patterns on a layout editorSilicon Foundry: - Mask generation from the layer patterns in the design data base - Printing: transfer the mask pattern to the wafer surface - Process the wafer to physically pattern each layer

of the IC

Lecture #4 12

Process Steps

Lecture #4 13

Process steps for Patterning

Light Sensitive organic polymer

Grow Crystal Saw

Silicon Wafer

Silicon Wafer

Oxide Layer SiO2 1m

Silicon Wafer

Oxide Layer

Photoresist

Bare silicon Wafer

Grow Oxide Layer

Spin coating with Photoresist –1mm

Thermal Oxidation

Acid-resistant

Soluble once exposed to UV

Light

4-12” dia <1mm

Lecture #4 14

Pattern formed on a glass plate (Mask) Transparent & Opaque

regionsPositive Photoresist Non exposed regions hardened

higher resolution

(hardened)Silicon Wafer

Oxide LayerExposed soluble

Expose to Ultraviolet Light

Lecture #4 15

Etching continued to remove SiO2

Pattern formed

Silicon Wafer

Oxide Layer

Silicon Wafer

Silicon Wafer

Soluble photoresist is chemically removed (etching) using HF acid

High-temp. plasma

removes hardened

photoresist

Lecture #4 16

Patterned Silicon

Si - Substarate