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Department of EECS University of California, Berkeley
EECS 105 Fall 2004, Lecture 41
Lecture 41: Review Frequency Response, FET physics
Prof. J. S. Smith
Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Final Exam
Covers the course from the beginningDate/Time: SATURDAY, MAY 15, 2004 8-11A Location: BECHTEL auditorium One page (Two sides) of notes
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Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Q&A about the finalQ: Are differential amplifiers going to be on the exam?A: No, there will not be a differential amplifier question.Q: Do we need to know a lot of device physics for BJTs? A: No, there won’t be any BJT physicsQ: Will there be any BJT circuits questions on the exam?A: No, the exam will not have any BJT transistor problems.Q: How much of the material from before Midterm 1 willbe tested in detail?
A: Material before midterm 1 is fair game.Q: Also, are we responsible for Chapter 5 i.e.- digital circuits?A: No, nothing specifically on digital circuits or from chapter 5.
Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Last Week of Lecture
Monday:– Review of Frequency domain analysis of linear circuits,
Bode plots.
Wednesday:– Frequency Response– Semiconductor materials, FET physics and models
Friday:– Review of active linear circuits, amplifiers wrapup
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Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Frequency response: CS
When we take into account a finite source impedance in a common source amplifier, the capacitances will reduce the voltage swing at the gate at high frequencies.
Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Parasitic Capacitances
The transfer function will be a low pass filter, with a pole at the frequency determined by the source resistance and the capacitance.
vs
rs
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Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
High frequency zero
At very high frequencies, the gain flattens out again, because the capacitor couples from the gate to the drain directly, as a passive circuit
vs
rs
Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Magnitude Bode Plot
ωp
βo
zωTω
0 dB
pole
Unity current gain
zero
Low frequencygain
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Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Miller Capacitance CM
Effective input capacitance:
( )[ ]gdvCgdgdvCMin CAjCjACj
Zgd
−=⎟
⎟⎠
⎞⎜⎜⎝
⎛⎟⎟
⎠
⎞
⎜⎜
⎝
⎛
−==
111
111
ωωω
AV,Cx
+
─
+
─
VinVout
Cx
AV,Cx
+
─
+
─Vout
(1-Av,Cx)Cx
(1-1/Av,Cx)Cx
Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Frequency response
−
+
gsv
−
+
outvinmvgor
gdC
gsC LR~
SR
−
+
gsv
−
+
outvinmvgorgsC LR~
SR
MC
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Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Some Examples
Common source (emitter) amplifier:
=gdvCA Negative, large number (-100)
Common drain (collector) amplifier:
=gsvCA Slightly less than 1
→Miller Multiplied Cap has Detrimental Impact on bandwidth
“Bootstrapped” cap has negligible impact on bandwidth!
( ) gdgdCVM CCACgd
1001 , ≈−=
( ) gsgsCVM CCACgs
01 , ≈−=
Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Open Circuit Time Constants
For a circuit dominated by a single poleFor each capacitor in the circuit you calculate an equivalent resistor “seen” by capacitor and form a time constant τi=RiCi
The dominant pole then is the sum of these time constants in the circuit
,1 2
1p domω
τ τ=
+ +L
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Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. SmithEquivalent Resistance “Seen” by Capacitor
For each “small” capacitor in the circuit:– Open-circuit all other “small” capacitors– Short circuit all “big” capacitors– Turn off all independent sources– Replace cap under question with current or voltage
source– Find equivalent input impedance seen by cap– Form RC time constant
Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Remember…
For a given capacitor:If the frequency is high compared to the 1/RC for the capacitor in that location in the circuit
– That Capacitor can be modeled as a short
If the frequency is low compared to the 1/RC for the capacitor in that location in the circuit
– That Capacitor can be modeled by an open circuit.
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Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Common-Drain Amplifier
21 ( )2DS ox GS T
WI C V VL
µ= −
2 DSGS T
ox
IV V WCL
µ= +
Weak IDS dependence
Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
CD Voltage Gain
1out m
in mb m
v gv g g
≈ ≈+
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Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
CD Output Resistance
Sum currents at output (source) node:
|| || tout o oc
t
vR r ri
= t m t mb ti g v g v= +
1out
m mb
Rg g
≈+
Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
CD Output Resistance (Cont.)
ro || roc is much larger than the inverses of the transconductances ignore
1out
m mb
Rg g
≈+
Function: a voltage buffer• High Input Impedance• Low Output Impedance
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Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Add capacitors
Procedure:Start with small-signal two-port modelAdd device (and other) capacitors
gdC
gsC
−+
inout vv ≈
Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Common Gate Amplifier
DC bias:
SUP BIAS DSI I I= =
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Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
CG→Current buffer
out d ti i i= = −
1iA = −
Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
CG Input Resistance
gs tv v= −
mbmin gg
R+
≈1
We found the approximation:
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Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
CG Output Resistance
)]1([||][|| SmoocSomoocout RgrrRrgrrR +=+≈
Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
CG Two-Port Model
The function of the CG amp was a current buffer:•Low input impedance•High output impedance
The only parasitic capacitances are directly across theInput and output: frequency response can be directlydetermined
( )SmOC Rrgrr 00|| +
gsC gdC
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Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. SmithSingle-Stage Amp Frequency Response
CS, CE: suffer from Miller-magnified capacitor for high-gain caseCD, CC: Miller transformation nulledcapacitor “wideband stage”CG, CB: no Millerized capacitor wideband stage (for low load resistance)
Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Electrostatics summary
In one dimension, the electrostatics equations reduce to the E field growing or diminishing depending on the net charge:
Which can also be written as a differential equation for the potential (voltage).
')'()()(0
0 dxxxExEx
x∫+=
ερ
ερφ )()(
2
2 xdx
xd−=
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Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Net Charge
The net charge density in a semiconductor is calculated from the number of charge carriers and fixed charges in a location:
If a region does not have the right number of electrons or holes to cancel the amount of charge from the dopants, the fixed charge of the dopants will influence the electric fields.
( ))()()()()( xNxNxnxpqx ad −+−=ρ
Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Thermal EquilibriumA couple fundamental principles about thermal equilibrium:
So when we look at this:
We know that the electrons are feeling a force due to the electric field, but there is also diffusion which contributes a exactly canceling amount of current! This means the diffusion constant can always be found in terms of mobility
Conduction band
Valence band
Fermi Level
•The energy that electrons are filled up to(the Fermi level) is the same everywhere.
•The current is zero at all points.
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Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Total Current and Boundary Conditions
The total current is given by the sum of drift and diffusion:
In resistors, the carriers are approximately uniform and the second term is nearly zeroIn metals, there are a very large number of carriers, in very uniform concentration, and the conduction current is quite linear with E (ohmic)
dxdnqDnEqJJJ nndiffdrift +=+= µ
Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Transport summary
The number of majority carriers in a neutral semiconductor goes according to the number of Donors or acceptors, and the number of minority carriers is found from the law of mass actionFor n-type material:
For p-type material:
The total current is given by the sum of drift and diffusion:
dxdnqDnEqJJJ nndiffdrift +=+= µ
ad NNn −≈nnp i
2
≈
da NNp −≈p
nn i2
≈
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Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Note: Band edge diagrams
We will often draw a diagram of the valence and the conduction band edges as a function of position.The energy at the band edge corresponds to the potential energy that an electron has (which is the negative of the electrostatic potential). Thus the slope of the band edge with distance is the electric field. (Silicon)
P type N type
Ener
gy
Distance
+++++++++
- - -- - -- - -
→Force on electrons←E field
Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
The Einstein relation (diffusion)
Since the diffusion process has a fundamental relationship to the mobility in an electric field, we can find the diffusion constant in terms of the mobility µ.
nn qkTD µ⎟⎟
⎠
⎞⎜⎜⎝
⎛=
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Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Carrier Concentration Versus Potential
The carrier concentration is thus a function of potential
Check that for zero potential, we have intrinsic carrier concentration (reference). If we do a similar calculation for holes, we arrive at a similar equation
Note that the law of mass action is upheld
thVxienxn /)(
00)( φ=
thVxienxp /)(
00)( φ−=
2/)(/)(200
00)()( iVxVx
i neenxpxn thth == − φφ
Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
PN Junction Fields
n-typep-type
NDNA
)(0 xpaNp =0
d
i
Nnp
2
0 =diffJ
0E
a
i
Nnn
2
0 =
Transition Region
diffJ
dNn =0
– – + +
0E
0px− 0nx
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Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Total Charge in Transition Region
To solve for the electric fields, we need to write down the charge density in the transition region:
In the p-side of the junction, there are very few electrons and only acceptors:
Since the hole concentration is decreasing on the p-side, the net charge is negative:
)()( 000 ad NNnpqx −+−=ρ
)()( 00 aNpqx −≈ρ
0)(0 <xρ0pNa >
00 <<− xxp
Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Charge on N-Side
Analogous to the p-side, the charge on the n-side is given by:
The net charge here is positive since:
)()( 00 dNnqx +−≈ρ 00 nxx <<
0)(0 >xρ0nNd >
a
i
Nnn
2
0 =
Transition Region
diffJ
dNn =0
– – + +
0E
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Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Accumulation
Under a higher forward bias, the mobile carriers get pushed up against the barrier, and start to pile up in a thin layer there, the accumulation layerThe bias where accumulation starts is called flat band
“Metal”Oxide
Semiconductor(n type)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Inversion
Under a strong reverse bias, the potential at the surface of the semiconductor, next to the oxide, can get high enough so that holes start to accumulate in a thin layer, the inversion layer
“Metal”Oxide
Semiconductor(n type)
Depletion region+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Band edge diagram: accumulation
“Metal” InsulatorN type semiconductor
Fermi level
Fermi levelLots of electrons
Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Band edge diagram: Flat band
“Metal” InsulatorN type semiconductor
Fermi level
Fermi level
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Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Band edge diagram: forward bias
“Metal” InsulatorN type semiconductor
Fermi level
Fermi level
Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Band edge diagram: equilibrium
“Metal” InsulatorN type semiconductor
Fermi level
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Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Band edge diagram: reverse bias
“Metal” InsulatorN type semiconductor
Fermi level
Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Band edge diagram: inversion
“Metal” InsulatorN type semiconductor
Fermi level
←holes
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Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Band edge diagram: more inversion
“Metal” InsulatorN type semiconductor
Fermi level
lots of holes
Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
P type body
If the semiconductor is p type, rather than n type:– The depletion has a negative fixed charge– An inversion layer is an accumulation of electrons
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Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
NMOS, below threshold
“Metal” InsulatorP type semiconductor
Fermi level
Fermi level
N+ semiconductor
p-type substrate
n+ n+
S DB
p+L jx
NMOS
G
Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
NMOS, near threshold
“Metal” InsulatorP type semiconductor
Fermi level
Fermi level
N+ semiconductor Electrons
p-type substrate
n+ n+
S DB
p+L jx
NMOS
G
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Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
NMOS, above threshold
“Metal” InsulatorP type semiconductor
Fermi level
Fermi level
N+ semiconductor Electrons
p-type substrate
n+ n+
S DB
p+L jx
NMOS
G
Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Variable resistor
If the Source and Drain voltages are about the same, then the inversion charge is about the same at different positions along the gate. The amount of charge under the gate is that which was calculated for the MOS capacitorThe current from the source to the drain is given by the amount of charge, the mobility of the carriers, and the component of the electric field from the source to the drain
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Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Observed Behavior: ID-VGS
Current zero for negative gate voltageCurrent in transistor is very low until the gate voltage crosses the threshold voltage of device (same threshold voltage as MOS capacitor)Current increases rapidly at first and then it finally reaches a point where it simply increases linearly
GSV
DSI
TV
GSV
DSIDSV
Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
SaturationAs the Source-Drain voltage is increased, there will be a significant change in the charge at different distances along the gateAs the voltage across the device at the drain end is below threshold, the current is pinched off.If there is no current out the drain end, however, the current due to the carriers which are available from the source cause the voltage to be closer to that of the source.These two effects cause a small region to form near the drain which limits the current.
This is called saturation
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Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Pinching the MOS Transistors
When VDS > VDS,sat, the channel is “pinched” off at drain end (hence the name “pinch-off region”)Drain mobile charge goes to zero (region is depleted), the remaining elecric field is dropped across this high-field depletion regionAs the drain voltage is increases further, the pinch off point moves back towards source
p-type
n+ n+p+
Pinch-Off Point
GS TnV V>
DSVG
DS
NMOS
Depletion RegionGS TnV V−
Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Observed Behavior: ID-VDS
For low values of drain voltage, the device is like a resistorAs the voltage is increases, the resistance behaves non-linearly and the rate of increase of current slowsEventually the current stops growing and remains essentially constant (current source)
DSV
/DSI k
“constant” current
resistor region
non-linear resistor region
2GSV V=
3GSV V=
4GSV V=
GSV
DSIDSV
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Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
“Linear” Region Current
If the gate is biased above threshold, the surface is invertedThis inverted region forms a channel that connects the drain and gateIf a drain voltage is applied positive, electrons will flow from source to drain
p-type
n+ n+p+
Inversion layer“channel”
GS TnV V>
100mVDSV ≈G
DS
NMOS
x
y
Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
MOSFET “Linear” Region
The current in this channel is given by
The charge proportional to the voltage applied across the oxide over threshold
If the channel is uniform density, only drift current flows
DS y NI Wv Q= −
( )N ox GS TnQ C V V= −
( )DS y ox GS TnI Wv C V V= − −
y n yv Eµ= − DSy
VEL
= −
GS TnV V>( )DS n ox GS Tn DSWI C V V VLµ= − 100mVDSV ≈
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Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
MOSFET: Variable Resistor
Notice that in the linear region, the current is proportional to the voltage
Can define a voltage-dependent resistor
This is a nice variable resistor, it is electronically tunable!
( )DS n ox GS Tn DSWI C V V VLµ= −
1 ( )( )
DSeq GS
DS n ox GS Tn
V L LR R VI C V V W Wµ
⎛ ⎞= = =⎜ ⎟− ⎝ ⎠
Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Observed Behavior: ID-VDS
DSV
/DSI k
“constant” current
resistor region
non-linear resistor region
2GSV V=
3GSV V=
4GSV V=
GSV
DSIDSV
As the drain voltage increases, the E field across the oxide at the drain endis reduced, and so the charge is less, and the current no longer increases proportionally. As the gate-source voltage is increased, this happensat higher and higher drain voltages. The start of the saturation region is shaped like a parabola
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Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Finding ID = f (VGS, VDS)Approximate inversion charge QN(y): drain is higher than the source less charge at drain end of channel
Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Inversion Charge at Source/Drain
)()0(
TnGSox
N
VVCyQ
−−== == )( LyQN
)( TnGDox VVC −−
DSGSGD VVV −=
2)()0()( LyQyQyQ NN
N=+=
≈
The charge under the gate along the gate, but we are going to make a simple approximation, that the average charge is the average of the charge near the source and drain
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Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Average Inversion Charge
Charge at drain end is lower since field is lower Notice that this only works if the gate is inverted along its entire lengthIf there is an inversion along the entire gate, it works well because Q is proportional to V everywhere the gate is inverted
( ) ( )( )2
ox GS T ox GD TN
C V V C V VQ y − + −≈ −
Source End Drain End
( ) ( )( )2
ox GS T ox GS SD TN
C V V C V V VQ y − + − −≈ −
(2 2 )( ) ( )2 2
ox GS T ox SD DSN ox GS T
C V V C V VQ y C V V− −≈ − = − − −
Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Drift Velocity and Drain Current
“Long-channel” assumption: use mobility to find v
( ) ( ) ( / ) n DSn n
Vv y E y V yL
µµ µ= − ≈ − −∆ ∆ =
And now the current is just charge per area, times velocity, times the width:
( )2
DS DSD N ox GS T
V VI WvQ W C V VL
µ= − ≈ − −
( )2DS
D ox GS T DSVWI C V V V
Lµ≈ − −
Inverted Parabolas
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Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Square-Law Characteristics
Boundary: what is ID,SAT?TRIODE REGION
SATURATION REGION
Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
The Saturation Region
When VDS > VGS – VTn, there isn’t any inversioncharge at the drain … according to our simplistic model
Why do curvesflatten out?
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Department of EECS University of California, Berkeley
EECS 105 Spring 2004, Lecture 41 Prof. J. S. Smith
Square-Law Current in Saturation
Current stays at maximum (where VDS = VGS – VTn = VDS,SAT)
Measurement: ID increases slightly with increasing VDSmodel with linear “fudge factor”
( )2DS
D ox GS T DSVWI C V V V
Lµ= − −
, ( )( )2
GS TDS sat ox GS T GS T
V VWI C V V V VLµ −
= − − −
2, ( )
2ox
DS sat GS TCWI V V
Lµ
= −
2, ( ) (1 )
2ox
DS sat GS T DSCWI V V V
Lµ λ= − +