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Low Density Parity Check(LDPC) Code Implementation
Matthew Pregara & Zachary Saigh
Advisors: Dr. In Soo Ahn & Dr. Yufeng Lu
Dept. of Electrical and Computer Eng.
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Contents Background and Motivation
Linear Block Coding Example
Hard Decision Tanner Graph Decoding
Constructing LDPC Codes
Soft Decision Decoding
Results
Conclusion
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Background ARQ: Automatic Repeat Request
Detects errors and requests retransmission
Example: Even or Odd Parity
FEC: Forward Error Correction Detects AND Corrects Errors
Examples: Linear Block Coding
Turbo Codes
Convolutional Codes
Why LDPC?
Low decoding complexity
Higher code rate
Better Error performance
Industry standard for: 802.11n Wi-Fi
Digital Video Broadcasting
WiMAX and 4G
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Performance Comparison
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(taken from [1])
Project Goals Create LDPC code system simulation with
MATLAB/Simulink
Implement a scaled down LDPC system on a FPGA using Xilinx System Generator
Complete System performance comparison between MATLAB/Simulink and FPGA implementation
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Linear Block Coding Block Codes are denoted by (n, k).
k = message bits (message word)
n = message bits + parity bits (coded bits)
# of parity bits: m = n - k
Code Rate R = k/n
Ex: (7,4) code
4 message bits
+3 parity bits
= 7 coded bits
Code rate R = 4/7
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Hamming Code Example
G(encoder matrix)
+ u m
e
rH’
(decoder matrix)
+
e
r u’
Error Lookup TableS
e = error patternm = message bit wordu = code wordr = received code word with errorS = syndromeu’ = corrected code wordm’ = received message word
Remove Parity bits m’
ChannelTransmitter Receiver
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Constructing Hamming Code
Factor xn +1
Populate G matrix (k x n) with shifted factor
Take reduced row echelon form to find
Systematic G matrix from G matrix
H matrix is obtained by manipulating the
systematic G matrix.
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Encoding Example
101
111
110
011
1000
0100
0010
0001
1101
321 ppp1101
1111mmmp 4311 0101mmmp 3212 0110mmmp 4323
0011101
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Decoding
1 2 3 4 1 2 3
1 1 0
0 1 1
1 1 1
m m m m p p p 1 0 1
1 0 0
0 1 0
0 0 1
1 2 3
1 1 3 4 1
2 1 2 3 2
3 2 3 4 3
m m m p
m m m p
m m m p
S S S
S
S
S
S = rcvd. code word × HT
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Correcting Errors
0 1 1S
In this case the 2nd bit is corrupted Invert the corrupted bit according to the
location found by the syndrome table
0011101
0000010
0011111
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Tanner Graph and Hard Decision Decoding
C1
C2
C3
V1
V2
V3
V4
V5
V6
V7
V8
C4
01011001
11100100
00100111
10011010
H
(2458)
(1236)
(3678)
(1457)
(8,4) Example
87654321 VVVVVVVV
4
3
2
1
C
C
C
C
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Hard Decision Decoding
C1
C2
C3
V1
V2
V3
V4
V5
V6
V7
V8
C4
1
0
1
0
1
0
1
1CheckNodes
Activities
C1
Receive V2→ 1 V4→ 1 V5→ 0 V8→ 1
Send 0 → V2 0 → V4 1 → V5 0 → V8
C2
Receive V1→ 1 V2→ 1 V3→ 0 V6→ 1
Send 0 → V1 0 → V2 1 → V3 0 → V6
C3
Receive V3→ 0 V6→ 1 V7→ 0 V8→ 1
Send 0 → V3 1 → V6 0 → V7 1 → V8
C4
Receive V1→ 1 V4→ 1 V5→ 0 V7→ 0
Send 1 → V1 1 → V4 0 → V5 0 → V7
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Hard Decision Decoding
C1
C2
C3
V1
V2
V3
V4
V5
V6
V7
V8
C4
1
0
1
0
1
0
1
1CheckNodes
Activities
C1
Receive V2→ 1 V4→ 1 V5→ 0 V8→ 1
Send 0 → V2 0 → V4 1 → V5 0 → V8
C2
Receive V1→ 1 V2→ 1 V3→ 0 V6→ 1
Send 0 → V1 0 → V2 1 → V3 0 → V6
C3
Receive V3→ 0 V6→ 1 V7→ 0 V8→ 1
Send 0 → V3 1 → V6 0 → V7 1 → V8
C4
Receive V1→ 1 V4→ 1 V5→ 0 V7→ 0
Send 1 → V1 1 → V4 0 → V5 0 → V7
Update
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Hard Decision Decoding
C1
C2
C3
V1
V2
V3
V4
V5
V6
V7
V8
C4
1
0
1
0
1
0
1
1CheckNodes
Activities
C1
Receive V2→ 1 V4→ 1 V5→ 0 V8→ 1
Send 0 → V2 0 → V4 1 → V5 0 → V8
C2
Receive V1→ 1 V2→ 1 V3→ 0 V6→ 1
Send 0 → V1 0 → V2 1 → V3 0 → V6
C3
Receive V3→ 0 V6→ 1 V7→ 0 V8→ 1
Send 0 → V3 1 → V6 0 → V7 1 → V8
C4
Receive V1→ 1 V4→ 1 V5→ 0 V7→ 0
Send 1 → V1 1 → V4 0 → V5 0 → V7
Update
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Hard Decision Decoding
C1
C2
C3
V1
V2
V3
V4
V5
V6
V7
V8
C4
1
0
1
0
1
0
1
1CheckNodes
Activities
C1
Receive V2→ 1 V4→ 1 V5→ 0 V8→ 1
Send 0 → V2 0 → V4 1 → V5 0 → V8
C2
Receive V1→ 1 V2→ 1 V3→ 0 V6→ 1
Send 0 → V1 0 → V2 1 → V3 0 → V6
C3
Receive V3→ 0 V6→ 1 V7→ 0 V8→ 1
Send 0 → V3 1 → V6 0 → V7 1 → V8
C4
Receive V1→ 1 V4→ 1 V5→ 0 V7→ 0
Send 1 → V1 1 → V4 0 → V5 0 → V7
Update
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Variable Node DecisionsVariable Nodes yi Messages from Check Nodes Decision
V1 1 C2 → 0 C4 → 1 1
V2 1 C1 → 0 C2 → 0 0
V3 0 C2 → 1 C3 → 0 0
V4 1 C1 → 0 C4 → 1 1
V5 0 C1 → 1 C4 → 0 0
V6 1 C2 → 0 C3 → 1 1
V7 0 C3 → 0 C4 → 0 0
V8 1 C1 → 0 C3 → 1 1
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Differences of LDPC Code
Construct H matrix first
H is sparsely populated with 1s
Fewer edges → less computations
Find the systematic H and G matrices
G will not be sparse
Soft Decision Decoding
Uses Tanner Graph representation with an iterative process
No “hard-clipping” of received code word 2dB performance gain over hard decision [2]
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Encoder Matrix
G+ u m
e
r LDPCDecoder u’
e = error patternm = message bit wordu = code wordr = received code word with errorS = syndromeu’ = corrected code wordm’ = received message word
Remove Parity bits m’
ChannelTransmitter Receiver
High Level LDPC System Block Diagram
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Soft Decision Decoder Diagram
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-7.11158
-1.5320
-0.3289
5.7602
2.7111
0.4997
-5.1652
1.5357
-5.0942
1.2526
1
1
2
2
3
3
4
4
5
5
6
7
8
9
10
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-7.11158
-1.5320
-0.3289
5.7602
2.7111
0.4997
-5.1652
1.5357
-5.0942
1.2526
12
2
3
3
4
4
5
5
6
7
8
9
10
Re-Calculate Each Edge
-1.5320
-0.3289
5.7602
1
2525
-7.11158
-1.5320
-0.3289
5.7602
2.7111
0.4997
-5.1652
1.5357
-5.0942
1.2526
12
2
3
3
4
4
5
5
6
7
8
9
10
Re-Calculate Each Edge
-1.5320
-0.3289
5.7602
1
262626
-7.11158
-1.5320
-0.3289
5.7602
2.7111
0.4997
-5.1652
1.5357
-5.0942
1.2526
1
12
2
3
3
4
4
5
5
6
7
8
9
10
Re-Calculate Each Edge
-1.5320
-0.3289
5.7602
SUM
-1.5320
Update Algorithm
27272727
-7.11158
-1.5320
-0.3289
5.7602
2.7111
0.4997
-5.1652
1.5357
-5.0942
1.2526
1
12
2
3
3
4
4
5
5
6
7
8
9
10
Re-Calculate Each Edge
-1.5320
5.7602
SUM
-0.3289
Update Algorithm
-0.3289
28282828
-7.11158
-1.5320
-0.3289
5.7602
2.7111
0.4997
-5.1652
1.5357
-5.0942
1.2526
1
12
2
3
3
4
4
5
5
6
7
8
9
10
Re-Calculate Each Edge
-1.5320
-0.3289
5.7602
This Updated Value is Sent back to Variable Node 1
SUM
5.7602
Update Algorithm
0.2096
0.2096
2929
-7.11158
-1.5320
-0.3289
5.7602
2.7111
0.4997
-5.1652
1.5357
-5.0942
1.2526
12
2
3
3
4
4
5
5
6
7
8
9
10
Re-Calculate Each Edge
-0.3289
5.7602
-7.11158
1
303030
-7.11158
-1.5320
-0.3289
5.7602
2.7111
0.4997
-5.1652
1.5357
-5.0942
1.2526
12
2
3
3
4
4
5
5
6
7
8
9
10
Re-Calculate Each Edge
5.7602
-7.11158
-1.5320
1
31313131
-7.11158
-1.5320
-0.3289
5.7602
2.7111
0.4997
-5.1652
1.5357
-5.0942
1.2526
2
2
3
3
4
4
5
5
6
7
8
9
10
Re-Calculate Each Edge
-7.11158
-1.5320
-0.3289
1
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Decoding Algorithm
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Difficult to implement on a FPGA Solutions:
Find an approximation Construct lookup table
Phi function:
Lookup table Approach
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Note: all inputs are >=0
Simulation Results
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Simulink LDPC System
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36Encoder Comparison
Encoder with Xilinx blocks
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Co-Simulation Results
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Xilinx LDPC Decoder
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Decoder Control Logic
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Check Node Implementation
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Conclusion MATLAB/Simulink simulation of LDPC system has been
completed.
An efficient approximation of decoding algorithm has been
developed for hardware implementation.
Xilinx System generator design for the decoder has been
constructed.
Comparison and verification has not been completed for
those results from MATLAB and Xilinx system generator.
FPGA implementation and a scaled up system may not be
completed.
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References[1] Valenti, Matthew. Iterative Solutions Coded Modulation Library
Theory of Operation. West Virginia University, 03 Oct. 2005. Web. 23 Oct. 2012. <www.wvu.edu>.
[2] B. Sklar, Digital Communications, second edition: Fundamentals and Applications, Prentice-Hall, 2000.
[3] Xilinx System Generator Manual, Xilinx Inc. , 2011.
Questions?
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Appendix
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Matrix Manipulation
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Reducing Decoding Complexity
Square_add function: y = max_star(L1,L2) - max_star(0, L1+L2);
MAX* function: if (L1==L2)
y = L1;
return;
end;
y = max(L1,L2) + log(1+exp(-abs(L1-L2)));
end;
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Reducing Decoding Complexity This: y = max(L1,L2) + log(1+exp(-abs(L1-L2)));
Becomes Approximated MAX* function: x = -abs(L1-L2);
if ((x<2) && (x>=-2))
y = max(L1,L2) + 3/8;
else
y = max(L1,L2);
end;
No costly log function
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In Practice
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Using MATLAB’s Code Profiler…
MAX* function takes: 25.85s of simulation
Approx. MAX* function takes: 28.02s of equally sized simulation
Difference of 2.17s
Simulation Results
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(10,5) Code 1000 codewords
per datapoint, or 10,000 bits
Timeline
Jan 28, 2013 May 15, 2013
Feb 1, 2013 Mar 1, 2013 Apr 1, 2013 May 1, 2013
Apr 15, 2013 - Apr 19, 2013Student Expo
Feb 11, 2013MATLAB Implementation
Feb 25, 2013Performance Analysis
Mar 4, 2013Xilinx System Generator Model
Apr 2, 2013FPGA Implementation
May 9, 2013 - May 15, 2013Project Presentations
Mar 29, 2013Student Expo Abstract Due
Apr 21, 2013Design Scaling
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Division of LaborZack
Simulink Model Xilinx System
generator design of decoder
Implementation of VHDL on FPGA
Performance analysis of FPGA implementation
Matt MATLAB Simulation Error Performance
Analysis Xilinx System
generator design of encoder
Performance analysis of MATLAB/Xilinx implementation
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