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© April 19, 2019 Dr. Lynn Fuller
Low Power CMOS
Page 1
Rochester Institute of Technology
Microelectronic Engineering
ROCHESTER INSTITUTE OF TECHNOLOGYMICROELECTRONIC ENGINEERING
Low Power CMOS
Dr. Lynn FullerWebpage: http://people.rit.edu/lffeee
Microelectronic EngineeringRochester Institute of Technology
82 Lomb Memorial DriveRochester, NY 14623-5604
Email: Lynn.Fuller@rit.eduDepartment webpage: http://www.rit.eduu/kgcoe/microelectronic/
4-19-2019 LowPowerCMOS.ppt
© April 19, 2019 Dr. Lynn Fuller
Low Power CMOS
Page 2
Rochester Institute of Technology
Microelectronic Engineering
ADOBE PRESENTER
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© April 19, 2019 Dr. Lynn Fuller
Low Power CMOS
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Rochester Institute of Technology
Microelectronic Engineering
INTRODUCTION
CMOS is suppose to be low power because CMOS gates only draw current from the supply during switching. In steady state High or Low CMOS gates do not draw power (almost zero). This document will investigate Energy and Power used by a complex CMOS integrated circuit and propose methods for reducing power consumed by the circuit.
© April 19, 2019 Dr. Lynn Fuller
Low Power CMOS
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Rochester Institute of Technology
Microelectronic Engineering
INTRODUCTION
What is a complex integrated circuit.
Answer: A big chip with many small transistors on it. The biggest chips could be as large as 1” by 1” and the small transistors could be 20nm gate lengths or smaller.
Chip Area is: 1”x1” or 25.4mm x 24.5mm = 645 mm2
Transistor size is : L=20nm and W = several times larger, plus room for drain and source, contact cuts and metal. This might be around 100nm x 100nm = 10,000 nm2
A complex chip could have as many as #N transistors based on area:#N = Chip Area / Transistor Area#N = 645 mm2 / 10,000 nm2 = 645x1E12/10,000
= 64.5 Billion Transistors!!
© April 19, 2019 Dr. Lynn Fuller
Low Power CMOS
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Rochester Institute of Technology
Microelectronic Engineering
INTRODUCTION
Transistor count for selected microcontrollers.
Name #’s of Transistors Date Design Size Area
“Transistor Count" Wikipedia: The Free Encyclopedia.
Wikimedia Foundation, Inc., Web. 25 April 2017.
https://en.wikipedia.org/wiki/Transistor_count
© April 19, 2019 Dr. Lynn Fuller
Low Power CMOS
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Rochester Institute of Technology
Microelectronic Engineering
CMOS INVERTER CURRENT DURING TRANSITION
Imax =70uA
Vout
Vin
Imin =0uA
© April 19, 2019 Dr. Lynn Fuller
Low Power CMOS
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Rochester Institute of Technology
Microelectronic Engineering
POWER MEASUREMENTS
Power consumed by a micro circuit can be easily measured.
Power = I V just measure I and V (while chip is operating)
To compare chips of different sizes we can use power density.
Power Density = Power / Chip Area
Example: 5 volts, 10 amps, chip area = 1cm x 1cm
P = 50 watts
Power Density = 50 w/cm2 Very Hot!!
© April 19, 2019 Dr. Lynn Fuller
Low Power CMOS
Page 8
Rochester Institute of Technology
Microelectronic Engineering
COOLING MICROCHIPS
Why is one chip cooled
and not the others.
© April 19, 2019 Dr. Lynn Fuller
Low Power CMOS
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Rochester Institute of Technology
Microelectronic Engineering
POWER DENSITY TRENDS
CMOS is suppose to be low power. Power density surpassed hot-plate at 0.5um technology node. Today we are way past the
power density of a nuclear reactor.
Fred Pollack, Intel
1000
100
10
1
Watt
s/cm
2
1.5u 1u 0.7u 0.5u 0.35u 0.25u 0.1u 0.13u 0.1u 0.07u
Hot PlatePentium III
Pentium II
Pentium Pro
Pentium
i486
Nuclear Reactor
© April 19, 2019 Dr. Lynn Fuller
Low Power CMOS
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Rochester Institute of Technology
Microelectronic Engineering
WE DEMAND HIGH SPEED COMPLEX CHIPS
CMOS running at high speed with millions of active gates is needed to provide capabilities we demand:
Java interpreterText/Graphics processingSpeech recognitionVideo decompressionProtocolsEncryptionHandwriting recognitionGamesmore…..
© April 19, 2019 Dr. Lynn Fuller
Low Power CMOS
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Rochester Institute of Technology
Microelectronic Engineering
COOLING MICROCHIPS
Chip Cooling is Expensive
© April 19, 2019 Dr. Lynn Fuller
Low Power CMOS
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Rochester Institute of Technology
Microelectronic Engineering
POWER USED BY A CMOS INVERTER
How Do we get to such high power densities? CMOS is suppose to be low power because CMOS gates only draw current during switching. Lets investigate a CMOS inverter first and maybe we can apply what we learn to more complex integrated circuits.
First Review:Power (electrical) P = I V (watts)Power Density P = P / Area (watts/cm2)Energy W = Power x Time (watt-seconds, joules)Charge storage in a battery Q = I t (amp-hours)
note: battery voltage is known so Energy W = V Q
Example: CR2032 (3 volt battery is rated at 200 mA-hr)it can deliver 720 coulombs of charge or 2160 joules of energy
© April 19, 2019 Dr. Lynn Fuller
Low Power CMOS
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Rochester Institute of Technology
Microelectronic Engineering
POWER FOR INVERTER TRANSITION
V+
VinVout
C
Q = CV
I = Q/t = CV/t
P = IV
P = CV2/tVout
t
+V
0
Vin
t
+V
0
I
t
Imax
0
Each low to high transition is accompanied by a pulse of current from the V+ supply.
Assume no current from V+ to ground when both transistors are on during switching. (current only to charge C)
I
© April 19, 2019 Dr. Lynn Fuller
Low Power CMOS
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Rochester Institute of Technology
Microelectronic Engineering
SPICE OF INVERTER FOR PULSED INPUT
Zoom in of output Transition
waveforms on next page
© April 19, 2019 Dr. Lynn Fuller
Low Power CMOS
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Rochester Institute of Technology
Microelectronic Engineering
SPICE OF INVERTER FOR PULSED INPUT
Because there are internal capacitors connected from gate to drain (input to output) we see some spikes from capacitive feed through.
We also see the voltage and current during the transition of the output.
Lets find the average current per transition.
Feed through
Feed through
Output High to Low
Output Low to High
Transition Iave
Vin Vout
Iload
© April 19, 2019 Dr. Lynn Fuller
Low Power CMOS
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Rochester Institute of Technology
Microelectronic Engineering
SPICE OF INVERTER FOR PULSED INPUT
Current from power supply during the low to high transition is Iave = 1/t integral of i(t) dtIave here ~ 50uA
Current to the load capacitor Iave= ~ 10uA
and should equal CV/t=0.48fF 2.5/120ps=10uA
Difference is current through both transistors during switching ~40uA
Isupply
Iload
© April 19, 2019 Dr. Lynn Fuller
Low Power CMOS
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Rochester Institute of Technology
Microelectronic Engineering
MATCHING RISE AND FALL TIME IS GOOD
Wpmos = 1.25 x WnmostdLTH = 604ps
tdHTL = 652psGate delay is the time to get to 50% of the final value.
I in C1
Vout
© April 19, 2019 Dr. Lynn Fuller
Low Power CMOS
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Rochester Institute of Technology
Microelectronic Engineering
CURRENT COMPONENTS FOR CMOS INVERTER
The current flows from the V+ to the capacitive load during the low to high transition, tLTH. That current is CV/tLTH.
Current also flows from V+ through the PMOS and NMOS during switching when both transistors are on.
Current also leaks through the reverse biased drain and source junctions to the substrate plus gate leakage. (assume small compared to the two currents above)
© April 19, 2019 Dr. Lynn Fuller
Low Power CMOS
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Rochester Institute of Technology
Microelectronic Engineering
TOTAL POWER
Supply Iave per transition = IavePower per transition = Iave x V+ Load Capacitance = CPower to load only = C V2 / tLTHClock frequency = fTransitions/sec = some ?% of possible transitionsNumber of gates = thousands or millions
Total Power = combination of above
Total Power = Iave x V x f x tLTH x ?% x N
Power to charge load capacitance only= C V2 / tLTH x f x tLTH x ?% x N
© April 19, 2019 Dr. Lynn Fuller
Low Power CMOS
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Rochester Institute of Technology
Microelectronic Engineering
EXAMPLE POWER CALCULATION
Example for 2um technology: Assume rise and fall time are matched thus Iload will be matched and = 100uA. Iave from supply is 300uA per transition. Assume V+ = 3 volts, Load C = 0.028pF, clock f = 1Mhz, Transitions = 20% of clock, tLTH = 600ps, Number of gates N = 20 million
Total Power = Iave x V x f x tLTH x 20% x N
= 300u x 3 x 1M x 600p x 20% x 20E6 = 2.16 watts
Power to charge load capacitance only= C V2 / tLTH x f x tLTH x ?% x N
= 0.028p x 9 x 1M x 20% x 20 million = 1.01 watts
© April 19, 2019 Dr. Lynn Fuller
Low Power CMOS
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Rochester Institute of Technology
Microelectronic Engineering
SUMMARY
Power is an important design criteria1. Reduce Vdd
(at 28nm node Vdd ~0.5 volts)2. Lower clock speed
(not always possible)3. Reduce transistor size4. Minimize capacitances5. Optimize and minimize gate delays6. Use dynamic logic where appropriate
© April 19, 2019 Dr. Lynn Fuller
Low Power CMOS
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Rochester Institute of Technology
Microelectronic Engineering
CMOS DOMINO LOGIC EVOLUTION
+V
VOVA
VB
precharge
VA
+V
VO
VB
evaluate
VA
+V
VO
VB
CLKCMOS
Dynamic Domino
YEARS
© April 19, 2019 Dr. Lynn Fuller
Low Power CMOS
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Rochester Institute of Technology
Microelectronic Engineering
CMOS DOMINO LOGIC
VA
VB
VC
VOUT
CLK
+V
DOMINO Logic
NMOS
complex
Domino Logic gates require a clock. High output is easy to obtain since the upper transistor will be on when the clock is off. If the output is suppose to be low it is only low during the clock pulse when the lower transistor is on (dynamic logic).
© April 19, 2019 Dr. Lynn Fuller
Low Power CMOS
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Rochester Institute of Technology
Microelectronic Engineering
CMOS DOMINO LOGIC
When the clock is low Vout is precharged high. When the clock is high Vout is valid.
© April 19, 2019 Dr. Lynn Fuller
Low Power CMOS
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Rochester Institute of Technology
Microelectronic Engineering
STATIC CMOS NOR-2
When the clock is low Vout is precharged high. When the clock is high Vout is valid.
© April 19, 2019 Dr. Lynn Fuller
Low Power CMOS
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Rochester Institute of Technology
Microelectronic Engineering
REFERENCES
1. Microelectronic Circuits, Sedra and Smith, 7th edition.
2. More
© April 19, 2019 Dr. Lynn Fuller
Low Power CMOS
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Rochester Institute of Technology
Microelectronic Engineering
HOMEWORK – LOW POWER CMOS
1. If some gates used dynamic logic techniques it might be possible to reduce power by reducing current. Investigate and compare static CMOS gate versus dynamic logic gate for power.
2. Compare power for 2um technology with power for 200nm technology. Assume same number of gates. Show an example approximate calculation.