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This document will discuss various types of semiconductor memory. We will look at layout of memory arrays. We will describe circuits common to all memory such as row and column decoders, readout electronics, and sense amplifiers.
Read-Only Memories (ROMs) - These are used to store information that will not change during the life of the system. They are permanently programmed during manufacture. Nonvolatile read-write Memories (EPROM, EEPROM) - These devices retain the information stored in them when the power is turned off. They can be erased but usually much slower than they can be written. The number of erase/write cycles may be limited. Dynamic Random Access Memories (DRAMs) - Information is stored as charge on a capacitor. The stored charge will eventually leak away so DRAMs must be periodically refreshed. Typically DRAMs are refreshed every 5-50 milli seconds. One transistor one capacitor per cell. Static Random Access Memories (SRAM) - These devices store information in two cross-coupled inverters. Such a memory does not need to be refreshed. CMOS SRAM is low power. The SRAM cell requires six transistors making it fewer bits per chip than DRAM.
The peripheral circuits include multiplexers, decoders, sense amplifiers, column precharge, data buffers, Read-write circuits, level shifting, amplification and more. These circuits have to work for Millions or Billions of storage locations.
A decoder will activate (high) one row (only) from a binary input. For example a 16 bit address will be able to address 2n rows or 216 = 65536 rows, 232 = 4.29Billion rows and 264 = 18.4Quintillion rows. We need more NOR gates…..each NOR is n-inputs.
•A DRAM memory cell is formed with one transistor and one capacitor. Referred to as a 1T1C cell. •Storing a logic ONE requires a voltage of +Vdd/2 across C1. •Storing a logic ZERO requires a voltage of -Vdd/2 across C1. •Various leakage paths cause the capacitor to slowly deplete charge. •The capacitor needs to be refreshed periodically, which makes the DRAM dynamic rather than static. •Typical refresh rates are every 5-50 msec •Voltage at node x=Vdd for logic one and ground for logic zero
Q7 is turned on with signal fp precharging the two digit lines to Vdd/2
Q7
Note: the memory is organized into two arrays so that one can be used as the reference for the other. (with basically identical digit line capacitance)
Fs goes high and the data in the selected memory cell is sensed. The word line WL0 goes high and the charge on selected capacitor C0 is shared with the capacitance of the digit line D0. If a “1” was stored in C0 the voltage on D0 will initially be a little higher than Vdd/2. The voltage on the reference digit line will initially be Vdd/2. The crosscoupled inverters amplify these starting voltage and bring the digit line D0 to Vdd and D0* to zero volts. The capacitor C0 is recharged (refreshed) at the same time it is read. If a “0” was stored in C0 the voltage on D0 will initially be a little lower than Vdd/2. The crosscoupled inverters bring D0 to zero volts, refreshing C0 and providing a one for an output on D0*.
The electrical engineer will be involved with the design, testing or application of semiconductor memory at some point in his/her career. An understanding of the different types of semiconductor memory and the peripheral circuits is important.
