Post on 07-Aug-2018
transcript
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE
SINGRAYAKONDA
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PART 1
FRONT END
LOGIC GATESAIM:
a. Write a program for digital circuit using VHDL.
b. Verify the functionality of designed circuit.
c. i!e the "iming simulation for critical path time calculation # also
hesis for Digital $ircuit.
d. %mplement the place # route techni&ue for ma'or ()* !endor i.e.+ ,%L%N,
-
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e. %mplement the designed digital circuit using ()* #$)LD de!ices.
APPARATUS:
1. $omputer system2. ,ilinx ./ soft0are tool
PROCEDURE:
Double clic1 on ,%L%N, %2E %$3N.
$lic1 on 4le and ne0 pro'ect.
Enter the pro'ect name and location clic1 on next.
$hoose the settings # clic1 on next # 4nally clic1 on 4nish.
Double clic1 on create ne0 source.
$hoose VHDL module # enter the 4le name clic1 o next.
Enter the post name # 2elect the direction # clic1 on next # 4nish 4nally.
Write the program # clic1 on program name in source 0indo0.
$lic1 on5t6 %$3N of synthesis7xst then double clic1 on the chec1 syntax option.
8
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3nce chec1 syntax is completed successfully+ you can go for simulation.
$hoose sources for beha!ioral simulation and clic1 on the program name you 0ill
get model sim simulator option on the process 0indo0.
$lic1 on 596 icon of model sim simulator then double clic1 on simulator
beha!ioral simulation.
$lic1 on 9 ;33e the 0indo0 of 0a!eform.
?ight clic1 on the signal and select the force !alue.
$hange the !alue from 5@6 to either 5/6 or 5-6 and clic1 3A and clic1 on run icon #
similarly !ary the inputs !alue for all possible options and obser!e the output.
$lose the model sim simulator and come bac1 to implementation in the source
for options.
$lic1 on 596 icon of user constraints and double clic1 on Boor plan %D pre7
2ynthesis.
$lic1 on 5Ces6 and enter the pin numbers in the L3$ column and clic1 on sa!e
icon and clic1 on 53A6.
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Double clic1 on con4gure target de!ice # clic1 on yes.
"urn on the po0er for the board and clic1 on 4nish.
"0o de!ices 0ill get identi4ed clic1 on bypass 0hen de!ices ,$(/82 is selected.
$lic1 on the 5.bit6 4le # select open 0hen de!ice ,$2// is selected and clic1
3A.
?ight clic1 on de!ice ,$2// and choose program option by clic1ing of right
clic1 and clic1 on 3A.
%mpact 0ill start to do0nload the 5bit6 4le to board.
3nce you got the program succeeded message +you can test the output on
board.
2ee the output ports by !arying the input ports.
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VHDL PROGRAM:
AND GATE:
Behavioa! Mo"e!:
Library %EEEF
@se %EEE. 2"D_L3%$_--G.allF
Entity and_gate is
)ort a : in 2"D_L3%$F
b : in 2"D_L3%$F
c : out 2"D_L3%$=F
end and_gateF
*rchitecture and_gate_beh of and_gate is
egin
processa+ b=
begin
if a I J-J and b I J-J then c KI J-JF
else c KI J/JF
end ifF
end processF
end and_gate_behF
Da#a$o% Mo"e!:
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Library %EEEF
@se %EEE. 2"D_L3%$_--G.allF
Entity and_gate is
)ort a : in 2"D_L3%$F
b : in 2"D_L3%$F
c : out 2"D_L3%$=F
end and_gateF
*rchitecture and_gate_df of and_gate is
egin
c KI a and bF
end and_gate_dfF
S#&'#&a! Mo"e!:
Library %EEEF
@se %EEE. 2"D_L3%$_--G.allF
Entity and_gate is
)ort a : in 2"D_L3%$F
b : in 2"D_L3%$F
c : out 2"D_L3%$=F
end and_gateF
*rchitecture and_str of and_gate is
component and_gate
)ort a : in 2"D_L3%$F
G
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b : in 2"D_L3%$F
c : out 2"D_L3%$=F
end componentF
begin
@- : and_gate port map a+b+c=F
end and_strF
LOGIC SYMBOL AND TRUTH TABLE:
AND GATE
TRUTH TABLE
SIMULATION RESULTS:
* C
/ / /
/ - /- / /
- - -
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OR GATE:
Behavioa! Mo"e!:
Library %EEEF
@se %EEE. 2"D_L3%$_--G.allF
Entity or_gate is
)ort a : in 2"D_L3%$F
b : in 2"D_L3%$F
c : out 2"D_L3%$=F
end or_gateF
*rchitecture or_gate_beh of or_gate is
egin
processa+ b=
begin
M
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if a I J/J and b I J/J then c KI J/JF
else c KI J-JF
end ifF
end processF
end or_gate_behF
Da#a$o% Mo"e!:
Library %EEEF
@se %EEE. 2"D_L3%$_--G.allF
Entity or_gate is
)ort a : in 2"D_L3%$F
b : in 2"D_L3%$F
c : out 2"D_L3%$=F
end or_gateF
*rchitecture or_gate_df of or_gate is
egin
c KI a or bF
end or_gate_dfF
S#&'#&a! Mo"e!:
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Library %EEEF
@se %EEE. 2"D_L3%$_--G.allF
Entity or_gate is
)ort a : in 2"D_L3%$F
b : in 2"D_L3%$F
c : out 2"D_L3%$=F
end or_gateF
*rchitecture or_str of or_gate is
component or_gate
)ort a : in 2"D_L3%$F
b : in 2"D_L3%$F
c : out 2"D_L3%$=F
end componentF
begin
@- : or_gate port mapa+b+c=F
end or_strF
-/
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LOGIC SYMBOL AND TRUTH TABLE:
OR GATE
TRUTH TABLE
SIMULATION RESULTS:
3?*"E:7
--
* C
/ / /
/ - -
- / -
- - -
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NOT GATE:
Behavioa! Mo"e!:
Library %EEEF
@se %EEE. 2"D_L3%$_--G.allF
Entity not_gate is
)ort a : in 2"D_L3%$F
c : out 2"D_L3%$=F
end not_gateF
*rchitecture not_gate_beh of not_gate is
egin
)rocess a=
begin
if a I J/J then
-8
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c KI J-JF
else
c KI J/JF
end ifF
end processF
end not_gate_behF
Da#a$o% Mo"e!:
Library %EEEF
@se %EEE. 2"D_L3%$_--G.allF
Entity not_gate is
)ort a : in 2"D_L3%$F
c : out 2"D_L3%$=F
end not_gateF
*rchitecture not_gate_df of not_gate is
egin
c KI not aF
end not_gate_dfF
S#&'#&a! Mo"e!:
Library %EEEF
@se %EEE. 2"D_L3%$_--G.allF
-
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Entity not_gate is
)ort a : in 2"D_L3%$F
c : out 2"D_L3%$=F
end not_gateF
*rchitecture not_str of not_gate is
component not_gate
)ort a : in 2"D_L3%$F
c : out 2"D_L3%$=F
end componentF
begin
@- : not_gate port mapa+c=F
end not_strF
LOGIC SYMBOL AND TRUTH TABLE:
NOT GATE
TRUTH TABLE
-
* C/ -
- /
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SIMULATION RESULTS:
N3" *"E:7
NAND GATE:
Behavioa! Mo"e!:
Library %EEEF
@se %EEE. 2"D_L3%$_--G.allF
Entity nand_gate is
)ort a : in 2"D_L3%$F
b : in 2"D_L3%$F
c : out 2"D_L3%$=F
end nand_gateF
*rchitecture nand_gate_beh of nand_gate is
-
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egin
processa+ b=
begin
if a I J-J and b I J-J then c KI J/JF
else c KI J-JF
end ifF
end processF
end nand_gate_behF
Da#a$o% Mo"e!:
Library %EEEF
@se %EEE. 2"D_L3%$_--G.allF
Entity nand_gate is
)ort a : in 2"D_L3%$F
b : in 2"D_L3%$F
c : out 2"D_L3%$=F
end nand_gateF
*rchitecture nand_gate_df of nand_gate is
egin
c KI a nand bF
end nand_gate_dfF
S#&'#&a! Mo"e!:
Library %EEEF
@se %EEE. 2"D_L3%$_--G.allF
-G
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Entity nand_gate is
)ort a : in 2"D_L3%$F
b : in 2"D_L3%$F
c : out 2"D_L3%$=F
end nand_gateF
*rchitecture nand_str of nand_gate is
component nand_gate
)ort a : in 2"D_L3%$F
b : in 2"D_L3%$F
c : out 2"D_L3%$=F
end componentF
begin
@- : nand_gate port mapa+b+c=F
end nand_strF
LOGIC SYMBOL AND TRUTH TABLE:
NAND GATE TRUTH TABLE
-
* C
/ / -
/ - -
- / -
- - /
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SIMULATION RESULTS:
N*ND*"E:7
NOR GATE:
Behavioa! Mo"e!:
Library %EEEF
@se %EEE. 2"D_L3%$_--G.allF
Entity nor_gate is
)ort a : in 2"D_L3%$F
b : in 2"D_L3%$F
c : out 2"D_L3%$=F
end nor_gateF
*rchitecture nor_gate_beh of nor_gate is
egin
processa+ b=
begin
-M
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if a I J/J and b I J/J then c KI J-JF
else c KI J/JF
end ifF
end processF
end nor_gate_behF
Da#a$o% Mo"e!:
Library %EEEF
@se %EEE. 2"D_L3%$_--G.allF
Entity nor_gate is
)ort a : in 2"D_L3%$F
b : in 2"D_L3%$F
c : out 2"D_L3%$=F
end nor_gateF
*rchitecture nor_gate_df of nor_gate is
egin
c KI a nor bF
end nor_gate_dfF
S#&'#&a! Mo"e!:
-
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Library %EEEF
@se %EEE. 2"D_L3%$_--G.allF
Entity nor_gate is
)ort a : in 2"D_L3%$F
b : in 2"D_L3%$F
c : out 2"D_L3%$=F
end nor_gateF
*rchitecture nor_str of nor_gate is
component nor_gate
)ort a : in 2"D_L3%$F
b : in 2"D_L3%$F
c : out 2"D_L3%$=F
end componentF
begin
@- : nor_gate port mapa+b+c=F
end nor_strF
LOGIC SYMBOL AND TRUTH TABLE:
NOR GATE
TRUTH TABLE
8/
* C
/ / -
/ - /
- / /
- - /
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SIMULATION RESULTS:
N3?*"E:
8-
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(OR GATE:
Behavioa! Mo"e!:
Library %EEEF
@se %EEE. 2"D_L3%$_--G.allF
Entity xor_gate is
)ort a : in 2"D_L3%$F
b : in 2"D_L3%$F
c : out 2"D_L3%$=F
end xor_gateF
*rchitecture xor_gate_beh of xor_gate is
egin
processa+ b=
begin
if a I b then c KI J/JF
else c KI J-JF
end ifF
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end processF
end xor_gate_behF
Da#a$o% MO"e!:
Library %EEEF
@se %EEE. 2"D_L3%$_--G.allF
Entity xor_gate is
)ort a : in 2"D_L3%$F
b : in 2"D_L3%$F
c : out 2"D_L3%$=F
end xor_gateF
*rchitecture xor_gate_df of xor_gate is
egin
c KI a xor bF
end xor_gate_dfF
S#&'#&a! Mo"e!:
Library %EEEF
@se %EEE. 2"D_L3%$_--G.allF
8
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Entity xor_gate is
)ort a : in 2"D_L3%$F
b : in 2"D_L3%$F
c : out 2"D_L3%$=F
end xor_gateF
*rchitecture xor_str of xor_gate is
component xor_gate
)ort a : in 2"D_L3%$F
b : in 2"D_L3%$F
c : out 2"D_L3%$=F
end componentF
begin
@- : xor_gate port mapa+b+c=F
end xor_strF
LOGIC SYMBOL AND TRUTH TABLE:
(OR GATE
TRUTH TABLE
8
* C
/ / /
/ - -
- / -
- - /
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SIMULATION RESULTS:
,orgate:
8
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(NOR GATE:
Behavioa! Mo"e!:
Library %EEEF
@se %EEE. 2"D_L3%$_--G.allF
Entity xnor_gate is
)ort a : in 2"D_L3%$F
b : in 2"D_L3%$F
c : out 2"D_L3%$=F
end xnor_gateF
*rchitecture xnor_gate_beh of xnor_gate is
egin
processa+ b=
begin
if a I b then c KI J-JF
else c KI J/JF
8G
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end ifF
end processF
end xnor_gate_behF
Da#a$o% Mo"e!:
Library %EEEF
@se %EEE. 2"D_L3%$_--G.allF
Entity xnor_gate is
)ort a : in 2"D_L3%$F
b : in 2"D_L3%$F
c : out 2"D_L3%$=F
end xnor_gateF
*rchitecture xnor_gate_df of xnor_gate is
egin
c KI a xnor bF
end xnor_gate_dfF
S#&'#&a! Mo"e!:
Library %EEEF
@se %EEE. 2"D_L3%$_--G.allF
Entity xnor_gate is
)ort a : in 2"D_L3%$F
8
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b : in 2"D_L3%$F
c : out 2"D_L3%$=F
end xnor_gateF
*rchitecture xnor_str of xnor_gate is
component xnor_gate
)ort a : in 2"D_L3%$F
b : in 2"D_L3%$F
c : out 2"D_L3%$=F
end componentF
begin
@- : xnor_gate port mapa+b+c=F
end xnor_strF
LOGIC SYMBOL AND TRUTH TABLE:
(NOR GATE
TRUTH TABLE
8M
* C
/ / -
/ - /
- / /
- - -
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SIMULATION RESULTS:
,norgate:
RESULT:
8
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3 8 DECODER
AIM:
To write VHDL and verilog program for 3 8 Decoder simulate the program and verify the
results.
APPARATUS:
Computer system
ilin! ".# software tool
PROCEDURE:
Double clic1 on ,%L%N, %2E %$3N.
$lic1 on 4le and ne0 pro'ect.
Enter the pro'ect name and location clic1 on next.
/
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$hoose the settings # clic1 on next # 4nally clic1 on 4nish.
Double clic1 on create ne0 source.
$hoose VHDL module # enter the 4le name clic1 o next.
Enter the post name # 2elect the direction # clic1 on next # 4nish 4nally.
Write the program # clic1 on program name in source 0indo0.
$lic1 on5t6 %$3N of synthesis7xst then double clic1 on the chec1 syntax option.
3nce chec1 syntax is completed successfully+ you can go for simulation.
$hoose sources for beha!ioral simulation and clic1 on the program name you 0ill
get model sim simulator option on the process 0indo0.
$lic1 on 596 icon of model sim simulator then double clic1 on simulator
beha!ioral simulation.
$lic1 on 9 ;33e the 0indo0 of 0a!eform.
?ight clic1 on the signal and select the force !alue.
-
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$hange the !alue from 5@6 to either 5/6 or 5-6 and clic1 3A and clic1 on run icon #
similarly !ary the inputs !alue for all possible options and obser!e the output.
$lose the model sim simulator and come bac1 to implementation in the source
for options.
$lic1 on 596 icon of user constraints and double clic1 on Boor plan %D pre7
2ynthesis.
$lic1 on 5Ces6 and enter the pin numbers in the L3$ column and clic1 on sa!e
icon and clic1 on 53A6.
Double clic1 on con4gure target de!ice # clic1 on yes.
"urn on the po0er for the board and clic1 on 4nish.
"0o de!ices 0ill get identi4ed clic1 on bypass 0hen de!ices ,$(/82 is selected.
$lic1 on the 5.bit6 4le # select open 0hen de!ice ,$2// is selected and clic1
3A.
8
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?ight clic1 on de!ice ,$2// and choose program option by clic1ing of right
clic1 and clic1 on 3A.
%mpact 0ill start to do0nload the 5bit6 4le to board.
3nce you got the program succeeded message +you can test the output on
board.
2ee the output ports by !arying the input ports.
VHDL PROGRAM:
li$rary %&&&'
use %&&&.(TD)L*+%C)##,-.LL'
use %&&&.(TD)L*+%C)/%TH.LL'
use %&&&.(TD)L*+%C)01(%+1&D.LL'
entity decoder is
2ort g#4g54g3 6 in std)logic'
6 in std)logic)vector5 downto 7'
9 6 out std)logic)vector7 to "'
end decoder'
architecture :ehavioral of decoder is
signal 9#6std)logic)vector7 to " '
$egin with select 9#;< =7#######= when =777=4
=#7######= when =77#=4
=##7#####= when =7#7=4
=###7####= when =#77=4
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=####7###= when =7##=4
=#####7##= when =#7#=4
=######7#= when =##7=4
=#######7= when =###=4
=########= when others'
9;< 9# when +# and not +5 and not +3#>
else =########='
end :ehavioral'
VERILOG PROGRAM:
module decoderveriloga4$4c4en4 ?'
input a4$4c4en'
output @"67A ?'
wire a$ar4$$ar4c$ar'
nota$ar4a'
not$$ar4$'
notc$ar4c'
and?@7A4en4a$ar4$$ar4c$ar'
and?@#A4en4a$ar4$$ar4c'
and?@5A4en4a$ar4$4c$ar'
and?@3A4en4a$ar4$4c'
and?@-A4en4a4$$ar4c$ar'
and?@BA4en4a4$$ar4c'
and?@,A4en4a4$4c$ar'
and?@"A4en4a4$4c'
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endmodule
LOGIC SYMBOL AND TRUTH TABLE:
3 x 8 decode
TRUTH TABLE
%120T( *0T20T(
+# +5)L +5:)L C : 9")L 9,)L 9B)L 9-)L 93)L 95)L 9#)L 97)L
* /=
3@"-
-
3
@"
-
8*
3@"
-
8
3@"
-
* -=3@"
-
* 8=
3@"
-
C/
3-
"-
C-
3@
"-
C8
3@
"-
C
3@
"-
C
3@
"-
C
3@
"-
CG
3@
"-
C
3@"-
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7 # # # # # # # #
# # # # # # # # #
# # # # # # # # #
# 7 7 7 7 7 # # # # # # # 7
# 7 7 7 7 # # # # # # # 7 #
# 7 7 7 # 7 # # # # # 7 # #
# 7 7 7 # # # # # # 7 # # #
# 7 7 # 7 7 # # # 7 # # # #
# 7 7 # 7 # # # 7 # # # # #
# 7 7 # # 7 # 7 # # # # # #
# 7 7 # # # 7 # # # # # # #
RTL SCHEMATIC:
G
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SYNTHESIS REPORT:
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F #of8 decoder 6 #
Cell 0sage 6
F :&L( 6 #7
F %1V 6 #
F L0T5 6 #
F L0T3 6 8
F liplopsILatches 6 8
F LD& 6 8
F %* :uffers 6 #-
F %:0 6 ,
F *:0 6 8
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)n7777)n7777#6* O 1*1&?)" O 8 O
NNN
This # clocM signals are generated $y com$inatorial logic4
and (T is not a$le to identify which are the primary clocM signals.
2lease use the CL*CE)(%+1L constraint to specify the clocM signals generated $y com$inatorial
logic.
%1*6st65#, HDL DV%(*/ (ome clocM signals were not automatically $uffered $y (T with
:0+I:0/ resources. 2lease use the $uffer)type constraint in order to insert these $uffers to the clocM
signals to help prevent sMew pro$lems.
Timing (ummary6
(peed +rade6 ,
Ginimum period6 1o path found
Ginimum input arrival time $efore clocM6 -.55ns
Ga!imum output reJuired time after clocM6 ,.,#3ns
Ga!imum com$inational path delay6 1o path found
Timing Detail6
ll values displayed in nanoseconds ns
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Cell6inPout fanout Delay Delay Logical 1ame 1et 1ame
%:06%P* # 7."" 7.57 e3)inv)%:0 e3)inv)%:0
%1V6%P* 8 7.-,8 5.7B7 ?)7))n777##)%1V)7 ?)7))n777#
LD&6+& 7.,8" ?)7
Total -.55ns #.B5ns logic4 5."7ns route
3."K logic4 ,7.3K route
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1um$er of errors 6 7 7 filtered
1um$er of warnings 6 # 7 filtered
1um$er of infos 6 # 7 filtered
SIMULATION RESULTS:
-
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!x" DE MULTIPLE#ER
AIM:
To write VHDL R verilog program for demultiple!er 4 simulate the program and verify the results
APPARATUS:
Computer system
ilin! ".# software tool
PROCEDURE:
Double clic1 on ,%L%N, %2E %$3N.
$lic1 on 4le and ne0 pro'ect.
Enter the pro'ect name and location clic1 on next.
$hoose the settings # clic1 on next # 4nally clic1 on 4nish.
Double clic1 on create ne0 source.
$hoose VHDL module # enter the 4le name clic1 o next.
8
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Enter the post name # 2elect the direction # clic1 on next # 4nish 4nally.
Write the program # clic1 on program name in source 0indo0.
$lic1 on5t6 %$3N of synthesis7xst then double clic1 on the chec1 syntax option.
3nce chec1 syntax is completed successfully+ you can go for simulation.
$hoose sources for beha!ioral simulation and clic1 on the program name you 0ill
get model sim simulator option on the process 0indo0.
$lic1 on 596 icon of model sim simulator then double clic1 on simulator
beha!ioral simulation.
$lic1 on 9 ;33e the 0indo0 of 0a!eform.
?ight clic1 on the signal and select the force !alue.
$hange the !alue from 5@6 to either 5/6 or 5-6 and clic1 3A and clic1 on run icon #
similarly !ary the inputs !alue for all possible options and obser!e the output.
$lose the model sim simulator and come bac1 to implementation in the source
for options.
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$lic1 on 596 icon of user constraints and double clic1 on Boor plan %D pre7
2ynthesis.
$lic1 on 5Ces6 and enter the pin numbers in the L3$ column and clic1 on sa!e
icon and clic1 on 53A6.
Double clic1 on con4gure target de!ice # clic1 on yes.
"urn on the po0er for the board and clic1 on 4nish.
"0o de!ices 0ill get identi4ed clic1 on bypass 0hen de!ices ,$(/82 is selected.
$lic1 on the 5.bit6 4le # select open 0hen de!ice ,$2// is selected and clic1
3A.
?ight clic1 on de!ice ,$2// and choose program option by clic1ing of right
clic1 and clic1 on 3A.
%mpact 0ill start to do0nload the 5bit6 4le to board.
3nce you got the program succeeded message +you can test the output on
board.
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2ee the output ports by !arying the input ports.
VHDL PROGRAM6
li$rary %&&&'
use %&&&.(TD)L*+%C)##,-.LL'
use %&&&.(TD)L*+%C)/%TH.LL'
use %&&&.(TD)L*+%C)01(%+1&D.LL'
entity demultiple!er is
2ort s# 6 in std)logic'
sel 6 in std)logic)vector # downto 7'
J 6 out std)logic)vector 3 downto 7'
end demultiple!er'
architecture :ehavioral of demultiple!er is
signal J# 6 std)logic)vector 3 downto 7'
$egin
with sel select J#;< =###7= when =77=4
=##7#= when =7#=4
=#7##= when =#7=4
=7###= when =##=4
=####= when others'
J;< J# when s#< >7>
else =####='
end :ehavioral'
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$e%&o' (o')* :
module demu!verilogd4en4 s4 y'
input d4en'
input @567A s'
output @"67A y'
wire s5$ar4s#$ar4s7$ar'
nots5$ar4s@5A'
nots#$ar4s@#A'
nots7$ar4s@7A'
andy@7A4d4en4s5$ar4s#$ar4s7$ar'
andy@#A4d4en4s5$ar4s#$ar4s@7A'
andy@5A4d4en4s5$ar4s@#A4s7$ar'
andy@3A4d4en4s5$ar4s@#A4s@7A'
andy@-A4d4en4s@5A4s#$ar4s7$ar'
andy@BA4d4en4s@5A4s#$ar4s@7A'
andy@,A4d4en4s@5A4s@#A4s7$ar'
andy@"A4d4en4s@5A4s@#A4s@7A'
endmodule
G
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LOGIC SYMBOL AND TRUTH TABLE:
! # " DEMULTIPLE#ER TRUTH TABLE
%120T( *0T20T
&1 (7 (# DT 9
7 7
# 7 7 97
# 7 # 9#
# # 7 95
# # # 93
2/3@
"-
C/
3@
"-C-
3@"-C83@
"-C
3@
"-
*
2-
3@
"-
EN
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_____________________________________________________________________________________
RTL SCHEMATIC:
M
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SYNTHESIS REPORT6
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F %*s 6 8
Cell 0sage 6
F :&L( 6 -
F L0T- 6 -
F %* :uffers 6 8
F %:0 6 -
F *:0 6 -
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1o clocM signals found in this design
Timing (ummary6
(peed +rade6 ,
Ginimum period6 1o path found
Ginimum input arrival time $efore clocM6 1o path found
Ga!imum output reJuired time after clocM6 1o path found
Ga!imum com$inational path delay6 8.37"ns
Timing Detail6
ll values displayed in nanoseconds ns
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*:06%P* -.,75 y)5)*:0 y;5P
Total 8.37"ns B.8,"ns logic4 5.--7ns route
"7.,K logic4 5.-K route
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PRIORITY ENCODER
AIM:
To write VHDL R verilog program forpriority encoder 4simulate the program and verify the results.
APPARATUS:
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_____________________________________________________________________________________
Computer system
ilin! ".# software tool
PROCEDURE:
Double clic1 on ,%L%N, %2E %$3N.
$lic1 on 4le and ne0 pro'ect.
Enter the pro'ect name and location clic1 on next.
$hoose the settings # clic1 on next # 4nally clic1 on 4nish.
Double clic1 on create ne0 source.
$hoose VHDL module # enter the 4le name clic1 o next.
Enter the post name # 2elect the direction # clic1 on next # 4nish 4nally.
Write the program # clic1 on program name in source 0indo0.
$lic1 on5t6 %$3N of synthesis7xst then double clic1 on the chec1 syntax option.
3nce chec1 syntax is completed successfully+ you can go for simulation.
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$hoose sources for beha!ioral simulation and clic1 on the program name you 0ill
get model sim simulator option on the process 0indo0.
$lic1 on 596 icon of model sim simulator then double clic1 on simulator
beha!ioral simulation.
$lic1 on 9 ;33e the 0indo0 of 0a!eform.
?ight clic1 on the signal and select the force !alue.
$hange the !alue from 5@6 to either 5/6 or 5-6 and clic1 3A and clic1 on run icon #
similarly !ary the inputs !alue for all possible options and obser!e the output.
$lose the model sim simulator and come bac1 to implementation in the source
for options.
$lic1 on 596 icon of user constraints and double clic1 on Boor plan %D pre7
2ynthesis.
$lic1 on 5Ces6 and enter the pin numbers in the L3$ column and clic1 on sa!eicon and clic1 on 53A6.
Double clic1 on con4gure target de!ice # clic1 on yes.
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"urn on the po0er for the board and clic1 on 4nish.
"0o de!ices 0ill get identi4ed clic1 on bypass 0hen de!ices ,$(/82 is selected.
$lic1 on the 5.bit6 4le # select open 0hen de!ice ,$2// is selected and clic1
3A.
?ight clic1 on de!ice ,$2// and choose program option by clic1ing of right
clic1 and clic1 on 3A.
%mpact 0ill start to do0nload the 5bit6 4le to board.
3nce you got the program succeeded message +you can test the output on
board.
2ee the output ports by !arying the input ports.
G
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VHDL CODE 6
li$rary %&&&'
use %&&&.(TD)L*+%C)##,-.LL'
use %&&&.(TD)L*+%C)/%TH.LL'
use %&&&.(TD)L*+%C)01(%+1&D.LL'
entity encoder is
2ort d 6 in std)logic)vector" downto 7'
$ 6 out std)logic)vector5 downto 7'
end encoder'
architecture :ehavioral of encoder is
$egin
processd
$egin
case d is
when =7777777#=
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VERILOG CODE:
module encoderd4 en4 y'
input @"67A d'
input en'
output @567A y'
wire a4$4c'
ora4d@#A4d@3A4d@BA4d@"A'
or$4d@5A4d@3A4d@-A4d@"A'
orc4d@-A4d@BA4d@,A4d@"A'
andy@7A4a4en'
andy@#A4$4en'
andy@5A4c4en'
endmodule
RTL SCHEMATIC:
M
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SYNTHESIS REPORT:
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_____________________________________________________________________________________
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(elected Device 6 !a5sB7etJ#--,
1um$er of (lices6 , out of ",8 7K
1um$er of (lice lip lops6 3 out of #B3, 7K
1um$er of - input L0Ts6 ## out of #B3, 7K
1um$er of $onded %*:s6 ## out of #75 #7K
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Timing (ummary6
(peed +rade6 ,
Ginimum period6 1o path found
Ginimum input arrival time $efore clocM6 -.5"ns
Ga!imum output reJuired time after clocM6 ,.,#3ns
Ga!imum com$inational path delay6 1o path found
Timing Detail6
ll values displayed in nanoseconds ns
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L0T-6%#P* # 7.-,8 7.777 )n7777;7P )n7777;7P
LD6D 7."5- $)7
Total -.5"ns 5.-B"ns logic4 5.-"7ns route
-.K logic4 B7.#K route
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Total memory usage is 8--B5 Milo$ytes
1um$er of errors 6 7 7 filtered
1um$er of warnings 6 # 7 filtered
1um$er of infos 6 # 7 filtered
(%G0LT%*1 /&(0LT(
G
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8x1 MULTIPLE#ER
G
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AIM:
To write VHDL R verilog program for Gultiple!er4 simulate the program and verify the results
APPARATUS:
Computer system
ilin! ".# software tool
PROCEDURE:
Double clic1 on ,%L%N, %2E %$3N.
$lic1 on 4le and ne0 pro'ect.
Enter the pro'ect name and location clic1 on next.
$hoose the settings # clic1 on next # 4nally clic1 on 4nish.
Double clic1 on create ne0 source.
$hoose VHDL module # enter the 4le name clic1 o next.
Enter the post name # 2elect the direction # clic1 on next # 4nish 4nally.
Write the program # clic1 on program name in source 0indo0.
GG
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_____________________________________________________________________________________
$lic1 on5t6 %$3N of synthesis7xst then double clic1 on the chec1 syntax option.
3nce chec1 syntax is completed successfully+ you can go for simulation.
$hoose sources for beha!ioral simulation and clic1 on the program name you 0ill
get model sim simulator option on the process 0indo0.
$lic1 on 596 icon of model sim simulator then double clic1 on simulator
beha!ioral simulation.
$lic1 on 9 ;33e the 0indo0 of 0a!eform.
?ight clic1 on the signal and select the force !alue.
$hange the !alue from 5@6 to either 5/6 or 5-6 and clic1 3A and clic1 on run icon #
similarly !ary the inputs !alue for all possible options and obser!e the output.
$lose the model sim simulator and come bac1 to implementation in the source
for options.
$lic1 on 596 icon of user constraints and double clic1 on Boor plan %D pre7
2ynthesis.
G
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_____________________________________________________________________________________
$lic1 on 5Ces6 and enter the pin numbers in the L3$ column and clic1 on sa!e
icon and clic1 on 53A6.
Double clic1 on con4gure target de!ice # clic1 on yes.
"urn on the po0er for the board and clic1 on 4nish.
"0o de!ices 0ill get identi4ed clic1 on bypass 0hen de!ices ,$(/82 is selected.
$lic1 on the 5.bit6 4le # select open 0hen de!ice ,$2// is selected and clic1
3A.
?ight clic1 on de!ice ,$2// and choose program option by clic1ing of right
clic1 and clic1 on 3A.
%mpact 0ill start to do0nload the 5bit6 4le to board.
3nce you got the program succeeded message +you can test the output on
board.
2ee the output ports by !arying the input ports.
GM
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VHDL CODE
li$rary %&&&'
use %&&&.(TD)L*+%C)##,-.LL'
use %&&&.(TD)L*+%C)/%TH.LL'
use %&&&.(TD)L*+%C)01(%+1&D.LL'
entity multiple!er is
2ort s 6 in std)logic)vector5 downto 7'
d 6 in std)logic)vector" downto 7'
y4y# 6 out std)logic'
end multiple!er'
architecture :ehavioral of multiple!er is
$egin
process s4d
$egin
case s is when =777=
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VERILOG CODE:
module amu!veriloga4 s4 y'
input @"67A a'
input @567A s'
output y'
wire M4l4m4n4o4p4J4r4g4h4i'
notg4s@5A'
notg4s@#A'
noti4s@7A'
andM4a@7A4g4h4i'
andl4a@#A4g4h4s@7A'
andm4a@5A4g4s@#A4i'
andn4a@3A4g4s@#A4s@7A'
ando4a@-A4s@5A4h4i'
andp4a@BA4s@5A4h4s@7A'
andJ4a@,A4s@5A4s@#A4i'
andr4a@"A4s@5A4s@#A4s@7A'
ory4M4l4m4n4o4p4J4r'
endmodule
/
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_____________________________________________________________________________________
LOGIC SYMBOL AND TRUTH TABLE:
8#1 MULTIPLE#ER
TRUTH TABLE
INPUTS OUTPUT
EN S+ S1 S! DATA 9
7 7
# 7 7 7 7 7
# 7 7 # # #
# 7 # 7 5 5
# 7 # # 3 3
# # 7 7 - -
# # 7 # B B
# # # 7 , ,
# # # # " "
-
2/
3@"-
*/
3@
"-
*-
3@
"-
*8
3@
"-
*
3@
"- C
*
3@
"-*
3@
"-*G
3@
"-
*
3@
"-2-3@
"-28
3@
"-
EN
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE
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_____________________________________________________________________________________
RTL SCHEMATIC
8
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SYNTHESIS REPORT:
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(elected Device 6 !a5sB7etJ#--,
1um$er of (lices6 3 out of ",8 7K
1um$er of - input L0Ts6 , out of #B3, 7K
1um$er of $onded %*:s6 #3 out of #75 #5K
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_____________________________________________________________________________________
ll values displayed in nanoseconds ns
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1um$er of errors 6 7 7 filtered
1um$er of warnings 6 7 7 filtered
1um$er of infos 6 # 7 filtered
SIMULATION RESULTS
G
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RIPPLE CARRY ADDER:
AIM:
To write VHDL R verilog program for ripple carry adder 4 simulate the program and verify theresults
APPARATUS:
Computer system
ilin! ".# software tool
PROCEDURE:
Double clic1 on ,%L%N, %2E %$3N.
$lic1 on 4le and ne0 pro'ect.
Enter the pro'ect name and location clic1 on next.
$hoose the settings # clic1 on next # 4nally clic1 on 4nish.
Double clic1 on create ne0 source.
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$hoose VHDL module # enter the 4le name clic1 o next.
Enter the post name # 2elect the direction # clic1 on next # 4nish 4nally.
Write the program # clic1 on program name in source 0indo0.
$lic1 on5t6 %$3N of synthesis7xst then double clic1 on the chec1 syntax option.
3nce chec1 syntax is completed successfully+ you can go for simulation.
$hoose sources for beha!ioral simulation and clic1 on the program name you 0ill
get model sim simulator option on the process 0indo0.
$lic1 on 596 icon of model sim simulator then double clic1 on simulator
beha!ioral simulation.
$lic1 on 9 ;33e the 0indo0 of 0a!eform.
?ight clic1 on the signal and select the force !alue.
$hange the !alue from 5@6 to either 5/6 or 5-6 and clic1 3A and clic1 on run icon #
similarly !ary the inputs !alue for all possible options and obser!e the output.
M
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$lose the model sim simulator and come bac1 to implementation in the source
for options.
$lic1 on 596 icon of user constraints and double clic1 on Boor plan %D pre7
2ynthesis.
$lic1 on 5Ces6 and enter the pin numbers in the L3$ column and clic1 on sa!e
icon and clic1 on 53A6.
Double clic1 on con4gure target de!ice # clic1 on yes.
"urn on the po0er for the board and clic1 on 4nish.
"0o de!ices 0ill get identi4ed clic1 on bypass 0hen de!ices ,$(/82 is selected.
$lic1 on the 5.bit6 4le # select open 0hen de!ice ,$2// is selected and clic1
3A.
?ight clic1 on de!ice ,$2// and choose program option by clic1ing of right
clic1 and clic1 on 3A.
%mpact 0ill start to do0nload the 5bit6 4le to board.
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3nce you got the program succeeded message +you can test the output on
board.
2ee the output ports by !arying the input ports.
VHDL CODE:
entity rca is
porta6in std)logic )vector3 downto 7'
$6in std)logic)vector3 downto 7'
cin6in std)logic'
sum6out std)logic )vector3 downto 7'
cout6out std)logic'
end rca'
architecture rca of rca is
component fulladder is
port a4$4c6in std)logic'
sum4carry6out std)logic'
end component'
sgnal c6std)logic)vector5 downto 7'
$egin
f#6fulladder portmapa74$74cin4sum#74c7'
f56fulladder portmapa#4$#4c74sum##4c#'
f36fulladder portmapa54$54c#4sum#54c5'
f-6fulladder portmapa34$34c54sum#34cout'
end rca'
M/
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_____________________________________________________________________________________
,-. (o')* /o %((&e c)0 )dde
ulladder6
&ntity fulladder is
2orta4$4cin6in std)logic'
(um4carry6out std)logic'
&nd fulladder'
rchitecture $ehav of fulladder is
signal p4J4r4s46std)logic'
$egin
p;
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VERILOG CODE:
Godule rcaa4$4cin4sum4carry'
%nput@367Aa'
%nput@367A$'
%nput cin'
*uput@367Asum'
*utput carry'Sire !4y4?'
#cin4a@7A4$@7A4sum@7A4!'
5!4a@#A4$@#A4sum@#A4y'
3y4a@5A4$@5A4sum@5A4?'
-?4a@3A4$@3A4sum@3A4carry'
&nd module
,-. (o')* /o %((&e c)0 )dde
Godule fulladdera4$4cin4sum4carry'
%nput a4$4cin'
*utput sum4carry'
/eg p4J4t54t3'
lways a or $ or c
:egin
M8
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Ex. No: Date:
_____________________________________________________________________________________
(um
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_____________________________________________________________________________________
SYNTHESIS REPORT:
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F %*s 6 #3
Gacro (tatistics 6
F ors 6 3
F #$it !or3 6 3
Cell 0sage 6
F :&L( 6 "
F L0T5 6 #
F L0T3 6 -
F L0T- 6 5
F %* :uffers 6 #3
F %:0 6 8
F *:0 6 B
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1*T&6 TH&(& T%G%1+ 10G:&/( /& *1L9 (91TH&(%( &(T%GT&.
*/ CC0/T& T%G%1+ %1*/GT%*1 2L&(& /&&/ T* TH& T/C& /&2*/T
+&1&/T&D T&/ 2LC&and/*0T&.
ClocM %nformation6
1o clocM signals found in this design
Timing (ummary6
(peed +rade6 ,
Ginimum period6 1o path found
Ginimum input arrival time $efore clocM6 1o path found
Ga!imum output reJuired time after clocM6 1o path found
Ga!imum com$inational path delay6 ##.3-3ns
Timing Detail6
ll values displayed in nanoseconds ns
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Data 2ath6 num#;7P to carry
+ate 1et
Cell6inPout fanout Delay Delay Logical 1ame 1et 1ame
%:06%P* 3 7."" #.357 num#)7)%:0 num#)7)%:0
L0T-6%#P* 5 7.-,8 #.#B7 Eer-# 1-
L0T36%5P* 5 7.-,8 #.#B7 c5# c5
L0T36%7P* # 7.-,8 7.57 G!or)sum;3P)o;#P# sum)3)*:0
*:06%P* -.,75 sum)3)*:0 sum;3P
Total ##.3-3ns ,.873ns logic4 -.B-7ns route
,7.7K logic4 -7.7K route
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_____________________________________________________________________________________
UNIVERSAL COUNTER
AIM:
To write VHDL R verilog program for universal counter4 simulate the program and verify the
results
APPARATUS:
MM
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_____________________________________________________________________________________
Computer system
ilin! ".# software tool
PROCEDURE:
Double clic1 on ,%L%N, %2E %$3N.
$lic1 on 4le and ne0 pro'ect.
Enter the pro'ect name and location clic1 on next.
$hoose the settings # clic1 on next # 4nally clic1 on 4nish.
Double clic1 on create ne0 source.
$hoose VHDL module # enter the 4le name clic1 o next.
Enter the post name # 2elect the direction # clic1 on next # 4nish 4nally.
Write the program # clic1 on program name in source 0indo0.
$lic1 on5t6 %$3N of synthesis7xst then double clic1 on the chec1 syntax option.
3nce chec1 syntax is completed successfully+ you can go for simulation.
M
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$hoose sources for beha!ioral simulation and clic1 on the program name you 0ill
get model sim simulator option on the process 0indo0.
$lic1 on 596 icon of model sim simulator then double clic1 on simulator
beha!ioral simulation.
$lic1 on 9 ;33e the 0indo0 of 0a!eform.
?ight clic1 on the signal and select the force !alue.
$hange the !alue from 5@6 to either 5/6 or 5-6 and clic1 3A and clic1 on run icon #
similarly !ary the inputs !alue for all possible options and obser!e the output.
$lose the model sim simulator and come bac1 to implementation in the source
for options.
$lic1 on 596 icon of user constraints and double clic1 on Boor plan %D pre7
2ynthesis.
$lic1 on 5Ces6 and enter the pin numbers in the L3$ column and clic1 on sa!eicon and clic1 on 53A6.
Double clic1 on con4gure target de!ice # clic1 on yes.
/
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"urn on the po0er for the board and clic1 on 4nish.
"0o de!ices 0ill get identi4ed clic1 on bypass 0hen de!ices ,$(/82 is selected.
$lic1 on the 5.bit6 4le # select open 0hen de!ice ,$2// is selected and clic1
3A.
?ight clic1 on de!ice ,$2// and choose program option by clic1ing of right
clic1 and clic1 on 3A.
%mpact 0ill start to do0nload the 5bit6 4le to board.
3nce you got the program succeeded message +you can test the output on
board.
2ee the output ports by !arying the input ports.
Vd& code:
entity counter is
genericn6integer6
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end counter'
architecture :ehavioral of counter is
signal count 6std)logic)vectorn# downto 7'
$egin
processclM4reset4load4ud
$egin
ifclM#> and clM>event then
ifreset#>then
count;then
count;
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output @"67AJ'
reg@"67Acount'
alwaysposedge clM or posedge reset
$egin
ifreset
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SYNTHESIS REPORT:
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_____________________________________________________________________________________
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F ClocM :uffers 6 #
F :0+2 6 #
F %* :uffers 6 #
F %:0 6 ##
F *:0 6 8
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ClocM (ignal O ClocM $uffer name O Load O
NNN
clM O :0+2 O 8 O
NNN
Timing (ummary6
(peed +rade6 ,
Ginimum period6 -.8-Bns Ga!imum reJuency6 57,.38GH?
Ginimum input arrival time $efore clocM6 ".#,8ns
Ga!imum output reJuired time after clocM6 ,."--ns
Ga!imum com$inational path delay6 1o path found
Timing Detail6
ll values displayed in nanoseconds ns
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Data 2ath6 count)7 to count)"
+ate 1et
Cell6inPout fanout Delay Delay Logical 1ame 1et 1ame
D/(&6CPQ 5 7.5 #.#B7 count)7 count)7
L0T-)L6%#PL* # 7.-,8 7.777 count)inst)lut-)7# count)inst)lut-)7
G0C96(P* # 7.B#B 7.777 count)inst)cy)# count)inst)cy)#
G0C96C%P* # 7.7B8 7.777 count)inst)cy)5 count)inst)cy)5
G0C96C%P* # 7.7B8 7.777 count)inst)cy)3 count)inst)cy)3
G0C96C%P* # 7.7B8 7.777 count)inst)cy)- count)inst)cy)-
G0C96C%P* # 7.7B8 7.777 count)inst)cy)B count)inst)cy)B
G0C96C%P* # 7.7B8 7.777 count)inst)cy), count)inst)cy),
G0C96C%P* 7 7.7B8 7.777 count)inst)cy)" count)inst)cy)"
*/C96C%P* # 7.,-8 7.777 count)inst)sum)" count)inst)sum)"
D/(&6D 7."5- count)"
Total -.8-Bns 3.,Bns logic4 #.#B7ns route
",.3K logic4 53."K route
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+ate 1et
Cell6inPout fanout Delay Delay Logical 1ame 1et 1ame
%:06%P* 5 7."" #.#B7 load)%:0 load)%:0
%1V6%P* 8 7.-,8 5.7B7 count)inst)lut#)7#)%1V)7 count)inst)lut#)7
L0T-)L6%7PL* # 7.-,8 7.777 count)inst)lut-)7# count)inst)lut-)7
G0C96(P* # 7.B#B 7.777 count)inst)cy)# count)inst)cy)#
G0C96C%P* # 7.7B8 7.777 count)inst)cy)5 count)inst)cy)5
G0C96C%P* # 7.7B8 7.777 count)inst)cy)3 count)inst)cy)3
G0C96C%P* # 7.7B8 7.777 count)inst)cy)- count)inst)cy)-
G0C96C%P* # 7.7B8 7.777 count)inst)cy)B count)inst)cy)B
G0C96C%P* # 7.7B8 7.777 count)inst)cy), count)inst)cy),
G0C96C%P* 7 7.7B8 7.777 count)inst)cy)" count)inst)cy)"
*/C96C%P* # 7.,-8 7.777 count)inst)sum)" count)inst)sum)"
D/(&6D 7."5- count)"
Total ".#,8ns 3.,8ns logic4 3.577ns route
BB.-K logic4 --.,K route
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+ate 1et
Cell6inPout fanout Delay Delay Logical 1ame 1et 1ame
D/(&6CPQ 5 7.5 #.#B7 count)" count)"
*:06%P* -.,75 J)")*:0 J;"P
Total ,."--ns B.B-ns logic4 #.#B7ns route
85.K logic4 #".#K route
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Ex. No: Date:
_____________________________________________________________________________________
UNIVERSAL SHIFT REGISTER
-/-
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_____________________________________________________________________________________
AIM:
To write VHDL R verilog program for universal shift register 4 simulate the program and verify
the results
APPARATUS:
Computer system
ilin! ".# software tool
PROCEDURE:
Double clic1 on ,%L%N, %2E %$3N.
$lic1 on 4le and ne0 pro'ect.
Enter the pro'ect name and location clic1 on next.
$hoose the settings # clic1 on next # 4nally clic1 on 4nish.
Double clic1 on create ne0 source.
$hoose VHDL module # enter the 4le name clic1 o next.
Enter the post name # 2elect the direction # clic1 on next # 4nish 4nally.
-/8
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_____________________________________________________________________________________
Write the program # clic1 on program name in source 0indo0.
$lic1 on5t6 %$3N of synthesis7xst then double clic1 on the chec1 syntax option.
3nce chec1 syntax is completed successfully+ you can go for simulation.
$hoose sources for beha!ioral simulation and clic1 on the program name you 0ill
get model sim simulator option on the process 0indo0.
$lic1 on 596 icon of model sim simulator then double clic1 on simulator
beha!ioral simulation.
$lic1 on 9 ;33e the 0indo0 of 0a!eform.
?ight clic1 on the signal and select the force !alue.
$hange the !alue from 5@6 to either 5/6 or 5-6 and clic1 3A and clic1 on run icon #
similarly !ary the inputs !alue for all possible options and obser!e the output.
$lose the model sim simulator and come bac1 to implementation in the source
for options.
$lic1 on 596 icon of user constraints and double clic1 on Boor plan %D pre7
2ynthesis.
-/
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_____________________________________________________________________________________
$lic1 on 5Ces6 and enter the pin numbers in the L3$ column and clic1 on sa!e
icon and clic1 on 53A6.
Double clic1 on con4gure target de!ice # clic1 on yes.
"urn on the po0er for the board and clic1 on 4nish.
"0o de!ices 0ill get identi4ed clic1 on bypass 0hen de!ices ,$(/82 is selected.
$lic1 on the 5.bit6 4le # select open 0hen de!ice ,$2// is selected and clic1
3A.
?ight clic1 on de!ice ,$2// and choose program option by clic1ing of right
clic1 and clic1 on 3A.
%mpact 0ill start to do0nload the 5bit6 4le to board.
3nce you got the program succeeded message +you can test the output onboard.
2ee the output ports by !arying the input ports.
-/
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_____________________________________________________________________________________
VHDL CODE:
entity shiftreg is
2ort clM 6 in std)logic' dsr 6 in std)logic' drl 6 in std)logic' clr)l 6 in std)logic'
clM)l 6 in std)logic' s 6 in std)logic)vector# downto 7' d 6 in std)logic)vector3 downto 7'
J 6 inout std)logic)vector3 downto 7'
end shiftreg'
architecture :ehavioral of shiftreg is
$egin
processclM4s4clr)l
$egin
if clr)l7>then
J;'
elsif clM)l#>then
ifclM>event and clM#>then
case s is
when=77=
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_____________________________________________________________________________________
VERILOG CODE:
module shift C4 (%4 (*'
input C4(%'
output (*'
reg @"67A tmp'
always posedge C
$egintmp ;< tmp ;; #'
tmp@7A ;< (%'
end
assign (* < tmp@"A'
endmodule
port
C4 (%4 CL/ 6 in std)logic'
(* 6 out std)logic'
end shift'
-/G
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_____________________________________________________________________________________
RTL SCHEMATIC
-/
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_____________________________________________________________________________________
SYNTHESIS REPORT:
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F (hift /egisters 6 #
F 8$it shift register 6 #
Cell 0sage 6
F :&L( 6 5
F +1D 6 #
F VCC 6 #
F liplopsILatches 6 #
F D& 6 #
F (hifters 6 #
F (/L#,& 6 #
F ClocM :uffers 6 #
F :0+2 6 #
F %* :uffers 6 5
F %:0 6 #
F *:0 6 #
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_____________________________________________________________________________________
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_____________________________________________________________________________________
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Data 2ath6 (% to Gshreg)tmp;"P)srl)7
+ate 1et
Cell6inPout fanout Delay Delay Logical 1ame 1et 1ame
%:06%P* # 7."" 7.57 (%)%:0 (%)%:0
(/L#,&6D 7.B83 Gshreg)tmp;"P)srl)7
Total 5.377ns #.387ns logic4 7.57ns route
,7.7K logic4 -7.7K route
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_____________________________________________________________________________________
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE
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UNIVERSAL SHIFT REGISTER
AIM:
To write VHDL R verilog program for L04 simulate the program and verify the results
APPARATUS:
Computer system
,ilinx -.8 soft 0are tool
(pga board
PROCEDURE:
Double clic1 on ,%L%N, %2E %$3N.
$lic1 on 4le and ne0 pro'ect.
--
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE
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Enter the pro'ect name and location clic1 on next.
$hoose the settings # clic1 on next # 4nally clic1 on 4nish.
Double clic1 on create ne0 source.
$hoose VHDL module # enter the 4le name clic1 o next.
Enter the post name # 2elect the direction # clic1 on next # 4nish 4nally.
Write the program # clic1 on program name in source 0indo0.
$lic1 on5t6 %$3N of synthesis7xst then double clic1 on the chec1 syntax option.
3nce chec1 syntax is completed successfully+ you can go for simulation.
$hoose sources for beha!ioral simulation and clic1 on the program name you 0ill
get model sim simulator option on the process 0indo0.
$lic1 on 596 icon of model sim simulator then double clic1 on simulator
beha!ioral simulation.
--
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$lic1 on 9 ;33e the 0indo0 of 0a!eform.
?ight clic1 on the signal and select the force !alue.
$hange the !alue from 5@6 to either 5/6 or 5-6 and clic1 3A and clic1 on run icon #
similarly !ary the inputs !alue for all possible options and obser!e the output.
$lose the model sim simulator and come bac1 to implementation in the source
for options.
$lic1 on 596 icon of user constraints and double clic1 on Boor plan %D pre7
2ynthesis.
$lic1 on 5Ces6 and enter the pin numbers in the L3$ column and clic1 on sa!e
icon and clic1 on 53A6.
Double clic1 on con4gure target de!ice # clic1 on yes.
"urn on the po0er for the board and clic1 on 4nish.
"0o de!ices 0ill get identi4ed clic1 on bypass 0hen de!ices ,$(/82 is selected.
$lic1 on the 5.bit6 4le # select open 0hen de!ice ,$2// is selected and clic1
3A.
--G
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE
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?ight clic1 on de!ice ,$2// and choose program option by clic1ing of right
clic1 and clic1 on 3A.
%mpact 0ill start to do0nload the 5bit6 4le to board.
3nce you got the program succeeded message +you can test the output on
board.
2ee the output ports by !arying the input ports.
)rogram:
L%?*?C %EEEF
@2E %EEE.2"D_L3%$_--G.*LLF
@2E %EEE.2"D_L3%$_@N2%NED.*LLF
@2E %EEE.2"D_L3%$_*?%"H.*LLF
EN"%"C *L@ is
)ort a+b: in std_logic_!ector do0n to /=F
2el: in std_logic_!ector do0n to /=F
$in: in std_logicF
y: out std_logic_!ector do0n to /==F
end *L@F
*?$H%"E$"@?E eha!ior 3( *L@ %2
--
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE
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2ignal arith+logic: std_logic_!ector do0nto /=F
egin
0ith sel 8 do0nto /= select
arithKI a 0hen O///P+
a 9-0hen O//-P+
a7-0hen O/-/P+
b 0hen O/--P+
b9- 0hen O-//P+
b7- 0hen O-/-P+
a9b 0henP--/P+
a9b9cin 0hen othersF
0ith sel8 do0nto /= select
logicKI not a 0henP///P+
not b 0henP//-P+
a and b 0henP/-/P+
a or b 0henP/--P+
a nand b 0henP-//P+
a nor b 0henP-/-P+
a xor b 0henP--/P+
nota xor b= 0hen othersF
0ithsel= select
yKI arith 0hen 5/6+
--M
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logic 0hen othersF
end beha!iorF
?"L ?E)3?":
--
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_____________________________________________________________________________________
-8/
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE
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2CN"HE2%2 ?E)3?":
?elease -.8 7 xst 3.G-xd nt=
$opyright c= -78/-- ,ilinx+ %nc. *ll rights reser!ed.
77Q )arameter "
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE
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"*LE 3( $3N"EN"2
-= 2ynthesis 3ptions 2ummary
8= HDL $ompilation
= Design Hierarchy *nalysis
= HDL *nalysis
= HDL 2ynthesis
.-= HDL 2ynthesis ?eport
G= *d!anced HDL 2ynthesis
G.-= *d!anced HDL 2ynthesis ?eport
= Lo0 Le!el 2ynthesis
M= )artition ?eport
= (inal ?eport
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
IIIIIIIIIIIIIIIIIIIIIII
S 2ynthesis 3ptions 2ummary S
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
IIIIIIIIIIIIIIIIIIIIIII
7777 2ource )arameters
%nput (ile Name : T!_-M.pr'T
%nput (ormat : mixed
%gnore 2ynthesis $onstraint (ile : N3
-88
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE
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7777 "arget )arameters
3utput (ile Name : T!_-MT
3utput (ormat : N$
"arget De!ice : *utomoti!e $ool?unner8
7777 2ource 3ptions
"op
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Aeep Hierarchy : Ces
Netlist Hierarchy : *s_3ptimi>ed
?"L 3utput : Ces
Hierarchy 2eparator : R
us Delimiter : KQ
$ase 2peci4er :
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IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
IIIIIIIIIIIIIIIIIIIIIII
S Design Hierarchy *nalysis S
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
IIIIIIIIIIIIIIIIIIIIIII
*naly>ing hierarchy for entity K!_-MQ in library K0or1Q architectureK!_-MQ=.
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
IIIIIIIIIIIIIIIIIIIIIII
S HDL *nalysis S
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
*naly>ing Entity K!_-MQ in library K0or1Q *rchitecture K!_-MQ=.
Entity K!_-MQ analy>ed. @nit K!_-MQ generated.
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
IIIIIIIIIIIIIIIIIIIIIII
S HDL 2ynthesis S
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
IIIIIIIIIIIIIIIIIIIIIII
-8
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE
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)erforming bidirectional port resolution...
2ynthesi>ing @nit K!_-MQ.
?elated source 4le is T$:RDocuments and 2ettingsRmlecRte'uRpriorityencoder.!hdT.
@nit K!_-MQ synthesi>ed.
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
IIIIIIIIIIIIIIIIIIIIIII
HDL 2ynthesis ?eport
(ound no macro
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
IIIIIIIIIIIIIIIIIIIIIII
S *d!anced HDL 2ynthesis S
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
IIIIIIIIIIIIIIIIIIIIIII
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
IIIIIIIIIIIIIIIIIIIIIII
-8G
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*d!anced HDL 2ynthesis ?eport
(ound no macro
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
IIIIIIIIIIIIIIIIIIIIIII
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
IIIIIIIIIIIIIIIIIIIIIII
S Lo0 Le!el 2ynthesis S
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
IIIIIIIIIIIIIIIIIIIIIII
3ptimi>ing unit K!_-MQ ...
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
IIIIIIIIIIIIIIIIIIIIIII
S )artition ?eport S
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
IIIIIIIIIIIIIIIIIIIIIII
)artition %mplementation 2tatus
7777777777777777777777777777777
No )artitions 0ere found in this design.
-8
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE
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7777777777777777777777777777777
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
IIIIIIIIIIIIIIIIIIIIIII
S (inal ?eport S
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
IIIIIIIIIIIIIIIIIIIIIII
(inal ?esults
?"L "op Le!el 3utput (ile Name : !_-M.ngr
"op Le!el 3utput (ile Name : !_-M
3utput (ormat : N$
3ptimi>ation oal : 2peed
Aeep Hierarchy : Ces
"arget "echnology : *utomoti!e $ool?unner8
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE
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$ell @sage :
EL2 : 8
*ND8 : M
*ND : -
*NDM : 8
%NV : -
3?8 : G
3? : -
%3 uUers : -
%@( :
3@( :
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
IIIIIIIIIIIIIIIIIIIIIII
"otal ?E*L time to ,st completion: --.// secs
"otal $)@ time to ,st completion: --.- secs
"otal memory usage is -GGG8 1ilobytes
Number of errors : / / 4ltered=
Number of 0arnings : / / 4ltered=
Number of infos : / / 4ltered=
W*VE(3?
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE
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_____________________________________________________________________________________
?E2@L":
-/
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE
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P%o%20 ecode
AIM:
To write VHDL R verilog program for universal 2riority encoder 4 simulate the program and
verify the results
APPARATUS:
Computer system
,ilinx -.8 soft0are tool
(pga oard
PROCEDURE:
Double clic1 on ,%L%N, %2E %$3N.
$lic1 on 4le and ne0 pro'ect.
Enter the pro'ect name and location clic1 on next.
$hoose the settings # clic1 on next # 4nally clic1 on 4nish.
Double clic1 on create ne0 source.
--
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE
SINGRAYAKONDA
Ex. No: Date:
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$hoose VHDL module # enter the 4le name clic1 o next.
Enter the post name # 2elect the direction # clic1 on next # 4nish 4nally.
Write the program # clic1 on program name in source 0indo0.
$lic1 on5t6 %$3N of synthesis7xst then double clic1 on the chec1 syntax option.
3nce chec1 syntax is completed successfully+ you can go for simulation.
$hoose sources for beha!ioral simulation and clic1 on the program name you 0illget model sim simulator option on the process 0indo0.
$lic1 on 596 icon of model sim simulator then double clic1 on simulator
beha!ioral simulation.
$lic1 on 9 ;33e the 0indo0 of 0a!eform.
?ight clic1 on the signal and select the force !alue.
$hange the !alue from 5@6 to either 5/6 or 5-6 and clic1 3A and clic1 on run icon #
similarly !ary the inputs !alue for all possible options and obser!e the output.
-8
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE
SINGRAYAKONDA
Ex. No: Date:
_____________________________________________________________________________________
$lose the model sim simulator and come bac1 to implementation in the source
for options.
$lic1 on 596 icon of user constraints and double clic1 on Boor plan %D pre7
2ynthesis.
$lic1 on 5Ces6 and enter the pin numbers in the L3$ column and clic1 on sa!e
icon and clic1 on 53A6.
Double clic1 on con4gure target de!ice # clic1 on yes.
"urn on the po0er for the board and clic1 on 4nish.
"0o de!ices 0ill get identi4ed clic1 on bypass 0hen de!ices ,$(/82 is selected.
$lic1 on the 5.bit6 4le # select open 0hen de!ice ,$2// is selected and clic1
3A.
?ight clic1 on de!ice ,$2// and choose program option by clic1ing of right
clic1 and clic1 on 3A.
%mpact 0ill start to do0nload the 5bit6 4le to board.
-
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MALINENI LAKSHMAIAH ENGINEERING COLLEGE
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Ex. No: Date:
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3nce you got the program succeeded message +you can test the output on
board.
2ee the output ports by !arying the input ports.
)rogram:
library %EEEF
use %EEE.2"D_L3%$_--G.*LLF
use %EEE.2"D_L3%$_*?%"H.*LLF
use %EEE.2"D_L3%$_@N2%NED.*LLF
entity !_-M is
port
E%_L: in 2"D_L3%$F
%_L : in 2"D_L3%$_VE$"3? do0nto /=F
*_L : out 2"D_L3%$_VE$"3? 8 do0nto /=F
E3_L+ 2_L : out 2"D_L3%$ =F
end !_-MF