Nmos and Cmos Fabrication

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CMOS FABRICATION

LAYOUTS

22SCHEMATIC CROSS SECTION OF MOSFET

1.Gate Oxide and Field oxide layer:

Gate oxide is the layer below which channel is formed and Field oxide is for isolation of devices.

They are formed by using thermal oxidation: Provides highest quality oxides using lowest interface trap densities.

2. Dielectric layers:

For insulation between conducting layers and diffusion and ion implantation masks, for capping doped films to prevent loss of dopants, for passivation to protect devices from impurities, heat, moisture and contamination and scratches.

: CVD techniques

3. Poly silicon:

For gate electrode and contact material of shallow junctions etc.: CVD techniques.

4. Metallization:

For interconnections, ohmic contacts, etc. :PVD techniques.

Summary of Conventional Microfabrication Modules

• Basic Process Modules:

– Crystal growth, wafer fabrication– Semiconductor manufacturing, wafer cleaning and gettering– Lithography– Thermal Oxidation– Etching (Chemical , Plasma)– Ion Implantation– Diffusion– Physical Vapor Deposition PVD– Chemical Vapor Deposition CVD & Epitaxial Growth– Chemical Mechanical Polishing CMP

Narrow BG (0.66 eV)

High junction leakage currents

Operate up to 100°C

Intrinsic resistivity 47 Ohm-cm. Hence, HV rectifying devices not possible.

Germanium Oxide unsuitable for device applications

EGG more costly

GaAsGaAs

Difficult to grow high quality oxide

One element oxidizes faster to other, leaving a metallic phase at the interface

Difficult to dope

Difficult to get high crystal perfection and large diameters

Wide BG (1.1 eV)

Less junction leakage currents

Operate up to 150°C

Intrinsic resistivity = 2,30,000 Ohm-cm. Hence, High voltage rectifying devices are possible.

Si dioxide suitable for device applications (more planar)

EGS Cheap

Polysilicon Crystal structure

Si Crystal Structure

Create N-well(for PMOS devices) &Channel Stop Regions

Grow Field & Gate Oxide

Deposit & PatternPoly Layer

Implant S, D &Substrate Contacts

Create ContactWindows

Deposit & Pattern Metal Layer

Impurity Implant Into The Substrate.

Thick Around The nMOS And pMOS Active Regions And Thin Respectively Through Thermal Oxidation.

Creation Of n+ And p+ Regions.

Metallization

PHOTOLITHOGRAPHY

• IC Is Set Of Patterned Layers Of Doped Silicon, Polysilicon, Metal And SiO2.

• All Areas Are To Be Defined By Proper Masks.

• A Layer Must Be Patterned Before Another Is Applied On The Chip.

• Every Layer Will Undergo Lithography With Different Mask.

Si Substrate

SiO2SiO2

Si Substrate

SiO2 layer by thermal oxidation

Unpatterned Structure Photolithography Patterned Structure

Chemical or Dry Etch

Hardened Photoresist

Si SubstrateSi Substrate

Si Substrate1mm SiO2 layer by thermal oxidation

Si Substrate

Hardened PhotoresistSiO2 Window

reaching down toSi substrate

Light Sensitive, Acid Resistant Organic Polymer

= Photoresist

Si SubstrateHardened photoresist removed by stripping solvents.

Si Substrate Obtained Patterned SiO2 feature on the Si Substrate

UV LightGlass Mask

Si Substrate

Insoluble Photoresist For High Density Patterns Required In Sub Micron Devices, E-beam Lithography Is Used Instead Of Optical Lithography.Soluble Photoresistv

a) Positive photoresist b) Negative photoresist

PHOTORESISTS (not sensitive to λ> 0.5 microns)

Positive :

Exposed regions become more soluble. Hence , easily removed in the developing process.

Patterns formed are same as that of masks.

Consists of photosensitive compound, a base resin, and an organic solvent.

Initially photosensitive compound is insoluble in the developer solution.

After exposure, its chemical structure changes due to absorption of the radiations.

After development, exposed areas are removed.

Negative :

Exposed regions become less soluble. Hence , can’t be removed in the developing process.

Patterns are mirror images of the mask patterns.It consists of polymers combined with photosensitive

compound . Initially less insoluble in the developer solution.After exposure, its chemical structure changes due to

absorption of the radiations. Optical energy is converted into chemical one which

initiates a polymer cross linking reaction. Cross linked polymers have more molecular weight and

they become more insoluble in the developer solution. After development, unexposed areas are removed.Developer solution is absorbed here and there is

swelling of the resist mass. Hence limited resolution.

Fabrication of nMOS: Basic stepsThin high

quality Oxide Layer

(gate oxide)

Si Substrate

Deposition of polysilicon

(gate + interconnect medium)OXIDATION

Thick Oxide layer

(field oxide)Si Substrate

Patterned and etchedSELECTIVE ETCHING FOR DEFINING ACTIVE AREA ON WHICH MOSFET

WILL BE FABRICATED

polysilicongate oxideoxide

Patterned and etched

Fabrication of nMOS: Basic stepsInsulating oxide

Si Substrate

Bare Si surface to form S & D

Patterned and etchedDoping : Diffusion or

ion implantation

(high concentration of impurity atoms)

Contact windows for D & S

Fabrication of nMOS: Basic stepsEvaporated Aluminum

By creating another insulating oxide layer, cutting contact holes (via), depositing and patterning metal, two more layers of metallic interconnects can also be added on the top of this structure.

Patterned and etched

Metal contacts

CHALLENGES:

• Electrical isolation on a single chip containing many devices is necessary

• To prevent undesired conducting paths;• To avoid creation of inversion layers outside the

channels;• To reduce leakage currents.

DEVICE ISOLATION TECHNIQUES:I) ETCHED FIELD OXIDE ISOLATION:

Devices are created in dedicated regions called active areas.

Each active area is surrounded by thick oxide barrier called field oxide.

Thick oxide is grown on complete surface of the chip andthen selectively etched to define active areas.

Straight forward method.

Thickness of oxide leads to large oxide steps at the boundaries of active areas and isolation regions.

May lead to chip failure due to cracking of deposited layers due to large height difference at the boundaries.

DEVICE ISOLATION TECHNIQUES:II Local oxidation of silicon

LOCOS technique is based on the principle of selectively growing the field oxide in certain regions , instead of selectively etching away active areas after oxide growth.

For selective growth of oxide, active areas are covered with Silicon nitride.

DEVICE ISOLATION TECHNIQUES:LOCOSThin PAD OXIDE

(stress relief oxide)

Protects Si surface from stress caused by nitride during subsequent process steps.

Si Substrate

Si3N4(Patterned and etched)

Si Substrate

(Doping of exposed Si surface with p type impurity)

Si3N4 Si3N4

Si Substrate

p+ p+p+Isolation Regions

(Channel stop implants)

Si Substrate

p+p+ p+

Lateral extension under nitride layer

Si3N4 Si3N4Thick Field Oxide which partially

recesses into Si substrate

Bird’s beak

** Reduces active area

Si Substrate

p+p+ p+

THE ACTIVE AREAS(Patterned and etched)

LOCOS is popular :

More planar surface topology

Bird’s beak encroachment can be reduced up to some limit

by device scaling

DEVICE ISOLATION TECHNIQUES:III) MULTILEVEL INTERCONNECTS & METALLIZATION:

• 4 to 8 metal layers are used to create interconnections between the transistors and for routing the power supply, signal lines and clock lines on the chip surface.

• Allows higher integration densities. • Adds to the third dimension.• Electrical connections between the layers are made by vias.• Each via is formed by creating an opening in isolation oxide

before every metallization step and filling it with a special metal plug (Tungsten).

• After creation of via, new metal layer is deposited and subsequent patterning is done.

SOME FACTS:• Due to various process steps chip surface is highly

nonplanar.• It may inhibit local thinning and discontinuities at uneven

surface edges.• Deposition of multiple metal interconnect lines is not

desirable on such irregular topography.• They will lead to hills and valleys on the chip surface.• Hence surface is usually planarised before every new metal

deposition step.• For this, a fairly thick SiO2 layer is grown on the wafer

surface to cover all existing surface nonuniformities.• Its surface is then planarised by any one of:Glass reflow (heat treatment),Etch back,Chemical mechanical polishing (CMP).CMP: Actual polishing of wafer surface using abrasive silica

slurry.Adopted in recent years.

EXERCISE:*Epitaxial layer

** Difference between ion implantation and diffusion processes of doping.

*** Design masks for all patterning and etching steps in the fabrication of nMOS transistor for positive and negative photoresist material.

Nmos and Cmos Fabrication

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