Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 LECTURE 10: KEEE 4425 WEEK 8 CMOS FABRICATION PROCESS.

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Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005

LECTURE 10: KEEE 4425

WEEK 8

CMOS FABRICATION PROCESS

CMOS Manufacturing Process

(Courtesy: Prof. Kenneth Laker, U. Penn)

CMOS Process

p-p+ p+

A Modern CMOS Process

p-well n-well

gate-oxide

Tungsten

Dual-Well Trench-Isolated CMOS ProcessDual-Well Trench-Isolated CMOS Process

Patterning of SiO2

Si-substrate

Si-substrate Si-substrate

(a) Silicon base material

(b) After oxidation and depositionof negative photoresist

(c) Stepper exposure

PhotoresistSiO2

UV-light

Patternedoptical mask

Exposed resist

Si-substrate

(d) After development and etching of resist,chemical or plasma etch of SiO2

(e) After etching

(f) Final result after removal of resist

Hardened resist

Chemical or plasmaetch

CMOS Processing Technology

Latch-up problem

Silicon on insulator(SoI)

oxidation

opticalmask

processstep

photoresist coatingphotoresistremoval (ashing)

spin, rinse, dryacid etch

photoresist

stepper exposure

development

Typical operations in a single photolithographic cycle (from [Fullman]).

Photo-Lithographic Process

Images after Lithography

Patterning of SiO2

Si-substrate

Si-substrate Si-substrate

(a) Silicon base material

(b) After oxidation and depositionof negative photoresist

(c) Stepper exposure

PhotoresistSiO2

UV-light

Patternedoptical mask

Exposed resist

Si-substrate

(d) After development and etching of resist,chemical or plasma etch of SiO2

(e) After etching

(f) Final result after removal of resist

Hardened resist

Chemical or plasmaetch

Plasma Etch Tool

Dry Etching

Picture of Wafer After Nitride Etch

Picture of Wafer After Resist Strip

Etching

Etch Wafers in KOH(potassium hydroxide)

Wet etching

Single sided KOH Etch Apparatus

Picture of Wafer After KOH Etch

Deposit Polysilicon

Deposition

Picture of Wafer After Polysilicon Deposition

Hand Spinner Coat(photoresist coating)

Exposure Tools

Pattern Developing (hand develop)

Picture of Wafer After photolithography

Picture of Wafer After Polysilicon Etch

Sputter Aluminium

Wafer Saw

Photo cross-section of a transistor

Review Questions1. Described briefly technological steps required to

manufacture a CMOS inverter. Clearly specify masks used in each step. Give relevant sketches.

2. Give a brief explanation for the following CMOS process technologies:

(i) N-well(ii) P-well(iii) Twin well

3. Why do we need design rules.

4. Contrast the difference between micron rules and scalable

rules. Give one advantage for using each design rule type.

Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 LECTURE 10: KEEE 4425 WEEK 8 CMOS FABRICATION PROCESS.

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