EE-200

Lecture 8Made By:

Adnan Munawar

Edited by

Shoaib Muhammad

Sabeeta

SOFTWARES USED FOR DESGINING

DIP TRACE

PROTEUS-ISIS

PROTEUS-ARES

EXPRESS PCB

Discrete Components

Bread Board

Vero Board

PCB

Types of PCBs

Single Layer PCB

Double/Multiple Layer PCBs

Surface Mount PCBs

Some tips for designing layout

Make neat and clean layouts. Do not misseven the intricate details. Its easier to debuglater on.

Used LEDs or LED banks (bridged throughbuffers) for multiple I/O lines. Consider howeasy your debugging would become.

Keep the components at a good distance.DO NOT rush to make compact boards(Unlessyou are a professional circuit designer,ironically none of us are).

Some tips for designing layout

When making PCB for power componentsand inductive loads, keep them at a gooddistance from the logic components toprevent EMI effect.

Remember there are two types of ground orsinks:

Analog ground

Digital ground

Keep the ground traces of powercomponents thick

Some tips for designing layout

As so resistance increases and power

dissipation increases and heat increases

Do not pass the tracks between the pins of

ICS

ROUTING TIPS Right Angle Tracks

Avoid right angle tracks where possible as they

can cause issues with signal integrity. Also, on

finer tracks they can cause the trace to be

broken due to acid traps and erosion over time

T - Junctions

It is advisable to avoid T junctions as they lead to

signal integrity. They can also cause acid traps

on each side, which gives a higher chance of

causing an open circuit.

ROUTING TIPS

As because of charge acceleration an

EMI is produced and that corner start

acting as a source

ROUTING TIPS Loops

It is best to avoid loops where possible as they cancause a large amount of noise, which in turn canaffect the signal integrity of many tracks on yourboard. Also they cause inductance which canalso lead to increased noise.

Acute AnglesAcute angles during the routing of a PCB cancause acid traps. This is where the etching solutiongets trapped in the small corners and over timecan etch away the track which can lead to anopen circuit.

GENERIC CONTROLLER BOARD

NEATLY DESIGNED LAYOUT

A thing others wont know

Focus today!

TYPES OF PCB PACKAGES

A PCB packages is also called a Device

Footprint or an IC footprint.

I would like to divide them into two basic

types:

a. Through the Hole PCB Packages.

b. Surface Mount Packages.

TYPES OF PCB PACKAGES

These two packages are further divided

into many categories.

Keep in mind that the characterization of

footprints and their classification is done

on a variety of different factors.

Factors for Different

Classification

Pins Arrangement (Single in Line, Dual in Line, Grid, Quadrature etc.)

Distance between pins (Rows and Columns)

Pins shape and type (SMT, Through hole, Balls, J-Shaped etc.).

Mould Material (Plastic, Epoxy Resin etc.)

Die Material.

and many other..

Through the Hole Footprint

We shall discuss these first.

Through the Hole Footprint

Quite popular in the 60s, 70s and 80s.

Are and were easy to manufacture, in

terms of price and automation.

Take up more space.

Are heavier.

Single in Line Package (SIP)

Normally a distance of 0.1 Inch between

pins.

Dual in Line Package (DIP)

Again normally a distance of 0.1 inch

between row pins.

Dual in Line Package (DIP)

For Enthusiasts

Quad in Line Package (QIP)

Same distance between pins of a row as

DIL Package.

Lead or Pin Spacing Commonly found DIP packages use an inter-

lead spacing (lead pitch) of 0.1 inch (2.54 mm).

Row spacing varies depending on lead counts, with 0.3 in. (7.62 mm) or 0.6 inch (15.24 mm) the most common.

Less common standardized row spacing include 0.4 inch (10.16 mm) and 0.9 inch (22.86 mm), as well as a row spacing of 0.3 inch, 0.6 inch or 0.75 inch with a 0.07 inch (1.778 mm) lead pitch.

Comparison

Comparison

Variants of the DIP package

Several DIP variants for ICs exist, mostly distinguished by packaging material:

Ceramic Dual In-line Package (CERDIP or CDIP)

Plastic Dual In-line Package (PDIP)

Shrink Plastic Dual In-line Package (SPDIP) – A denser version of the PDIP with a 0.07 in. (1.778 mm) lead pitch.

Skinny Dual In-line Package (SDIP or SPDIP[4]) –Sometimes used to refer to a 0.3 in. wide DIP, normally when clarification is needed e.g. for a 24 or 28 pin DIP.

SMT (Surface Mount

Technology)

Started to take over the through hole packages around 80’s and 90’s.

Have won over the industry, almost replaced through the hole Packages in the industry (Not is school and universities)

Are relatively difficult to manufacture; cost and technology.

Can be used easily on automation plants auto soldering and placing

Are lighter and save a lot of space in circuit design.

Classes in the SMD with higher

terminal count.

RLC’s (2 terminals)

SOD (2 terminals).

SOT (3-8 terminals).

Dual in Line.

Quad in Line.

Grid Arrays.

Dual In Line SOIC: (Small-Outline Integrated Circuit), dual-in-line, 8 or more

pins, gull-wing lead form, pin spacing 1.27 mm

SOJ: Small-Outline Package, J-Leaded, the same as SOIC except J-leaded [2]

TSOP: Thin Small-Outline Package, thinner than SOIC with smaller pin spacing of 0.5 mm

SSOP: Shrink Small-Outline Package, pin spacing of 0.635 mm or in some cases 0.8 mm

TSSOP: Thin Shrink Small-Outline package.

QSOP: Quarter-Size Small-Outline package, with pin spacing of 0.635 mm

VSOP: Very Small Outline Package, even smaller than QSOP; 0.4, 0.5 mm or 0.65 mm pin spacing

DFN: Dual Flat No-lead, smaller footprint than leaded equivalent.

Quad in Line PLCC: Plastic Leaded Chip Carrier, square, J-lead, pin spacing 1.27 mm QFP: Quad Flat Package, various sizes, with pins on all four sides

LQFP: Low-profile Quad Flat Package, 1.4 mm high, varying sized and pins on all four sides

PQFP: Plastic Quad Flat-Pack, a square with pins on all four sides, 44 or more pins

CQFP: Ceramic Quad Flat-Pack, similar to PQFP MQFP: Metric Quad Flat Pack, a QFP package with metric pin

distribution

TQFP: Thin Quad Flat Pack, a thinner version of PQFP QFN: Quad Flat No-lead, smaller footprint than leaded equivalent LCC: Leadless Chip Carrier, contacts are recessed vertically to "wick-in"

solder. Common in aviation electronics because of robustness to mechanical vibration.

MLP (MLF): Micro Lead frame Package (Micro Lead-Frame package) with a 0.5 mm contact pitch, no leads (same as QFN) [3]

PQFN: Power Quad Flat No-lead, with exposed die-pad[s] for heat sinking

Grid Arrays PGA: Pin grid array. BGA: Ball Grid Array, with a square or rectangular array of solder balls on

one surface, ball spacing typically 1.27 mm LGA: An array of bare lands only. Similar to in appearance to QFN, but

mating is by spring pins within a socket rather than solder. FBGA: Fine pitch Ball Grid Array, with a square or rectangular array of

solder balls on one surface LFBGA: Low profile Fine pitch Ball Grid Array, with a square or

rectangular array of solder balls on one surface, ball spacing typically 0.8 mm

TFBGA: Thin Fine pitch Ball Grid Array, with a square or rectangular array of solder balls on one surface, ball spacing typically 0.5 mm

CGA: Column Grid Array, circuit package in which the input and output points are high temperature solder cylinders or columns arranged in a grid pattern.

CCGA: Ceramic Column Grid Array, circuit package in which the input and output points are high temperature solder cylinders or columns arranged in a grid pattern. The body of the component is ceramic.

μBGA: micro-BGA, with ball spacing less than 1 mm LLP: Lead Less Package, a package with metric pin distribution (0.5 mm

pitch).

Image

Image

Small Outline IC (SOIC)-DIP

Quad Flat Package (QFP)-QIP

Pin Grid Array (PGA)-GA

Land Grid Array (LGA)-GA

Ball Grid Array (BGA)-GA

THANK YOU!