P.Rajasekar & C.M.T.Karthigeyan Asst.Professor SRM University, Kattankulathur 1.

transcript

P.Rajasekar & C.M.T.KarthigeyanAsst.Professor

SRM University, Kattankulathur

The contents of the slides are solely for the purpose of teaching students at SRM University. All copyrights and Trademarks of organizations/persons apply even if not specified explicitly.

Synchronous Sequential Logic Introduction to sequential circuits Types of sequential circuits Storage elements Latches Flip-flops Sequential circuit analysis State tables

Design Procedure

A Sequential circuit contains: Storage elements:

Latches or Flip-Flops Combinational Logic: Implements a multiple-output

switching function Inputs are signals from the outside. Outputs are signals to the outside. Other inputs, State or Present State, are

signals from storage elements. The remaining outputs, Next State are

inputs to storage elements.

Combina-tionalLogic

Storage Elements

Inputs Outputs

StateNextState

Combinatorial LogicNext state function

Next State = f(Inputs, State)Output function (Mealy)

Outputs = g(Inputs, State)Output function (Moore)

Outputs = h(State) Output function type depends on specification

and affects the design significantly

Combina-tionalLogic

Storage Elements

Inputs Outputs

StateNextState

Depends on the times at which: storage elements observe their inputs, and storage elements change their state

Synchronous Behavior defined from knowledge of its signals

at discrete instances of time Storage elements observe inputs and can

change state only in relation to a timing signal (clock pulses from a clock)

Asynchronous Behavior defined from knowledge of inputs an

any instant of time and the order in continuous time in which inputs change

If clock just regarded as another input, all circuits are asynchronous!

Nevertheless, the synchronous abstraction makes complex designs tractable!

“Cross-Coupling” two NAND gates gives the S -R Latch:

Which has the time sequence behavior:

S = 0, R = 0 is forbidden as input pattern

QS (set)

R (reset) Q

R S Q Q Comment1 1 ? ? Stored state unknown1 0 1 0 “Set” Q to 11 1 1 0 Now Q “remembers” 10 1 0 1 “Reset” Q to 01 1 0 1 Now Q “remembers” 00 0 1 1 Both go high1 1 ? ? Unstable!

Cross-coupling twoNOR gates gives theS – R Latch:

Which has the time sequence behavior:

S (set)

R (reset)Q

R S Q Q Comment0 0 ? ? Stored state unknown0 1 1 0 “Set” Q to 10 0 1 0 Now Q “remembers” 11 0 0 1 “Reset” Q to 00 0 0 1 Now Q “remembers” 01 1 0 0 Both go low0 0 ? ? Unstable!

Adding two NANDgates to the basicS - R NAND latchgives the clockedS – R latch:

Has a time sequence behavior similar to the basic S-R latch except that the S and R inputs are only observed when the line C is high.

C means “control” or “clock”.

The Clocked S-R Latch can be described by a table:

The table describeswhat happens after theclock [at time (t+1)]based on: current inputs (S,R) and current state Q(t).

Q(t) S R Q(t+1) Comment

0 0 0 0 No change

0 0 1 0 Clear Q

0 1 0 1 Set Q

0 1 1 ??? Indeterminate

1 0 0 1 No change

1 0 1 0 Clear Q

1 1 0 1 Set Q

1 1 1 ??? Indeterminate

Adding an inverterto the S-R Latch,gives the D Latch:

Note that there areno “indeterminate”states!

Q D Q(t+1) Comment

0 0 0 No change

0 1 1 Set Q

1 0 0 Clear Q

1 1 1 No Change

The graphic symbol for aD Latch is:

The latch timing problem Master-slave flip-flop Edge-triggered flip-flop Standard symbols for storage elements Direct inputs to flip-flops

In a sequential circuit the changes should take place with clock transitions and not with levels.

Consists of two clockedS-R latches in serieswith the clock on the second latch inverted

The input is observedby the first latch with C = 1

The output is changed by the second latch with C = 0

The path from input to output is broken by the difference in clocking values (C = 1 and C = 0).

The behavior demonstrated by the example with D driven by Y given previously is prevented since the clock must change from 1 to 0 before a change in Y based on D can occur.

Use edge-triggering instead of master-slave

An edge-triggered flip-flop ignores the pulse while it is at a constant level and triggers only during a transition of the clock signal

Edge-triggered flip-flops can be built directly at the electronic circuit level, or

A master-slave D flip-flop which also exhibits edge-triggered behavior can be used.

The edge-triggered D flip-flop is thesame as the master-slave D flip-flop

It can be formed by: Replacing the first clocked S-R latch with a clocked D

latch or Adding a D input and inverter to a master-slave S-R flip-

flop The change of the D flip-flop output is associated

with the negative edge at the end of the pulse It is called a negative-edge triggered flip-flop

The edge-triggered flip-flop consists of two latches: master and slave.

Other types of flip-flops may be constructed from D flip-flop. Two other types less commonly used are JK and T flip flops.

General Model Current State

at time (t) is stored in an array offlip-flops.

Next State at time (t+1) is a Boolean function of State and Inputs.

Outputs at time (t) are a Boolean function of State(t) &(sometimes)Inputs (t).

Combina-tionalLogic

Inputs

StateNextState

Outputs

Storage Elements

Input: x(t) Output: y(t) State: ((A(t), B(t)) What is the Output Function?

What is the Next State Function?

State table – a multiple variable table with the following four sections: Present State – the values of the state

variables for each allowed state. Input – the input combinations allowed. Next-state – the value of the state at time

(t+1) based on the present state and the input. Output – the value of the output as a function

of the present state and (sometimes) the input. From the viewpoint of a truth table:

the inputs are Input, Present State and the outputs are Output, Next State

The state table can be filled in using the next state and output equations: A(t+1) = A(t)x(t) + B(t)x(t) B(t+1) =A (t)x(t) y(t) =x (t)(B(t) + A(t))

Present State Input Next State Output A(t) B(t) x(t) A(t+1) B(t+1) y(t)

0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 1 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1 0 0 0 1 1 1 1 1 0 0

2-dimensional table that matches well to a K-map. Present state rows and input columns in Gray code order. A(t+1) = A(t)x(t) + B(t)x(t) B(t+1) =A (t)x(t) y(t) =x (t)(B(t) + A(t))

Present State

Next State x(t)=0 x(t)=1

Output x(t)=0 x(t)=1

A(t) B(t) A(t+1)B(t+1) A(t+1)B(t+1) y(t) y(t) 0 0 0 0 0 1 0 0 0 1 0 0 1 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 0 1 0

Determine flip-flop input equations in terms of present state and inputs.

For each JKFF determine J=f(Q(t),x(t)) and K=g(Q(t),x(t))

Using the flip-flop characteristic table determine the next state values in the state table.

Substitute equations for J and K into Q(t+1)=JQ’+K’Q to calculate the values of next-states

Input equations for D-FF is obtained directly from next state

For JK and T FFs FF input equations cannot be obtained easily from state table.

A table that lists the inputs for a given change of state is needed.

It is called excitation table

A register capable of shifting the binary information held in each cell to its neighboring cell, is called a shift register.

Serial input is shifted to right with each clock pulse.After four clock pulses serial input appears

at the Serial output.

A digital system operates at serial mode: information transferred and manipulated one bit at a time.

Serial transfers take place with the system clock.

In the next clock contents of shift register A is transferred to shift register B.

Two binary numbers to be added are stored in two shift registers A and B.

The shift registers are shifted right starting with least significant bit, the bits are added by the full adder and carry is stored in a D flip-flop.

When the addition is completed the sum is in regiater A.

Serial adder will require n clock pulses for adding n-bit numbers. A parallel adder can perform the n-bit addition in one clock pulse period.

However a parallel adder will have n full adders.

Clear control Shift-right Shift left Parallel load Parallel

output

A register that goes through a prescribed sequence of states upon application of input pulses is called a counter.

A counter that follows binary number sequence is called a binary counter

n-bit binary counter consists of n flip-flops and count from 0 to 2^n-1.

Two categories: ripple counters and synchronous counters

In a ripple counter the clock input of flip-flops is connected to output of other flip flops

Ripple counters do not have a common clock (not synchronous circuit)

Synchronous counters have common clock connected to clock input of flip-flops

Chapter 6 - Fall 10 46

Chapter 6 - Fall 10 51

Charles H. Roth- Jr., Fundamentals of logic design, Thomson Asia,5th edition-2004 (CH1,CH2,CH3,CH4,CH5,CH6,CH7,CH9,CH11,CH12)

M. Morris Mano, Digital Logic and Computer Design, Prentice Hall of India

Floyd, Digital Fundamentals, Universal Book Stall, 3rd Edition,1986

Morris Mano, Digital Design, Prentice Hall of India, 2nd Edition 1991

Bigell & Donovan, Digital Electronics, Thomson Asia Pvt. Ltd., 4th Edition

1. State the difference between combinational circuits and sequential circuits?

2. What do you mean by Latches?3. Give the difference between latches

and flip flops?4. Define Flipflops?5. List the design procedures for

designing a sequential circuit?6. State the operation of S-R flipflop?7. State the operation of T-fliflop?8. State the features of clocked T flipflop?

9. Give the characteristics equation for S-R , T,J-K and D-flipflop?

10. What is a counter?11. What is a buffer register?12. List the types of shift register?13. How do you convert JR flipflop into D

flipflop?14. How do you convert T flipflop into D-

flipflop?15. Give the counter applications?

P.Rajasekar & C.M.T.Karthigeyan Asst.Professor SRM University, Kattankulathur 1.

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