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R. H. Richter et al - VERTEX 2002 Kailua-Kona, 05.11.2002
DEPFET sensorsDEPFET sensors for a LC vertex detector (1) for a LC vertex detector (1)
» DEP(leted)F(ield)E(ffect)T(ransistor) operation principles
» Results of pre-tests
» DEPFET prototype run
» Technology, simulation and design
» Wafer thinning
» Concept, first results
» Summary
L. Andriceka, P. Fischerb, K. Heinzingera, P. Lechnera, G. Lutza, I. Pericb, M. Reichec, R.H. Richtera, G. Schallera, M. Schneckea, F. Schoppera, H. Soltaua, L. Strüdera, J. Treisa, M. Trimplb, J. Ulricib, N. Wermesb
aMPI Halbleiterlabor Munich bUniv. of Bonn
cMPI für Mikrostrukturphysik Halle, Germany
R. H. Richter et al - VERTEX 2002 Kailua-Kona, 05.11.2002
DEPFET-PrinzipleDEPFET-Prinziple
FET integrated on high ohmic n-bulk
Collection of electrons within the internal gate
Modulation of the FET current by the signal charge!
p+
p+ n+
n
n+
totally depletedn --substrate
internal gate
rear contact
source top gate drain bulk potential via axistop-gate / rear contact
V
potential m inim umfor electrons
p-channel
p+
Radiation
-
-
- -+
+
++
-
-
~1m
~300 m
Advantages: Amplification of the charge at the position of collection=> no transfer loss
Full bulk sensitivity Non structured thin entrance window (backside) Very low input capacitance => very low noise
R. H. Richter et al - VERTEX 2002 Kailua-Kona, 05.11.2002
2 4 6
0
1000
2000
3000
4000
5000
6000
Escape - Peak
K
K
# Z
ähle
r
Energie [keV]
ENC = 4.8 +/- 0.1 e-
55Fe-spectra @ 300K
Excellent noise values measured on single pixels
BioScope - imaging of tracer-marked bio-medical samples
(P. Klein and W. Neeser)
Noise: ca. 70 ENC @ 300KSlow operation (old technology)Large arrays are impossible(JFET => VP variations)Large cell size
R. H. Richter et al - VERTEX 2002 Kailua-Kona, 05.11.2002
Rectangular DEPFET pixel Rectangular DEPFET pixel detectordetector
MOS transistor instead of JFET
A pixel size of ca. 20 x 20 µm² is achievable using 3µm minimum feature size.
R. H. Richter et al - VERTEX 2002 Kailua-Kona, 05.11.2002
DEPFETDEPFET pixel matrix pixel matrix
- Read filled cells of a row- Clear the internal gates of the row - Read empty cells
Low power consumption
Fast random access to specific array regions
R. H. Richter et al - VERTEX 2002 Kailua-Kona, 05.11.2002
DEPFET TechnologyDEPFET Technology
Double poly / double aluminum process on high ohmic n- substrate
along p-channel perpendicular to channel (with clear)
R. H. Richter et al - VERTEX 2002 Kailua-Kona, 05.11.2002
Self aligning TechnologySelf aligning Technology
Positions of all essential implantations are determined not by masks but by polysilicon layers
shallow channel implantation
- mandatory for rectangular cells (lateral channel definition)
- reduces parameter variations on the wafer
R. H. Richter et al - VERTEX 2002 Kailua-Kona, 05.11.2002
Technology – pre-testsTechnology – pre-tests
Motivation
o Low leakage current <-> new technology
o First MOS transistor parameters for the DEPFET and readout electronics design
o Process know how and design rules
Pre-tests:
Device test: Single poly, single Al, MOS technology on 300µm silicon
+ Numereous deposition, lithography and etching tests
R. H. Richter et al - VERTEX 2002 Kailua-Kona, 05.11.2002
Pretest results: Diode leakage currentsPretest results: Diode leakage currents
Reference diodes Pre-test diodes
IBulk =100pA/cm2 IBulk =100pA/cm2
R. H. Richter et al - VERTEX 2002 Kailua-Kona, 05.11.2002
Linear Linear MOS Transistors (self aligned technolgy)MOS Transistors (self aligned technolgy)
VGS = -4V...-7V @VB=10V
L=5µm L=7µm
R. H. Richter et al - VERTEX 2002 Kailua-Kona, 05.11.2002
Pixel prototype production (6“ wafer)Pixel prototype production (6“ wafer)for XEUS and LC (TESLA)for XEUS and LC (TESLA)
Many test arrays- Circular and linear DEPFETS up to 128 x 128 pixels minimum pixel size about 30 x 30 µm² - variety of special test structures
Aim: Select design options for an optimized array operation (no charge loss, high gain, low noise, good clear operation) On base of these results => production of full size sensors
Production will be finished in spring
purpose
detector format
pixel size
thickness
noise
readout time/ detector
/ row
particle tracking
1.3 x 10 cm² (x 8)
520 x 4000 pixels
(x 8)
2.1 Mpix (x8)
25 µm
50 µm
~ 100 el. ENC
50 µsec20 nsec
imaging spectroscopy
7.68 x 7.68 cm²
1024 x 1024 pixels
1 Mpix
75 µm
300 ... 500 µm
4 el. ENC
1.2 msec2.5 µsec
Active Pixel Sensor (rectangular)
• 2 pixels
30 x 30 µm²
• DEPFET
L = 5 µm
W = 18 µm
reduce the required read out speed by 2doubles the number of read out channels
R. H. Richter et al - VERTEX 2002 Kailua-Kona, 05.11.2002
Potential during collection - 3D Poisson equation (Poseidon)Potential during collection - 3D Poisson equation (Poseidon) (50µm thick Si, N (50µm thick Si, NBB=10=101313cmcm-3-3,V,VBackBack=-20V)=-20V)
Depth 10µmDepth 7µmDepth 4µmDepth 1µm
So
urce
sD
rain
External (internal) Gates
n+
cle
ar
con
tact
s
Cell size 36 x 27 µm²
R. H. Richter et al - VERTEX 2002 Kailua-Kona, 05.11.2002
Hiding the nHiding the n++-clear contacts-clear contacts
Depth 1µm
The positive Clear pulse removes the electrons from the Internal Gate and also pushs the holesout of the deep p cover region. After returning of theclear the deep p remains negatively charges forminga shield for the signal electrons.
R. H. Richter et al - VERTEX 2002 Kailua-Kona, 05.11.2002
Potential distribution during ReadingPotential distribution during Reading
Internal Gate
Drain
Source
Back contact
2D dynamic simulation along the channel
ID adjusted to 100µA (W/L =18µm/5µm)
Vinternal Gate ca. 3V
Localized charge generation simulates a hit
DEPFET simulation – TeSCA (2D, time dependent)
hit response to a generation of 1600 electron-hole pairs
TeSCA (2D, time dependent)Removal of 1600 electrons from the internal gate (VClear=15V)
Simulation of the Clear mechanism
Poseidon (3D Poisson equ.)Includes 3D effects => VClear=20V
R. H. Richter et al - VERTEX 2002 Kailua-Kona, 05.11.2002
Current production statusCurrent production status
Pixel array section – Design with clockable clear gatePixel array section – Design with clockable clear gate
N-side view with two polysilicon layers and contact openings
To do:
- P-side processing
- Metallization
Drain Gate
Clear
Cleargate
Source
1 Pixel cell
R. H. Richter et al - VERTEX 2002 Kailua-Kona, 05.11.2002
Processing thin detectorsProcessing thin detectors- the Idea -- the Idea -
R. H. Richter et al - VERTEX 2002 Kailua-Kona, 05.11.2002
Detector thinning – first resultsDetector thinning – first results
Wafer bonding – MPI f. Festkörperstrukturphysik, HalleWafer grinding – SICO GmbH, JenaAnisotropic etching – CiS gGmbH Erfurt, MPI Halbleiterlabor Munich
Thickness of detector region : 50µmof frame : 350µm
Size: 8cm x 1cm
R. H. Richter et al - VERTEX 2002 Kailua-Kona, 05.11.2002
SummarySummary
o DEPFET is promising detector candidate for future HE and astrophysics experiments. Key features: low noise, full bulk sensitivity, no charge transfer loss, low power consumption, random access within an array
o A new DEPFET technology (2 poly/ 2 aluminum) was developed for large arrays and high speed operation
o A DEPFET Prototype production has been started with DEPFET arrays with
30 x 30 µm² pixel size (TESLA) to 75 x 75 µm² XEUS
- Technology and device simulations are looking encouraging - Technological pre-tests show very good electrical parameters (leakage currents and MOS transistor characteristics)o A concept for merging the DEPFET technology with a thinning technology is
proposed
- thin mechanical detector samples were fabricatedo First wafers will be finished in spring ‘03
R. H. Richter et al - VERTEX 2002 Kailua-Kona, 05.11.2002
Processing thin detectorsProcessing thin detectors- Wafer bonding -- Wafer bonding -
10 “SOI” Wafer prepared by MPI für Microstrukturphysik, Halle
picture from: www.mpi-halle.mpg.deQ.-Y. Tong and U. Gösele “ Semiconductor Wafer Bonding ”
John Wiley & Sons, Inc.
≈1 cm/sec