Si CMOS for RF Power Applications

J. A. del AlamoMIT

Workshop on Advanced Technologies for Next Generation of RFIC2005 RFIC Symposium June 12, 2005

Sponsors: DARPA, IBM, SRC

RF power applications

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Frequency [GHz]

Out

put P

ower

[dB

m]

GaAs HEMTInP HEMTSi BJTSiGe HBTGaAs / InP HBTGaAs MESFETGaN HEMTLDMOSCMOS

Power vs. frequency

Compilation of research papers from IEEE Xplore

by J. Scholvin

Research activity by material and frequency

Compilation of research papers from IEEE Xplore by J. Scholvin

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r above 27 GHz3 to 27 GHzbelow 3 GHz

RF power technologies: 1993 vs. 2003

Compilation of research papers from IEEE Xplore by J. Scholvin

GaAs MESFET34%

InP HEMT12%

GaAs HBT12%

GaAs HEMT37% LDMOS

5%

1993

2003

SiC 3%

GaAs MESFET5%

GaN HEMT16%

InP HBT3%

InP HEMT3%

GaAs HBT16%

GaAs HEMT22%

CMOS16%

LDMOS5%

Si BJT3%

SiGe HBT10%

Silicon34%

RF Power Figures of Merit

• PA specs:

– Frequency

– Power– Gain– Linearity– Voltage– Reliability – Power efficiency– Cost

PA

Fundamental trade-off between voltage and frequency

scaling

Key to power: supply voltage

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0.001

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Vdd [V]

Pow

er D

ensi

ty [W

/mm

]

GaN HEMTGaAs & InP HBT

LDMOS

CMOS

GaAs MESFET

HEMT

Si BJTSiGe HBT

Compilation of research papers from IEEE Xplore by J. Scholvin

Wf

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Frequency [GHz]

Pow

er A

dded

Effi

cien

cy [%

]GaAs/InP HBTInP HEMTGaAs HEMTGaAs MESFETCMOSSiGe HBTLDMOS

Key to frequency: efficiency

Compilation of research papers from IEEE Xplore by J. Scholvin

The benefits of scaling

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0 0.2 0.4 0.6 0.8 1Lg [µm]

Pea

k P

AE

[%]

All FETs

27 GHz < f < 50 GHz

Compilation of research papers from IEEE Xplore by J. Scholvin

scaling

Si CMOS: a disruptive technology for RF power?

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Phy

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ngth

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III-V'sCMOSCMOS Roadmap

Gate length scaling in III-V FETs and CMOS

Compilation of research papers from IEEE Xplore

by J. Scholvin

Si MOSFETs for RF power

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Frequency [GHz]

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GaAs HEMTInP HEMTSi BJTSiGe HBTGaAs / InP HBTGaAs MESFETGaN HEMTLDMOSCMOS

1. Extending LDMOS beyond 2 GHz 2. RF power suitability of deeply scaled CMOS

1. Extending LDMOS beyond 2 GHz

(PhD Thesis of J. Fiorenza)SourceSource

• Two critical sources of RF Loss:– Gate resistance loss: reduces power gain– Substrate loss: reduces power efficiency

Drain

Gate

Drain

Gate

LDMOSFET: Lightly-doped Drain MOSFET

n+n-n+

Pn+

Source Drain

n-

Gaten+n-n+

Pn+

Source Drain

n-

Gate

n-

300 nm

50 nm50 nm

AlTiN

PolySiGate Oxide 20 or 30 nm

n-

300 nm

50 nm50 nm

AlTiN

PolySiGate Oxide 20 or 30 nm

Low-loss gate: Metal/Poly-Si damascene gate

Advantages:

– Implemented in the back end of process– Allows the use of Al or Cu: very low gate resistance– Self-aligned: no increase in overlap capacitance – Gate oxide undisturbed

Achieved: 0.2 ohm/sqr (>10 for polySi, ~1 for silic’d gate)

Metal/Poly-Si Damascene Gate

3 μm

Source

Gate Drain

200 μm

Lg = 0.6 μm ft ~ 15 GHz BVoff > 18 V

0.6 μm minimum Lg

10 mask levels

2 levels of metal

Fabricated at MIT

Test chip

Benefit of low gate resistance: small signal

Damascene gate increases fmax, enables wide gate fingers

Source

Source

Drain

Gat

e

Wf

Benefit of low gate resistance: large signal

High PAE with gate finger width up to 140 μm

Source

Source

Drain

Gat

e

Wf

Low-loss substrates: SOI and high-resistivity Si

Substrate:

• Regular Si

• High-resistivity Si

Handle wafer:

• Regular Si

• High-resistivity Si

Drain

Gate

Drain

Gaten+n-n+

Pn+

Source Drain

n-

Gate

n+n-n+

P n+

Source Drain

n-

Gate

Bulk Si Thin-film SOI

Drain

Gate

Drain

Gaten+n-n+

Pn+

Source Drain

n-

Gate

n+n-n+

Pn+

Source Drain

n-

Gate

n+n-n+

P n+

Source Drain

n-

Gate

Bulk Si Thin-film SOI

Impact of substrate

• SOI improves PAE• High-resistivity silicon improves PAE on bulk • High-resistivity silicon does not improve PAE on SOI

Beyond 2 GHz

Low-loss substrate very important at high frequencies

Analysis of substrate loss

Gate

Source

Drain Loss

Drain Pad

Pad Loss

• Pad Loss: • SOI effective

• HR effective on bulk Si and SOI

• Drain Loss:• SOI somehow effective

• HR very effective on bulk Si, only moderately on SOI

Why is HRSOI Ineffective?

Drain Pad

Gate

Source

HRSOI

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

RsubRsurf

Cbox

n+pn+

Surface inversion increases drain loss on HRSOI

Effect of substrate inversion in HRSOI-LDMOS

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VHS [V]

Pea

k P

AE

[%]

4.8 GHz

2.4 GHz

+- VHS

HRSOI

RFin RFout

Load-Pull Measurement

• Eliminating substrate inversion improves PAE• Most prominent at high frequencies

Impact of inversion layer elimination

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Bulk HR Bulk SOI HR SOI

Pea

k P

AE

[%]

Substrate

Enhancement due to elimination of inversion layer

f=1.9 GHz

Impact of inversion layer elimination

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peak

PA

E [%

]

VHS = 5.5 V

VHS = 0 V

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Gai

n [d

B]

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PA

E [%

]

f = 4.8 GHz36x40 µmVdd = 3.6 V Id = 10 mA

VHS=5.5 V

VHS=0 V

• Eliminating substrate surface effects improves performance:– Particularly prominent in LDMOS due to large drain area– Both linear and saturated performance– Most prominent at high frequencies

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GaAs HEMTInP HEMTSi BJTSiGe HBTGaAs / InP HBTGaAs MESFETGaN HEMTLDMOSCMOS

Si MOSFETs for RF power

1. Extending LDMOS beyond 2 GHz 2. RF power suitability of deeply scaled CMOS

2. RF power suitability of deeply scaled CMOS(PhD Thesis of J. Scholvin)

Attractiveness of CMOS:• System-on-Chip integration• Low cost• Low voltage• Good device models• Aggressive roadmap• Wide flavor of devices available

Suitable for:• High-volume, low cost consumer applications • Moderate frequencies (2-10 GHz)• Medium power (<100 mW)• Current: WLAN, Bluetooth, Cell-phone PA driver, WiMax/802.16

Picture from: http://www.intel.com/research/silicon/micron.htm#silicon

90 nm CMOS

• Concerns: CMOS scaling ⇒ Vdd ↓ ⇒ Pout ↓

• Possible solutions:– Raise Vdd ⇒ impact on reliability– Use I/O devices ⇒ not really scaling

Issues of CMOS for RF power

data for IEEE published CMOS PA devices and circuits

90 nm CMOS: there is a lot more than 90 nm devices!

• Includes devices with longer gate lengths and thicker gate oxides for I/O drivers and high V operation

• Designed RF power devices in collaboration with IBM

thick(51A)

medium(22 A)

thin (14 A)

Oxide thickness

2.51.21.0Nominal voltage [V]

xxxLg = 250 nmxxLg = 130 nm

xLg = 90 nm

The benefits of scaling for RF

• Logic devices at optimized bias point have very high bandwidth• But… power devices at class AB bias point have much less bandwidth

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Device type

f max

(GH

z)

power device

logic device

RF power performance ofstandard 90 nm devices

Vdd = 1 V, Id = 26 mA/mmf = 2.2 GHz48x16 µm (1 cell)8 x 48x16 (8 cell)

• 1 cell: Peak PAE = 66% at Pout = 12.5 dBm• 8 cell: Peak PAE = 59% at Pout = 20.2 dBm

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Pout [dBm]

Gai

n [d

B],

PA

E [%

]

Gain

PAE

1 cell8 cells

Linear performance of 90 nm CMOS

Vdd = 1 VId = 26 mA/mmfreq = 2.2 GHz8x48x16 µm

• What is PAE at a given IM3 ?– at IM3 = -35 dBc, PAE = 12% at Pout = 12 dBm

• Exceeds WCDMA PA driver specs

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dBc]IM3

PAE

WCDMA PA driver spec

-35 dBc

90 nm vs. 250 nm devices at 8 GHz

• At Vdd = 1 V, 90 nm has best PAE and Pout

• 250 nm device offers highest power density at Vdd=2.5 V

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ower

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sity

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t 1 m

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Lg = 90nm, Thin OxLg = 250nm, Thick Ox

Pout

freq = 8 GHzId = 26 mA/mm

PAE

90 nm vs. 250 nm

• 250 nm thick oxide device has higher Vds,sat⇒ compresses earlier and softer ⇒ lower Pout and peak PAE

• As Vdd ↑ impact of Vds,sat decreases

90 nm, thin oxide 250 nm, thick oxideVgs = 1V Vgs = 2.4V

0.1V steps 0.2V steps

What about reliability?

For RF power, reliability related to ratio of:

• nominal Vdd

• to breakdown voltage

For RF power:

• 90 nm device expected to be more reliable at Vdd=1 V than 250 nm device at 2.5 V

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Device type

BV o

ff, V

nom (V

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BVoff

Reliability: impact of output power

• Run device under continuous RF power conditions• Measure drop in gain over time, define MTTF as 0.2 dB drop• Power compression has huge impact on degradation

Vdd = 1.6 VId = 26 mA/mmf = 8 GHz48x16 μm

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Gai

n [d

B],

PA

E [%

]

Gain

PAE

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Cha

nge

in G

ain

[dB

]

Pout = 17.6 dBm

17.4 dBm

17.2 dBm

16.8 dBm

Reliability: impact of Vdd

• For same Vdd, thick oxide is more reliable– but thin oxide has better performance

• For identical lifetime, how does performance compare?

Impedances and RF power set for peak PAE

Id = 26 mA/mmfreq = 8 GHz

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Mea

n Ti

me

to F

ailu

re [h

ours

]

90 nmthin oxide

250 nmthick oxide

Reliability: impact of Vdd

Impedances and RF power set for peak PAE

Id = 26 mA/mmfreq = 8 GHz

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Mea

n Ti

me

to F

ailu

re [h

ours

]

90 nmthin oxide

250 nmthick oxide

• 90 nm thin ox. outperforms 250 nm thick ox. for high MTTF– Low Vdd performance of 90 nm device much better than 250 nm device

PAE=58%, Pout=16.8 dBmPAE=56%, Pout=15.6 dBm

Conclusions

• Metal-containing gates and low-loss substrates will project LDMOS to 5-6 GHz

• Deeply scaled CMOS suitable for RF power for:– Moderate power levels (~100 mW)– Very low operating voltage (~1 V and below)

• Scaling will project CMOS beyond 10 GHz

• Si-based RF power technologies will dominate many high-volume consumer applications:– WLANs, bluetooth, cellphone PA drivers, RF tags, etc

MIT’s RF power measurement setup

– 1.8 - 18 GHz Maury ATS automatic load-pull system– 8-inch Cascade on-wafer probe station– Synthesized source with 10 W TWT-PA supplying up to 200 mW at DUT

References

• LDMOS:– Bengtsson: MTT 2003– Fiorenza: SOI Conf. 1999; MTT-S 2001; IEDM 2002,

EDL 2001, 2003, 2005; TED 2002– Scholvin: IEDM 2003– Van der Heijden: MTT-S 2001

• 90 nm CMOS:– Ferndahl: MGWL 2003– Scholvin: IEDM 2004