SOFTWARE DEFINED RADIO BASED SPECTRUM ANALYZER WITH

HARDWARE ACCELERATION

TEAM DAEDALUSGEORGE MASON UNIVERSITY

VOLGENAU SCHOOL OF ENGINEERINGSENIOR DESIGN PROJECT FALL 2015

Faculty Supervisors

Dr. Kris Gaj

Dr. Brian Mark

Additional Advisors

Malik Umar Sharif

Team MembersRichard Haeussler - PMDaniel Barcklow –TMChristopher FortmanJoshua Herr

• Keysight N9343C

• Fixed set of features

• Total $16,901

• Limits undergraduate

exposure

Commercial Spectrum Analyzer

2

Antenna User Interface

Display: Amplitude vs. Frequency

70 MHz – 6 GHz

Large bandwidth

Near real-time performance

Touch screen interface

Potentially portable

Reprogrammable for different applications

Target Price: under $1000

Our Daedalus Spectrum Analyzer

3

Functional Decomposition

4

Hardware Decomposition

5

RF FRONT-END 6

Source: National Instruments, http://www.ni.com/tutorial/4805/en/

Sampling

7

Benefits:• Increases Bandwidth • Demodulation

Phase No Phase

Analog Device’s RF-transceiver: AD9364

8

Source: Analog Devices, AD9361 and AD9364

Source: Analog Devices, https://wiki.analog.com

PROCESSING SYSTEM 9

Zynq-7000 All Programmable SoC

Processing System

• Dual-core ARM Cortex –A9

• Up to 1 GHz

Programmable Logic

• Allows for parallel processing

• 85K Logic Cells

• 4.9 Mb Block RAM

Our current utilization = 31%

10

10

Source: http://www.zynqbook.com/

• Open source platform

• User friendly

• Extensively tested

• Supports multiple

development

environments and

applications

• Simpler initial development

• More difficult future development

• Less tested

• Does not fit well with our goals

Linux OS Bare Metal

11

PROGRAMMABLE LOGIC 12

• Computationally Intensive O(𝑁2)

– FFT O(𝑁 log 𝑁 )

• Frequency Resolution

– Large N is desirable

• Xilinx DFT IP Core

Discrete Fourier Transform(DFT)

13

Source: Oppenheim, Willsky, Nawab, “Signals and Systems”

Source: Xilinx DFT v4.0 LogiCORE IP Product Guide

DFT Implementation Using Xilinx Vivado

14

14

DFT Bit Packing

15

15

Controller and Datapath

16

16

Datapath

17

17

Controller

18

18

GNU RADIO 19

Software Defined Radio (SDR)

20

• Hardware components implemented with software

• GNU Radio is an SDR development tool

Source: National Instruments, http://www.ni.com/cms/images/devzone/tut/appframeworkusrprio.png

Source: GNU Radio http://gnuradio.org/redmine/projects/gnuradio/wiki

GNU Radio Companion

21

GRAPHICAL USER

INTERFACE

22

GUI Development

23

23

GQRX

24

24

PICTURE

Compiling Software for OsmoSDR

25

25

CHASSIS 26

Chassis

27

27

DEMONSTRATION 28

29

https://youtu.be/Dzr6LCWmviM

TESTING 30

Frequency tone Successful

70MHz ✓

300MHz ✓

800MHz ✓

1.0GHz ✓

1.5GHz ✓

2.0GHz ✓

3.0GHz ✓

4.0GHz ✓

4.4GHz ✓

Local Oscillator Testing

31

Testing of the Daedalus DFT core

32

Input signal

GNU Radio DFTconverter Output

33

Original GNU Radio

ADMINISTRATIVE 34

Component Price Status

AD-FMCOMMS4 $416.56 Purchased

ZedBoard* $495.00 Donation from Xilinx

Antenna $45.00 Purchased

Display $134.95 Purchased

SD card $15.00 Purchased

Chassis $35.00 Printed

Total funds spent $646.51 With Xilinx donation

With academic discount $965.51

Total Cost $1,141.51

*Academic discount available

Cost of Device

35

Team member Time in hours Focus

Richard Haeussler 525 RF, GNU Radio

Daniel Barcklow 700 FPGA, GNU Radio

Christopher Fortman 550 GUI, GNU Radio

Joshua Herr 600 Linux, Chassis

Total Hours 2375

Man Hours Spent

36

Focus Area Percent of man hours

Research 40%

Zynq – Programmable Logic 15%

GQRX Development 13%

Linux 10%

GNU Radio 7%

Documentation & Reporting 5%

Chassis 5%

Testing 5%

Breakdown of Man Hours

37

• Python, C, Matlab, C++, Octave, XML

• VHDL, Verilog

• Qt, CMake, Git, PyBombs, GNU Radio

• Linux Kernel Development

• Cross Compiling/embedded device development

• Xilinx Vivado, Xilinx SDK

• Networking

• DSP

Technical Skills (Learned)

38

• Dr. Kris Gaj and Dr. Brian Mark

• Malik Umar Sharif

• Dr. Pachowicz

• ECE Department

• Xilinx for the donation

Special Thanks To

39

COMMENTS/QUESTIONS? 40

We will be giving a live demo at the break!

APPENDIX 41

Vivado Testbench Result

42

43

36 72 108 216 480 600 720 960 1080 1200

0.0001

0.001

0.01

0.1

1

10

Transform Size (N)

Tim

e (m

s)FFT: Software vs. Hardware

Software

Hardware

44

• Allows for parallel processing– FFT

• Offload operations from processor

• Allows for higher sampling rates

• More samples

Programmable Logic

45