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Structure of Computer Structure of Computer SystemsSystems
Course 8Course 8
Memory systemMemory system
Memory – as main component of a Memory – as main component of a von Neumann computervon Neumann computer
Role:Role: stores instruction codes and datastores instruction codes and data
Basic types:Basic types: registers - contained in the CPUregisters - contained in the CPU
• register types: general purpose registers, instruction register, program register types: general purpose registers, instruction register, program counter, stack pointer, control and status registerscounter, stack pointer, control and status registers
• access – direct through internal links or busesaccess – direct through internal links or buses• access time – 1 clock period or lessaccess time – 1 clock period or less
internal or main memoryinternal or main memory• access: through the system bus – read/write transfer cyclesaccess: through the system bus – read/write transfer cycles• random access to every location, based on the location’s addressrandom access to every location, based on the location’s address• technology: semiconductor circuitstechnology: semiconductor circuits• access time: 1—70nsaccess time: 1—70ns
external memoryexternal memory• indirectly accessible through interfaces and system busindirectly accessible through interfaces and system bus• sequential or partially random access to blocks of memory (e.g. sectors)sequential or partially random access to blocks of memory (e.g. sectors)• technology: magnetic , optical, semiconductortechnology: magnetic , optical, semiconductor• access time: 0.1-10msaccess time: 0.1-10ms
Memory systemMemory system
New memory types:New memory types: Cache memory Cache memory
• high-speed low capacity memory between the CPU and the high-speed low capacity memory between the CPU and the internal memoryinternal memory
• keeps copies of the main memory’s zones (lines)keeps copies of the main memory’s zones (lines) Virtual memoryVirtual memory
• extension of the internal memory on the external memoryextension of the internal memory on the external memory• mechanisms for protecting memory zones allocated for mechanisms for protecting memory zones allocated for
different purposesdifferent purposes Memory hierarchy = Memory hierarchy =
• cache memorycache memory• internal memoryinternal memory• virtual memoryvirtual memory
Memory technologies Memory technologies (semiconductor technologies) (semiconductor technologies)
Basic classification:Basic classification: ROMROM
• non-volatile memorynon-volatile memory• types: ROM, PROM, EPROM, EEPROM, Flashtypes: ROM, PROM, EPROM, EEPROM, Flash
RAMRAM• volatile memoryvolatile memory• types:types:
Static RAM (SRAM):Static RAM (SRAM):• bipolar, CMOSbipolar, CMOS
Dynamic RAM (DRAM)Dynamic RAM (DRAM)• (basic) DRAM, FPM DRAM, EDRAM, SDRAM, (basic) DRAM, FPM DRAM, EDRAM, SDRAM,
DDRAM1, 2, 3, RAMBUS-DRAMDDRAM1, 2, 3, RAMBUS-DRAM
Memory design issuesMemory design issues Access:Access:
address-based:address-based:• random – every location can be accessed randomly based on its address random – every location can be accessed randomly based on its address
(e.g. RAM, ROM)(e.g. RAM, ROM)• sequential – the locations are read or written one after the other (magnetic sequential – the locations are read or written one after the other (magnetic
tape, CCD – charge coupled devices)tape, CCD – charge coupled devices) partial random – random at block level (e.g. sector) and sequential inside a partial random – random at block level (e.g. sector) and sequential inside a
memory block (e.g. magnetic and optical disk)memory block (e.g. magnetic and optical disk) associative – a location is found based on a tag (content) associated to associative – a location is found based on a tag (content) associated to
every locationevery location stack – a location is found on top of the stack – the stack pointer is stack – a location is found on top of the stack – the stack pointer is
automatically incremented or decremented for read and write operationsautomatically incremented or decremented for read and write operations Volatility:Volatility:
non-volatile memories – does not lose their content when the power is non-volatile memories – does not lose their content when the power is switched off (e.g. ROM, PROM, EEPROM, Flash)switched off (e.g. ROM, PROM, EEPROM, Flash)
volatile memories – lose their content without power supplyvolatile memories – lose their content without power supply• static memories – preserve the data as long as the circuit has power supply static memories – preserve the data as long as the circuit has power supply • dynamic memories – lose their content in time (e.g. DRAMs) even if power is dynamic memories – lose their content in time (e.g. DRAMs) even if power is
ON - requires periodic refresh cyclesON - requires periodic refresh cycles
Memory design issuesMemory design issues
communication:communication: through a parallel bus – address, data and control signalsthrough a parallel bus – address, data and control signals
• asynchronous bus – classical bus controlled through control signals asynchronous bus – classical bus controlled through control signals (e.g. 8086 bus)(e.g. 8086 bus)
• synchronous bus – controlled through the clock signal (e.g. P6 bus)synchronous bus – controlled through the clock signal (e.g. P6 bus) through a serial bus – serial transmission based on a protocol through a serial bus – serial transmission based on a protocol
(e.g. SPI, I2C)(e.g. SPI, I2C) trough an interface – indirect access (e.g. hard-disc interface) trough an interface – indirect access (e.g. hard-disc interface)
organization:organization: uniform access – every location accessed in the same wayuniform access – every location accessed in the same way non-uniform memory access (NUMA) – access depends on the non-uniform memory access (NUMA) – access depends on the
position of the memory relative to a given CPUposition of the memory relative to a given CPU
Memory system – basic conceptsMemory system – basic concepts
memory cell memory cell smallest storing unitsmallest storing unit preserves 1 logical variable – 1 bit (binary digit)preserves 1 logical variable – 1 bit (binary digit) usually, not directly accessibleusually, not directly accessible implementations:implementations:
• flip-flop (2,4, 6 transistors) - SRAMflip-flop (2,4, 6 transistors) - SRAM• a condenser (1 CMOS transistor) – DRAMa condenser (1 CMOS transistor) – DRAM• conductor/isolator – ROM, PROM, EPROM EEPROMconductor/isolator – ROM, PROM, EPROM EEPROM• magnetic polarization – magnetic discmagnetic polarization – magnetic disc• transparent/opaque surface – optical disctransparent/opaque surface – optical disc
memory locationmemory location a group of memory cells (8, 16, 32 bits) addressable as an individuala group of memory cells (8, 16, 32 bits) addressable as an individual addressing: unique address, incremental or sequential, associativeaddressing: unique address, incremental or sequential, associative a memory location has:a memory location has:
• an address and an address and • a contenta content
Memory system – basic conceptsMemory system – basic concepts Examples of memory cellsExamples of memory cells
sel
D
T
ROM
sel
D
T
PROM
Vcc
F
sel
D
T1
EPROM
PL
T2
sel/R
D
T3
sel/W
C
T1 T2
DRAM
DD
seli
SRAM
Memory system – basic conceptsMemory system – basic concepts
memory structure (block)memory structure (block) linear organization – locations placed one after the linear organization – locations placed one after the
other at ascending addressesother at ascending addresses
matrix organization – matrix organization – a location is at the intersection of a line a location is at the intersection of a line and a columnand a column
Address 0 1 2 3 4 5 ..FFD ..FFE ..FFF
....
....
....
....
....
....
....
0123
1..FF
Columns
Lines
1 2 3 4 ..FF
Dm Dm-1 Dm-2 ... D0 one location
Dm Dm-1 Dm-2 ... D0
one location
Memory system – basic conceptsMemory system – basic concepts Memory structureMemory structure
internal structure of a ROM or SRAM memory circuitinternal structure of a ROM or SRAM memory circuit
ComponentsComponents• address decoderaddress decoder
• memory locationsmemory locations
• data amplifierdata amplifier
• control unitcontrol unit
Address A0-An
...
DEC Memory locations
Control unitWrite signal Wr
or program
Chip select CS
Data D0-DmData Amp
Dir OE
Sel
Sel0Sel1
Memory system – basic conceptsMemory system – basic concepts Time diagrams for memory read and memory write cyclesTime diagrams for memory read and memory write cycles
A0-An
Read Memory Cycle
CS
Wr
D0-Dm
valid address
valid data
tcycletaccess
A0-An
Write Memory Cycle
CS
Wr
D0-Dm
valid address
valid data
tcycletaccess
Memory system – basic conceptsMemory system – basic concepts
Memory structureMemory structure internal structure of a DRAM memory circuitinternal structure of a DRAM memory circuit
DATA MUX
RAW DEC
RAW addr buf
Col addr buf
Column addr
RAW addr
RAW
Column
Address
Din Dout
RAS
CASControl
unit
Memory system – basic conceptsMemory system – basic concepts DRAM memory:DRAM memory:
Components:Components:• raw and column address buffersraw and column address buffers• raw address decoderraw address decoder• column data multiplexercolumn data multiplexer• memory locationsmemory locations• control unitcontrol unit
IssuesIssues• too many address linestoo many address lines• memory must be refreshed raw by rawmemory must be refreshed raw by raw
Solutions:Solutions:• address lines are multiplexed in time (half of the address pins address lines are multiplexed in time (half of the address pins
are needed)are needed)• two extra selection signals:two extra selection signals:
RAS – Raw address selectRAS – Raw address select CAS – Column address selectCAS – Column address select
• no chip select lineno chip select line• external refresh cyclesexternal refresh cycles
Memory system – basic conceptsMemory system – basic concepts Time diagram for DRAM memory read cycleTime diagram for DRAM memory read cycle
A0-An/2
Memory Read Cycle
Wr
D0-Dmvalid data
tcycletaccess
RAS
Raw Column
CAS
Memory system – basic conceptsMemory system – basic concepts
Time diagram for DRAM memory write cycleTime diagram for DRAM memory write cycle
A0-An/2
Memory Write Cycle
Wr
D0-Dmvalid data
tcycletaccess
RAS
Raw Column
CAS
Memory system – basic conceptsMemory system – basic concepts
Time diagram for DRAM memory refresh cycleTime diagram for DRAM memory refresh cycle
A0-An/2
Memory Refresh Cycle
Wr
D0-Dm
tcycle
RAS
Raw
CAS
Memory system – basic conceptsMemory system – basic concepts
Access timeAccess time one of the most important parameter of a memory one of the most important parameter of a memory
circuitcircuit measures the time required to perform a read or write measures the time required to perform a read or write
operationoperation measured from the moment when address lines are measured from the moment when address lines are
stable until the data is read or written in the memorystable until the data is read or written in the memory smaller access time => higher speedsmaller access time => higher speed ttaccessaccess = t = taddr_decaddr_dec + t + tcell_read/writecell_read/write + t + ten_ampen_amp
depends on capacity constant for a technology enable/disable time
Memory system – basic conceptsMemory system – basic concepts
Access time (cont)Access time (cont) depends on technologydepends on technology
• ROM – medium – 20-30 nsROM – medium – 20-30 ns• SRAM – small – 10-15nsSRAM – small – 10-15ns• DRAM – high – 70ns (basic DRAM); 10-15ns (DDRAM – block DRAM – high – 70ns (basic DRAM); 10-15ns (DDRAM – block
read)read)
Read/write cycle periodRead/write cycle period minimum time needed to perform a complete read or a write minimum time needed to perform a complete read or a write
operationoperation measured from the moment address signals are stable until the measured from the moment address signals are stable until the
address and data lines may be disabledaddress and data lines may be disabled Technology dependences:Technology dependences:
• constant time for SRAM, ROM; variable for DRAM (see refresh)constant time for SRAM, ROM; variable for DRAM (see refresh)• same for read and write – SRAM, DRAM; write is much longer – same for read and write – SRAM, DRAM; write is much longer –
Flash, EEPROMFlash, EEPROM
Memory system – basic conceptsMemory system – basic concepts Memory capacityMemory capacity
number of locations or bytesnumber of locations or bytes measured in kilo (k), mega (M), giga (G) or measured in kilo (k), mega (M), giga (G) or
terra (T) locations or bytesterra (T) locations or bytes capacity is dependent of technologycapacity is dependent of technology
• ROM, SRAM technologies:ROM, SRAM technologies: small capacity/chip – 64KB-4MBsmall capacity/chip – 64KB-4MB flash – 4-64GBflash – 4-64GB
• DRAM technologies:DRAM technologies: high capacity/chip – 2-8 GBhigh capacity/chip – 2-8 GB
New DRAM technologiesNew DRAM technologies
Why DRAM memories?Why DRAM memories? very big capacity/chip (1-4GB) at a reasonable pricevery big capacity/chip (1-4GB) at a reasonable price SRAMs cannot be implemented at such capacitiesSRAMs cannot be implemented at such capacities
Problems with DRAMs:Problems with DRAMs: require periodic refresh cyclesrequire periodic refresh cycles address multiplexingaddress multiplexing too long access time (70ns)too long access time (70ns)
Conclusions:Conclusions: most of today’s computers use DRAM circuits as their most of today’s computers use DRAM circuits as their
main memorymain memory we have to do something to reduce the access time we have to do something to reduce the access time
and to reduce the impact of extra refresh cycles and to reduce the impact of extra refresh cycles
New DRAM technologiesNew DRAM technologies FPM-DRAM FPM-DRAM
idea – one raw address and multiple column idea – one raw address and multiple column addresses – sequential block read/write:addresses – sequential block read/write:
• data1,2,4 – read; data3 – writedata1,2,4 – read; data3 – write
Raw Col1 Col2 Col3 Col4A0-An/2
RAS
CAS
Wr
D0-Dm data1 data2 data3 data4
taccess taccess taccess taccessNo delay for EDO-DRAM
New DRAM technologiesNew DRAM technologies
EDO-DRAM – Enable Data Output DRAMEDO-DRAM – Enable Data Output DRAM an extra output enable signal (OE) that eliminate the an extra output enable signal (OE) that eliminate the
delay between two consecutive columns (see delay between two consecutive columns (see previous diagram)previous diagram)
BEDO-DRAM Burst EDO-DRAMBEDO-DRAM Burst EDO-DRAM consecutive column addresses are generated inside consecutive column addresses are generated inside
the memory chip (no extra CAS cycles are needed)the memory chip (no extra CAS cycles are needed)
Time parameter DRAM FPM DRAM EDO DRAM
BEDO DRAM
SDRAM
First access time (ns) 70 50 50 52 50
Cycle time (ns) 100 30 20 15 10
Bus speed (MHz) 5 16-66 33-75 60-100 60-100+
New DRAM technologiesNew DRAM technologies
SDRAM – synchronous DRAMSDRAM – synchronous DRAM synchronous mode; every signal controlled by the synchronous mode; every signal controlled by the
processor’s clock signalprocessor’s clock signal memory organized on blocks that can work in parallelmemory organized on blocks that can work in parallel promotes burst data transfers (1,2,4, 8 or a whole page)promotes burst data transfers (1,2,4, 8 or a whole page) pipelined access to the memory; a new access may be pipelined access to the memory; a new access may be
initiated before the previous endedinitiated before the previous ended consecutive addresses generated inside the memory chipconsecutive addresses generated inside the memory chip access time is 4 times smaller than classic DRAMaccess time is 4 times smaller than classic DRAM
New DRAM technologiesNew DRAM technologies SDRAM – synchronous DRAM (cont.)SDRAM – synchronous DRAM (cont.)
Clock
Command
Address
Data
Read Nop Nop Nop Read Nop Nop
Dn Dn+1 Dn+2 Dn+3 Dm
Block n Block m
taccess
New DRAM technologiesNew DRAM technologies
DDR – SDRAM – Double Data Rate SDRAMDDR – SDRAM – Double Data Rate SDRAM makes data transfer on both edges of the clock signal (double makes data transfer on both edges of the clock signal (double
pumping) – reduces the required clock frequency to halfpumping) – reduces the required clock frequency to half very strict timing conditionsvery strict timing conditions 64 bit transfers64 bit transfers
DDR SDRAM Bus clock (MHz)
Internal Bus clock (MHz)
Prefetch(min burst)
Transfer Rate(MT/s)
Voltage
DDRDDR 100-200100-200 100-200100-200 2n2n 200-400200-400 2.52.5
DDR2DDR2 200-533200-533 100-266100-266 4n4n 400-1066400-1066 1.81.8
DDR3DDR3 400-1066400-1066 100-266100-266 8n8n 800-2133800-2133 1.51.5
Design of memory modulesDesign of memory modules Design parameters:Design parameters:
capacity:capacity:• in number of locations or bytesin number of locations or bytes
organization:organization:• bits/locationbits/location• addressing: random, sequential addressing (FIFO, LIFO), addressing: random, sequential addressing (FIFO, LIFO),
associativeassociative bus specifications:bus specifications:
• address and data signsaddress and data signs• control signalscontrol signals• timing (time diagrams)timing (time diagrams)
starting address:starting address:• place of the designed module in the addressing space of the place of the designed module in the addressing space of the
processorprocessor available circuitsavailable circuits special requirements (e.g. refresh, periodic access, etc.)special requirements (e.g. refresh, periodic access, etc.)
Design of ROM or SRAM memory Design of ROM or SRAM memory modulesmodules
Steps:Steps:1.1. build a sub-module with the required data build a sub-module with the required data
widthwidth
2.2. build the memory matrixbuild the memory matrix
3.3. design the address decoderdesign the address decoder
4.4. address amplifiersaddress amplifiers
5.5. data amplifiersdata amplifiers
6.6. control unit (if necessary) control unit (if necessary)
Design of a SRAM memory modulesDesign of a SRAM memory modules Design parameters:Design parameters:
Capacity: 1MbytesCapacity: 1Mbytes Organization: Organization: 16 bits with access on 8 bits too16 bits with access on 8 bits too The bus: The bus:
• ISA (24 address lines, 16 data lines, MRDC, MWTC)ISA (24 address lines, 16 data lines, MRDC, MWTC) Start address: C0000HStart address: C0000H Available circuits: 64KbytesAvailable circuits: 64Kbytes
Addresses sig Data
Sel
Addre
ss
Am
p.
Data
A
mp. Metrix of
memory circuites
Control circuit
Dec Module
selection
Command sig.
Building a sub-module with the required data Building a sub-module with the required data widthwidth
64K*8
64K*8
A1
A2
A16
WR\
CSHi\
CSLi\
D0
D1
D8
D7
D15
D9
Submodule 64K*16= 128K*8
Building the memory matrix with the Building the memory matrix with the required capacityrequired capacity
A1-A16 64K*16
64K*16
64K*16
…
D0-D15WR\CSL0\
CSH0\
CSH1\
CSH7\
CSL1\
CSL7\
512K*16=1M*8
Design of the decoder unitDesign of the decoder unit
CS0\
CS1\
CS7\
A17-A23
MRDC\, MWTC\
DEC DEC
SelMod\
74LS138
A17A18
A19
A23
A22
A21
A20
MRDC\
MWTC\
BHE\ A0
CSL0\
CSH0\
CSL7\
CSH7\SelMod\
Design of address and data amplifiersDesign of address and data amplifiers
74LS244
74LS244
74LS244
74LS245
74LS245
SelMod\RD\
SA0SA1
SA7
SA8SA9
SA15
SA16
SA23
A0A1
A7
A8A9
A15
A16
A23
SD0SD1
SD7
SD8SD9
SD15
D0D1
D7
D8D9
D15
Design of a DRAM memory moduleDesign of a DRAM memory moduleAddress bus Data bus
MUX 2:1 MUX Amp 2:1 DRAM
Refresh RAS
WCounter AdrSel CAS
WR\ CAS0 \,CAS1 \,….CASn
MRD\ Command RAS \
MWR\ device CAS \ CSM \ Oscilator
RefReq
DEC.
CS0 \, CS1 \, ..CSn