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Page 1 of 1 TOPRO CONFIDNETIAL 2003/7/28 Print
TP5208 64K SRAM
Echo Processor
D D D a a a t t t a a a S S S h h h e e e e e e t t t
Version: 1.0
Jun/2002
http://www.topro.com.tw
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SHNHN :
Room 802, Tower A, World Trade Plaza, Fahong Rd., Fatian, Shenzhen, China
²¦¥«ºÖ¥Ð°ÏºÖiô 9 ¹¥@ ¶T¼s³õ A ®y 802 «Ç (¶l½s¡G 518033) H.Q.: Tel:886-3-5632515 Fax:886-3-5641728
TPE.: Tel:886-2-25856858 Fax:886-2-25941104
SHENZ HEN:TEL:755-3679985 Fax:755-367951
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TP5208 64K SRAM
Echo Processor
Description
The TP5208 is a developed for producing echo effects added to voice signals picked up by
microphone for karaoke applications. The IC has the largest memory among the digital delay
series. As its design is aimed at high performance, it is best suited to provide radio cassette tape
recorders and miniature unit audio system with quality echo function.
Being pin compatible with the Mitsubishi M65831AP/FP, M65830CP/FP, and M65843AP/FP,
the TP5208 is suitable for upgrading the series.
Features
Built-in input/output filters, A-D and D-A converters and memory realize a delay system
with only a single chip
Capable of composing low-noise and low–distortion delay system at low cost by ADM
system (No= -88dB typ, THD=0.17% typ)
Control mode selections available from 2 kinds: easy mode using parallel data and
microcomputer mode using serial data
Sleep mode can be selected to stop IC functions Built-in automatic reset circuit
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TP5208 64K SRAM
Echo Processor
Pin Configuration
VDD 1 24 VCC
XIN 2 23 LPF1 IN
XOUT 3 22 LPF1 OUT
D1/REQ 4 21 OP1 OUT
D2/SCK 5 20 OP1 IN
D3/DATA 6 19 REF
D4/IDSW 7 18 CC1
TEST 8 17 CC2
EASY/U-COM 9 16 OP2 IN
SLEEP 10 15 OP2 OUT
D-GND 11 14 LPF2 IN
A-GND 12 13 LPF2 OUT
24 PINS DIP/SOP
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TP5208 64K SRAM
Echo ProcessorPin Description
No. Symbol Name I /O Function1. VDD Digital VDD ¢w Supply voltage2. XIN Oscillator input I
3. XOUT Oscillator input O Connects to 2MHz ceramic filter4. D1/REQ Delay1/Request I
Easy mode: inputs D1 dataU-COM mode: inputs request data
5. D2/SCK Delay2/Shift clock IEasy mode: inputs D2 dataU-COM mode: inputs shift clock
6. D3/DATA Delay3/Serial data IEasy mode : inputs D3 dataU-COM mode: inputs shift data
7. D4/IDSW Delay4/ID switch IEasy mode : inputs D4 dataU-COM mode: controls ID code
8. TEST Test I L= normal mode
9. EASY/U-COM EASY/U-COM I H= Easy modeL= U-COM mode
10. SLEEP Sleep IH= sleep modeL= normal mode
11. DGND Digital GNDConnects to analog GND at one point
12. AGND Analog GND Connects to analog GND
13. LPF2 OUT Low pass filter2 output O14. LPF2 IN Low pass filter2 input I
Forms low pass filter with external C, R
15. OP2 OUT OP-AMP2 output O16. OP2 IN OP-AMP2 input I
Forms integrator with external C.R
17. CC2 Current control 218. CC1 Current control 1
19. REF Reference = 1/2 VCC20. OP1 IN OP-AMP1 input I21. OP1 OUT OP-AMP1 output O
Forms integrator with external C, R
22. LPF1 OUT Low pass filter1 output O23. LPF1 IN Low pass filter1 input I
Forms low pass filter with external C, R
24. VCC Analog Vcc Supply voltage
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TP5208 64K SRAM
Echo Processor
Operation
1) EASY Mode (EASY / U-COM =H)
D4 D3 D2 D1 fs Td
L L L L 666 12.3
L L L H 666 24.6
L L H L 666 36.9
L L H H 666 49.2
L H L L 666 61.4
L H L H 666 73.7
L H H L 666 86.0
L H H H 666 98.3
H L L L 333 110.6
H L L H 333 122.9
H L H L 333 135.2
H L H H 333 147.5
H H L L 333 159.7H H L H 333 172.0
H H H L 333 184.3
H H H H 333 196.6
f s¡G Sampling Frequenct (KHz)
Td¡G Delay Time (msec)
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TP5208 64K SRAM
Echo Processor2) U-COM Mode (EASY / U-COM =L)
H Delay Time H ID Code= SLEEP Mode = MUTE
This Timing chart shows that delay time is set by serial data from U-COM.DATA signal is latched at the falling edge of SCK signal, the last ten data
are set at the rising edge of REQ signal when ID codes are satisfied.
ID1, ID3: L
ID2 : H
ID4 : equal to IDSW
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TP5208 64K SRAM
Echo Processor
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TP5208 64K SRAM
Echo Processor
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TP5208 64K SRAM
Echo Processor
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TP5208 64K SRAM
Echo Processor
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TP5208 64K SRAM
Echo ProcessorREQ, SCK, DATA Input Timing
Symbol Parameter Range Unitsmin typ max
t1 SCK Pulse Width 250 nsds SCK Pulse Duty 50 %
t2 DATA Setup Time 100 t1/2 ns
t3 DATA Hold Time 100 t1/2 ns
t4 REQ Hold Time 100 ns
t5 REQ Pulse Width 250 ns
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TP5208 64K SRAM
Echo Processor
3) MUTING
(a) EASY mode
Automatic mute upon changing delay time, cancelling SLEEP mode
and power-on.(b) U-COM mode
MUTE= H: mute
MUTE= L: automatic mute
Automatic Mute:
Delay Signal Before Change Mode Delay Signal After Change Mode
(a) Upon Changing Delay TimeDelay Signal
(b) Upon Cancelling SLEEP Mode
Delay Signal
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TP5208 64K SRAM
Echo Processor
Power On
(c) Upon Power-On
4) SLEEP Mode
SLEEP data is
H: clock and RAM stop to reduce circuit current (SLEEP mode)L: normal operation
5) System Reset
Automatically reset power-on. The reset time is about 120msec.
Delay time is set at 147.5msec.
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TP5208 64K SRAM
Echo Processor
Absolute Maximum Ratings (Ta=25¢J , unless otherwise noted)
Symbol Parameter Ratings Units
Vcc Supply Voltage 6.5 V
Icc Supply Current 100 mA
Pd Power Dissipation 1.7 W
Topr Operating Temperature -20~75 ¢J
Tstg Storage Temperature -25~125 ¢J
Recommended Operating Conditions
Symbol Parameters Range UnitsMin Typ Max
VCC Supply Voltage 4.5 5 5.5 V
VDD Supply Voltage 4.5 5 5.5 V
VCC-VDD Difference Voltage -0.3 0 0.3 V
fck Clock Frequency 1 2 3 MHz
VIH High Input Voltage 0.7VDD V
VIL Low Input Voltage 0.3VDD V
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TP5208 64K SRAM
Echo ProcessorElectrical Characteristics
(Vcc=5.0V¡A fin=1KHz¡A Vi=100mVrms¡A f ck =2MHz¡A Ta=25¢J , unless otherwise noted)
Symbol parameter Test Conditions Min Typ Max Units
Icc Circuit Current No Signal 36 50 mA
Gv Voltage gain R L=47K Ω -0.5 2.5 dB
VomaxMaximum Output
VoltageTHD=10% 1.0 1.6 Vrms
fs=666KHz 0.17 0.8 %THD Output Distortion
30KHzL.P.F. fs=333Khz 0.4 1.2 %
Upon Changing Delay Time¨ ¯
508 528 548 msTMUTE Mute Time
Upon Cancelling Sleep Mode 508 528 548 ms
No Output Noise Voltage DIN-AUDIO(fs=333KHz) -88 -80 dBV
D.C. Characteristics
RangeSymbol Parameters
Min Typ MaxUnits
Vcc Supply Voltage 4.5 5 5.5 V
Icc Supply Current 60 80 mA
VIH High Input Voltage 0.7VDD V
VIL
Low Input Voltage 0.3VDD
V
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TP5208 64K SRAM
Echo Processor
Application Circuit
EASY Mode
U-COM Mode
2 3 9876541
u-COM
24 23 22 21 1920 18 1617
10 11 12
1415 13
1u
22nF
0.01u 3k30k1u
10k10k
0.047u
47u 0.33u 0.33u
0.047u
22nF10k
2.2nF 2.7k
0.01u
1u
2.2nF
2M
Hz
620
0.1u100u 100p100p
10k
IN
OUT
V D D
X I N X O U T
R E Q
D A T A
S C K
T E S T
I D S W
C C 1
E A S Y / u_ c o m
V c c
A G N D
D G N D
S L E E P
L P F 1_ i n
O P 1_ o u
t
L P F 1_ o u t
O P 1_ i n R E
F
L P F 2_ o u t O
P 2_ o u
t
O P 2_ i n C
C 2
L P F 2_ i n
620
20k
2 3 9876541
SETING DELAY
TIME
24 23 22 21 1920 18 1617
10 11 12
1415 13
1u
22nF
0.01u 3k30k1u
10k10k
0.047u
47u 0.33u 0.33u
0.047u
22nF10k
2.2nF 2.7k
0.01u
1u
2.2nF
2M
Hz
620
0.1u100u 100p100p
10k
IN
OUT
V D D
X I N X O U T D
1 D 3
D 2
T E S T
D 4
C C 1
E A S Y / u_ c o m
V c c
A G N D
D G N D
S L E E P
L P F 1_ i n
O P 1_ o u
t
L P F 1_ o u
t O P 1_ i n R E
F
L P F 2_ o u
t
O P 2_ o u
t O P 2_ i n C
C 2
L P F 2_ i n
620
20k