Tri-Level-Cell Phase Change Memory (PCM): Toward an Efficient and

Reliable Memory System

Nak Hee Seong Sungkap Yeo Hsien-Hsin S. Lee

School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta, GA 30332

nakhee.seong@gmail.com {sungkap, leehs}@gatech.edu

Presented By:Anand DholeShalini Satre

ContentsPCMBackground and MotivationTri-Level-Cell (3LC) PCM3LC PCM in PracticeEvaluationConclusion

PCMBackground and MotivationTri-Level-Cell (3LC) PCM3LC PCM in PracticeEvaluationConclusion

Phase Change Memory (PCM)Promising alternative memory

technologyTwo states

◦Crystalline (SET)◦Amorphous (RESET)

Multi-level-cell PCM◦Intermediate states◦Store more data per cell

Single Level Cell (SLC) [1]

Low resistivityHigh resistivity

Set

Reset

SLC vs MLC

0

1

Two Storage Levels

2LC or SLC = one bit per cell

002

012

102

112

Four Storage Levels

4LC = two bits per cell

SLC PCM

103

# of Cells

SET RESETi

t

i

t

106

103 Difference

MLC PCM

1k

# of Cells

SET RESETi

t

i

t

1M

i

t

StorageLevel 0

StorageLevel 1

StorageLevel 2

StorageLevel 3

Error ModelCritical problems

◦Resistance Drift Resistance of PCM cell increases over time

◦Soft errors Not permanent failure Have solutions to resolve Soft error caused by resistance drift Error rate is proportional to initial resistance value Error rate is negligible in SLC PCM In MLC PCM, resistance drift at intermediate levels

◦ Iterative-writing mechanism Degrades write latency For 4LC, 4x~8x slower than that of SLC [1]

Resistance Drift [1]

# of Cells

SET RESET

T = 1

StorageLevel 0

StorageLevel 1

StorageLevel 2

StorageLevel 3

Decision Boundaries Programmed Boundaries

Resistance Drift

# of Cells

SET RESET

T = 2

StorageLevel 0

StorageLevel 1

StorageLevel 2

StorageLevel 3

Resistance Drift

# of Cells

SET RESET

T = 4

StorageLevel 0

StorageLevel 1

StorageLevel 2

StorageLevel 3

Resistance Drift

# of Cells

SET RESET

StorageLevel 0

StorageLevel 1

StorageLevel 2

StorageLevel 3

Drift-induced Soft Errors!!!

T = 8

Drifted ResistancePower Law Equation

IIdrift

IIdrift

t

tRtR

t

tRtR

101010 log log )(log

)(

Proposed SolutionProposed tri-level-cell PCM

◦Soft error rate matches that of DRAM◦Gain performance of SLC PCM

PCMBackground and MotivationTri-Level-Cell (3LC) PCM3LC PCM in PracticeEvaluationConclusion

Background and Motivation

Flash Memory w.r.t. PCM◦ Switching mem. ele. requires more voltage & time.◦ Degrades more rapidly◦ More susceptible to radiation

PCM w.r.t NAND◦ Better read/write latency.◦ Consumes significantly less read/write energy.

PCM Advantages◦ Higher information density.◦ Cheaper when in mass production.

Background and Motivation cont…MLC PCM

◦Many intermediate states between SET and RESET

◦E.g. 8LC PCM stores three bits per cell◦Soft error rate(SER) is higher than that

of DRAM ◦SER increases over time along with

resistance◦Error correction Methods

Time-aware error correction scheme Scrub mechanism

Background and Motivation cont…Time-aware error correction scheme [3]

◦Uses extra cells for storing predefined reference resistance values

◦While reading, reference values are used to compensate the resistance drift in corresponding cell.

◦Reduced SER from 10-3 ~ 10-1 to 10-4 ~ 10-2

Background and Motivation cont…Scrub Mechanism [2]

◦Reduced 99.6% of uncorrectable errors◦Memory controller spend more time in

scrubbingDRAM-style self refresh [3]

◦Cells with correct information also gets refreshed

◦Higher chip-level power◦Frequent write decreases lifespan◦Slower responsiveness

PCMBackground and MotivationTri-Level-Cell (3LC) PCM3LC PCM in PracticeEvaluationConclusion

3LC PCMEach cell has three storage levelsRemoved most error-prone state

from 4LC PCM i.e. Third storage level

Drift is proportional to resistanceRemoves errors generated by

third as well as most of the errors generated by second storage level

0

1

Two Storage Levels

2LC or SLC = one bit per cell

002

012

102

112

Four Storage Levels

4LC = two bits per cell

Binary System

03

13

23

Three Storage Levels

3LC

~ 1.5 bits per cell≠ three bits per cell

Ternary

System

3LC PCM

PCMBackground and MotivationTri-Level-Cell (3LC) PCM3LC PCM in PracticeEvaluationConclusion

3LC PCM4-level cell PCM

◦ unreliable

Tri-level cell PCM◦ Removing the most error-prone state

i

t

i

t

i

t

L0 L1 L2

Bandwidth Expanded 3LC PCM

# of Cells

SET RESETi

t

i

t

i

t

L0 L1 L2L1

i

t

or

Relaxing programming

range

Reducing programming

latency

Increasing write

bandwidth

Configuration variable of 4LC PCM Storage Levels

Data Log10 R α

µR ϭR µα ϭα

0 01 3.0

1/6

0.001

0.4 x µα

1 11 4.0 0.02

2 10 5.0 0.06

3 00 6.0 0.10

Storage Levels

Log10 R α

µR ϭR µα ϭα

0 3.01/6

0.0010.4 x µα1 4.0 0.02

2 6.0 0.10

Configuration variable of 3LC PCM

Efficient Conversion Method [1]In theory

11 bits of binary = 2048 states7 ternary cells = 2187 states~94% utilization

Proposed approach3 bits of binary = 8 states2 ternary cells = 9 states~89% utilizationNotation: <3,2> conversion

Number Mapping Method

00

1001

12

1102

21

20

22

000

100001 010

110011 101

111

Binary Ternary

ECC for Tri-Level-Cell PCM

Single Bit Error Single Bit Error

Binary Ternary

Legacy ECC for binary can be used• Simple (72, 64) Hamming Code• Memory controller requires minimal change

PCMBackground and MotivationTri-Level-Cell (3LC) PCM3LC PCM in PracticeEvaluationConclusion

Drift Induced Error Rate

ElapsedTime (s)

3LC PCM BE-3LC PCM

BE-3LC PCM

+ (72,64) ECC

215 (9 hours)

(too small)

(too small)

(too small)

220 (12 days)

(too small)

3.60E-16% (too small)

225 (1 year) (too small)

1.28E-10% 2.66E-15%

Information Density

0 2 4 6 81

01

21

41

61

82

02

22

42

62

83

03

2

0.80

1.00

1.20

1.40

1.60

1.80

2.00

BE3LC+ECC

2LC

4LC

3LC

Bit

s Pe

r C

ell

Number of Correctable Bits

Data block size- 256 bits

PCMBackground and MotivationTri-Level-Cell (3LC) PCM3LC PCM in PracticeEvaluationConclusion

Conclusion [1]Results (over 4LC PCM)

105 lower soft error rates 36.4% performance improvement

Results (over SLC PCM) 1.33x higher information density

References1) Nak Hee Seong, Sungkap Yeo, Hsien-Hsin S. Lee, "Tri-Level-Cell Phase

Change Memory: Toward an Efficient and Reliable Memory System",ISCA'13

2) M. Awasthi, M. Shevgoor, K. Sudan, B. Rajendran, R. Balasubramonian, and V. Srinivasan, “Efficient Scrub Mechanisms for Error-Prone Emerging Memories,” in Proceedings of the International Symposium on High Performance Computer Architecture, 2012.vol. 19, no. 8, pp. 1357–1367, 2011

3) W. Xu and T. Zhang, “A time-aware fault tolerance scheme to improve reliability of multilevel phase-change memory in the presence of significant resistance drift,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 8, pp. 1357–1367, 2011.

4) T. Nirschl, J. Phipp, T. Happ, G. Burr, B. Rajendran, M. Lee, A. Schrott, M. Yang, M. Breitwisch, C. Chen et al., “Write strategies for 2 and 4-bit multi-level phase-change memory,” in IEEE International Electron Devices Meeting (IEDM), 2007, pp. 461–464.

5) N. Papandreou, H. Pozidis, T. Mittelholzer, G. Close, M. Breitwisch, C. Lam, and E. Eleftheriou, “Drift-tolerant multilevel phase-change memory,” in 2011 3rd IEEE International Memory Workshop (IMW). IEEE, pp. 1–4.

6) R. Hamming, “Error detecting and error correcting codes,” Bell System Technical Journal, vol. 29, no. 2, pp. 147–160, 1950.