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VHDL Digital Full ADDER Logic Program
VHDL program for “Full Adder” behavioral design in Xilinx integrated software environment---------------------------------------------------------------------------------- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date:20:36:38 03/28/12-- Design Name:Full Adder Design -- Module Name:FullAdder1 - Behavioral-- Project Name:VHDL Program for "Full Adder" in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)-- Revision 0.01 - File Created-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;------------------------------------------------------------------------------------ Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;--------------------------------------------------------------------------------entity FullAdder1 is Port ( X : in std_logic; Y : in std_logic; CIN : in std_logic; SUM : out std_logic; CARRY : out std_logic);end FullAdder1;architecture Behavioral of FullAdder1 isbegin Process (X,Y,CIN) begin SUM <= X XOR Y XOR CIN; CARRY<=(X AND Y) OR (X AND CIN) OR (Y AND CIN); end process;end Behavioral;
VHDL Digital Full ADDER Logic using NAND Gate Program
VHDL program for “Full Adder” design using NAND Gate in Xilinx integrated software environment----------------------------------------------------------------------------------- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date:23:35:46 03/28/12-- Design Name:Full Adder Design -- Module Name:nand2 - Behavioral-- Project Name:VHDL Program for "Full Adder" using NAND Gate in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)-- Revision 0.01 - File Created-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;------------------------------------------------------------------------------------ Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;--------------------------------------------------------------------------------entity nand2 is Port ( L : in std_logic; M : in std_logic; N : out std_logic);end nand2;architecture Behavioral of nand2 isbegin Process (L,M) begin N <= L NAND M; end process;end Behavioral;---------------------------------------------------------------------------------- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date:23:21:04 03/28/12-- Design Name:Full Adder Design -- Module Name:FullAdder2 - Structure-- Project Name:VHDL Program for "Full Adder" using NAND Gate in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)-- Revision 0.01 - File Created
-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;------------------------------------------------------------------------------------- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;----------------------------------------------------------------------------------entity FullAdder2 is Port ( X : in std_logic; Y : in std_logic; CIN : in std_logic; SUM : out std_logic; CARRY : out std_logic);end FullAdder2;architecture Structure of FullAdder2 iscomponent NAND2 Port ( L : in std_logic; M : in std_logic; N : out std_logic);end component;signal T1, T2, T3, T4, T5, T6, T7: std_logic;begin N1 : NAND2 Port map(X,Y,T1); N2 : NAND2 Port map(X,T1,T2); N3 : NAND2 Port map(Y,T1,T3); N4 : NAND2 Port map(T2,T3,T4); N5 : NAND2 Port map(T4,T5,T6); N6 : NAND2 Port map(T4,T5,T6); N7 : NAND2 Port map(T6,T7,T7); N8 : NAND2 Port map(T6,T7,SUM); N9 : NAND2 Port map(T1,T5,CARRY);end Structure;
VHDL Degital Half ADDER Logic Using NAND Gate Program
VHDL program for “Half Adder” design using NAND Gate in Xilinx integrated software environment---------------------------------------------------------------------------------- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date:20:36:38 03/28/12-- Design Name: HalfAdder Design -- Module Name: HalfAdder3 - Structure-- Project Name:VHDL Program for "Half Adder" using NAND Gate in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)-- Revision 0.01 - File Created-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;------------------------------------------------------------------------------------- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;----------------------------------------------------------------------------------entity HalfAdder3 is Port ( X : in std_logic; Y : in std_logic; SUM : out std_logic; CARRY : out std_logic);end HalfAdder3;architecture structure of HalfAdder3 iscomponent NAND2 Port ( L : in std_logic; M : in std_logic; N : out std_logic);end component;signal T1, T2, T3, T4: std_logic;begin N1 : NAND2 Port map(X,Y,T1); N2 : NAND2 Port map(X,T1,T2); N3 : NAND2 Port map(T1,Y,T3); N4 : NAND2 Port map(X,Y,SUM); N5 : NAND2 Port map(X,Y,T4); N6 : NAND2 Port map(T4,T4,CARRY);end structure;
VHDL Digital Half ADDER Logic Program
VHDL program for “Half Adder” behavioral design in Xilinx integrated software environment---------------------------------------------------------------------------------- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date:20:36:38 03/28/12-- Design Name:Half Adder Design -- Module Name:HalfAdder1 - Behavioral-- Project Name:VHDL Program for "Half Adder" in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)-- Revision 0.01 - File Created-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;------------------------------------------------------------------------------------ Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;--------------------------------------------------------------------------------entity HalfAdder1 is Port ( X : in std_logic; Y : in std_logic; SUM : out std_logic;
CARRY : out std_logic);end HalfAdder1;architecture Behavioral of HalfAdder1 isbegin
Process (X,Y)begin
SUM <= X XOR Y; CARRY<=X AND Y; end process;end Behavioral;
VHDL program for “Half Adder” architectural design in Xilinx integrated software environment---------------------------------------------------------------------------------- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date:20:36:38 03/28/12-- Design Name: HalfAdder Design -- Module Name: HalfAdder2 - Architectural
-- Project Name:VHDL Program for "Half Adder" in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)-- Revision 0.01 - File Created-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;------------------------------------------------------------------------------------- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;----------------------------------------------------------------------------------entity HalfAdder2 is Port ( X : in std_logic; Y : in std_logic; SUM : out std_logic; CARRY: out std_logic);end HalfAdder2;architecture HalfAdder2_arch of HalfAdder2 isbegin process(X,Y) begin if(X/=Y) then SUM<='1'; else SUM<='0'; end if; end process; process(X,Y) begin if((X='1') and (Y='1')) then CARRY<='1'; else CARRY<='0'; end if; end process;end HalfAdder2_arch;
STRUCTURAL HALF ADDER-- half adder library ieee; use ieee.std_logic_1164.all; entity ha is port(a,b:in bit; sum,carry:out bit); end ha; architecture behav of ha is begin sum<= a xor b; carry<=a and b; end behav;
---vhdl code for 2 input or gate library ieee; use ieee.std_logic_1164.all; entity or2 is port(a,b:in bit; y:out bit); end or2; architecture behav of or2 is begin y<= a or b; end behav;
--compile the above vhdl codes then compile the below vhdl code --Fulladder using half adders library ieee; use ieee.std_logic_1164.all; use work.all; entity fa is port(a,b,cin:in bit; sum,cout:out bit); end fa; architecture struct_fa of fa is component ha port(a,b:in bit; sum,carry:out bit); end component; component or2 port(a,b:in bit; y:out bit); end component; signal x,y,z:bit; begin ha1: ha port map (a,b,x,y); ha2: ha port map (x,cin,sum,z); or1: or2 port map (z,y,cout); end struct_fa
VHDL Digital Full SUBSTRUCTURE Logic Program
VHDL program for “Full Substructure” behavioral design in Xilinx integrated software environment---------------------------------------------------------------------------------- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date:19:26:12 03/29/12-- Design Name: Full Substructure Design -- Module Name: SUB2 - Behavioral-- Project Name:VHDL Program for " Full Substructure " in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)-- Revision 0.01 - File Created-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;------------------------------------------------------------------------------------ Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;--------------------------------------------------------------------------------entity SUB2 is Port ( X : in std_logic; Y : in std_logic; BORROWIN : in std_logic; SUB : out std_logic; BORROWOUT : out std_logic);end SUB2;architecture Behavioral of SUB2 isbegin process (X,Y,BORROWIN) begin SUB <= X XOR Y XOR BORROWIN;BORROWOUT <= ((NOT X)AND Y)OR ((NOT X)AND BORROWIN) OR (Y AND BORROWIN); end process;end Behavioral;
VHDL Digital Half Substructure Logic Program
VHDL program for “Half Substructure” behavioral design in Xilinx integrated software environment-
-------------------------------------------------------------------------------
-- Company:Techno Global - Balurghat
-- Engineer:Mr. Jitaditya Mondal
-- Create Date: 19:09:27 03/29/12
-- Design Name: Half Substructure Design
-- Module Name: SUB1 - Behavioral
-- Project Name:VHDL Program for "Half Substructure " in XILINX Integrated Software Environment
-- Target Device:XC2S15
-- Tool versions:XST(VHDL/Verilog)
-- Revision 0.01 - File Created
-- Additional Comments:
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--------------------------------------------------------------------------------
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
--------------------------------------------------------------------------------
entity SUB1 is
Port ( X : in std_logic;
Y : in std_logic;
SUB : out std_logic;
BORROW : out std_logic);
end SUB1;
architecture Behavioral of SUB1 is
begin
process(X,Y)
begin
SUB <= X XOR Y;
BORROW<=(NOT X) AND Y;
end process;
end Behavioral;
VHDL program for “Half Substructure” architectural design in Xilinx integrated software environment-
-------------------------------------------------------------------------------
-- Company:Techno Global - Balurghat
-- Engineer:Mr. Jitaditya Mondal
-- Create Date:20:36:38 03/28/12
-- Design Name: Half Substructure Design
-- Module Name: HalfSub1 - Architectural
-- Project Name:VHDL Program for " Half Substructure " in XILINX Integrated Software Environment
-- Target Device:XC2S15
-- Tool versions:XST(VHDL/Verilog)
-- Revision 0.01 - File Created
-- Additional Comments:
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---------------------------------------------------------------------------------
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
----------------------------------------------------------------------------------
entity HalfSub1 is
Port ( X : in std_logic;
Y : in std_logic;
SUB : out std_logic;
BORROW : out std_logic);
end HalfSub1;
architecture HalfSub1_arch of HalfSub1 is
begin
process(X,Y)
begin
if(X=Y) then
SUB<='0';
end if;
if((X='1') and (Y='0')) then
SUB<='1';
else
BORROW<='1';
end if;
end process;
end HalfSub1_arch;
VHDL Digital N - Bit Full ADDER Logic Program
VHDL program for “N Bit Adder” behavioral design in Xilinx integrated software environment---------------------------------------------------------------------------------- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date:20:36:38 03/28/12-- Design Name:N Bit Adder Design -- Module Name:BitAdder2 - Behavioral-- Project Name:VHDL Program for "N Bit Adder" in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)-- Revision 0.01 - File Created-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;------------------------------------------------------------------------------------ Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;--------------------------------------------------------------------------------entity BitAdder2 isgeneric (N: natural :=2); Port ( X : in std_logic_vector(N-1 downto 0); Y : in std_logic_vector(N-1 downto 0); SUM : out std_logic_vector(N-1 downto 0); CARRY : out std_logic);end BitAdder2;architecture Behavioral of BitAdder2 issignal result: std_logic_vector(N downto 0);begin result <= ('0' & X)+('0' & Y); SUM <= result(N-1 downto 0); CARRY <= result(N);end Behavioral;
VHDL Digital 8 - Bit Full ADDER Program
VHDL program for “8 Bit Adder” behavioral design in Xilinx integrated software environment---------------------------------------------------------------------------------- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date:20:36:38 03/28/12-- Design Name:8 Bit Adder Design -- Module Name:BitAdder3 - Behavioral-- Project Name:VHDL Program for "8 Bit Adder" in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)-- Revision 0.01 - File Created-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;------------------------------------------------------------------------------------ Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;--------------------------------------------------------------------------------entity BitAdder3 isgeneric (N: natural :=2); Port ( X : in std_logic_vector(7 downto 0); Y : in std_logic_vector(7 downto 0); SUM : out std_logic_vector(7 downto 0); CARRY : out std_logic);end BitAdder3;architecture Behavioral of BitAdder3 issignal result: std_logic_vector(8 downto 0);begin result <= ('0' & X)+('0' & Y); SUM <= result(7 downto 0); CARRY <= result(8);end Behavioral;
VHDL Digital N - Bit Full SUBSTRUCTURE Logic Program
VHDL program for “N Bit Substructure” behavioral design in Xilinx integrated software environment---------------------------------------------------------------------------------- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date:20:36:38 03/28/12-- Design Name:N Bit Substructure Design -- Module Name: SUB3 - Behavioral-- Project Name:VHDL Program for "N Bit Substructure " in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)-- Revision 0.01 - File Created-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;------------------------------------------------------------------------------------ Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;--------------------------------------------------------------------------------entity SUB3 isgeneric(N: natural :=2); Port ( X : in std_logic_vector (N-1 downto 0); Y : in std_logic_vector (N-1 downto 0); SUB : out std_logic_vector (N-1 downto 0); BORROW : out std_logic);end SUB3;architecture Behavioral of SUB3 issignal result: std_logic_vector (N downto 0);begin result<=('0' & X)-('0' & Y); SUB <= result(N-1 downto 0); BORROW <= result(N);end Behavioral;
VHDL Digital 8 - Bit SUBSTRUCTURE Logic Program
VHDL program for “8 Bit Substructure” behavioral design in Xilinx integrated software environment---------------------------------------------------------------------------------- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date:20:36:38 03/28/12-- Design Name:8 Bit Substructure Design -- Module Name: SUB4 - Behavioral-- Project Name:VHDL Program for "8 Bit Substructure " in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)-- Revision 0.01 - File Created-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;------------------------------------------------------------------------------------ Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;--------------------------------------------------------------------------------entity SUB4 isgeneric(N: natural :=2); Port ( X : in std_logic_vector (7 downto 0); Y : in std_logic_vector (7 downto 0); SUB : out std_logic_vector (7 downto 0); BORROW : out std_logic);end SUB4;architecture Behavioral of SUB4 issignal result: std_logic_vector (8 downto 0);begin result<=('0' & X)-('0' & Y); SUB <= result(7 downto 0); BORROW <= result(8);end Behavioral;
VHDL Digital 1 - Bit ADDER logic Program
VHDL program for “1 Bit Adder” architectural design in Xilinx integrated software environment---------------------------------------------------------------------------------- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date:20:36:38 03/28/12-- Design Name:1 Bit Adder Design -- Module Name:BitAdder1 - Behavioral-- Project Name:VHDL Program for "1Bit Adder" in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)-- Revision 0.01 - File Created-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;------------------------------------------------------------------------------------ Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;--------------------------------------------------------------------------------entity BitAdder1 is Port ( X : in std_logic; Y : in std_logic; CIN : in std_logic; SUM : out std_logic; CARRY : out std_logic);end BitAdder1;architecture BitAdder1_arch of BitAdder1 isbegin process(X,Y) begin if (CIN='0') then if ((X AND Y)='1') then SUM <='0'; CARRY <= '1'; elsif ((X OR Y)='1') then SUM <='1'; CARRY <='0'; end if; elsif (CIN='1') then if ((X AND Y)='1') then SUM <='1';
CARRY <= '1'; elsif ((X OR Y)='1') then SUM <='0'; CARRY <='1'; end if; end if; end process;end BitAdder1_arch;
VHDL Digital OCT:BIN ENCODER Logic Program
VHDL program for “Octal To Binary Encoder” behavioral design in Xilinx integrated software environment---------------------------------------------------------------------------------- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date: 14:31:54 04/01/12-- Design Name: Octal To Binary Encoder Design -- Module Name: OCT2BIN - Behavioral-- Project Name:VHDL Program for " Octal To Binary Encoder Design" in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)-- Revision 0.01 - File Created-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;------------------------------------------------------------------------------------ Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;--------------------------------------------------------------------------------entity OCT2BIN is Port ( D : in std_logic_vector (7 downto 0); Y : out std_logic_vector (2 downto 0));end OCT2BIN;architecture Behavioral of OCT2BIN isbegin Y(0) <= D(1) OR D(3) OR D(5) OR D(7); Y(1) <= D(2) OR D(3) OR D(6) OR D(7); Y(2) <= D(4) OR D(5) OR D(6) OR D(7);end Behavioral;
VHDL Digital DEC:BCD ENCODER Logic Program
VHDL program for “Decimal To BCD Encoder” behavioral design in Xilinx integrated software environment---------------------------------------------------------------------------------- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date: 12:13:00 03/30/12-- Design Name: Decimal to BCD Encoder Design -- Module Name: ENC3 - Behavioral-- Project Name:VHDL Program for " Decimal to BCD Encoder Design" in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)-- Revision 0.01 - File Created-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;------------------------------------------------------------------------------------ Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;--------------------------------------------------------------------------------entity ENC3 is Port ( Q : in std_logic; R : in std_logic; S : in std_logic; T : in std_logic; U : in std_logic; V : in std_logic; W : in std_logic; X : in std_logic; Y : in std_logic; Z : in std_logic; OUT0 : out std_logic; OUT1 : out std_logic; OUT2 : out std_logic; OUT3 : out std_logic);end ENC3;architecture Behavioral of ENC3 isbegin process (Q,R,S,T,U,V,W,X,Y,Z) begin
OUT0 <= R OR T OR V OR X OR Z; OUT1 <= S OR T OR W OR X; OUT2 <= U OR V OR W OR X; OUT3 <= Y OR Z; end process;end Behavioral;Posted by Jitditya Mondal at 05:31
VHDL Digital 8:3 ENCODER Logic Program
VHDL program for “8:3 Encoder” behavioral design in Xilinx integrated software environment---------------------------------------------------------------------------------- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date: 12:13:00 03/30/12-- Design Name: 8:3 Encoder Design -- Module Name: ENC2 - Behavioral-- Project Name:VHDL Program for " 8:3 Encoder Design" in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)-- Revision 0.01 - File Created-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;------------------------------------------------------------------------------------ Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;--------------------------------------------------------------------------------entity ENC2 is Port ( S : in std_logic; T : in std_logic; U : in std_logic; V : in std_logic; W : in std_logic; X : in std_logic; Y : in std_logic; Z : in std_logic; OUT0 : out std_logic; OUT1 : out std_logic; OUT2 : out std_logic);end ENC2;architecture Behavioral of ENC2 isbegin process(S,T,U,V,W,X,Y,Z) begin OUT0 <= T OR V OR X OR Z; OUT1 <= U OR V OR Y OR Z; OUT2 <= W OR X OR Y OR Z;
end process;end Behavioral;
VHDL Digital 4:2 ENCODER Logic Program
VHDL program for “4:2 Encoder” behavioral design in Xilinx integrated software environment---------------------------------------------------------------------------------- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date: 12:13:00 03/30/12-- Design Name: 4:2 Encoder Design -- Module Name: ENC1 - Behavioral-- Project Name:VHDL Program for " 4:2 Encoder Design" in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)-- Revision 0.01 - File Created-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;------------------------------------------------------------------------------------ Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;--------------------------------------------------------------------------------entity ENC1 is Port ( W : in std_logic; X : in std_logic; Y : in std_logic; Z : in std_logic; OUT0 : out std_logic; OUT1 : out std_logic);end ENC1;architecture Behavioral of ENC1 isbegin process(W,X,Y,X) begin OUT0 <= X OR Z; OUT1 <= Y OR Z; end process;end Behavioral;
VHDL Digital PARITY ENCODER Logic Program
VHDL program for “Parity Encoder” behavioral design in Xilinx integrated software environment---------------------------------------------------------------------------------- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date: 12:13:00 03/30/12-- Design Name: Parity Encoder Design -- Module Name: ENC4 - Behavioral-- Project Name:VHDL Program for " Parity Encoder Design" in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)-- Revision 0.01 - File Created-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;------------------------------------------------------------------------------------ Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;--------------------------------------------------------------------------------entity ENC4 is Port ( W : in std_logic; X : in std_logic; Y : in std_logic; Z : in std_logic; OUTP : out std_logic; OUT1 : out std_logic; OUT2 : out std_logic);end ENC4;architecture Behavioral of ENC4 isbegin process (W,X,Y,Z) begin OUTP <= W OR X OR Y OR Z; OUT1 <= X OR Z; OUT2 <= Y OR Z; end process;end Behavioral;
VHDL Digital D - -Flip Flop Program
VHDL program for “D – Flip Flop Design” Behavioral design in Xilinx integrated software environment----------------------------------------------------------------------------------- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date: 19:00:36 04/01/12-- Design Name: D FlipFlop Design -- Module Name: DFF1 - Behavioral-- Project Name:VHDL Program for "D FlipFlop Design" in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)-- Revision 0.01 - File Created-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;------------------------------------------------------------------------------------ Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;--------------------------------------------------------------------------------entity DFF1 is Port ( D : in std_logic; CLK : in std_logic; Q : out std_logic; QN : out std_logic);end DFF1;architecture Behavioral of DFF1 isbegin process (CLK) begin if CLK = '1' then Q <= D; QN <= NOT D; end if; end process;end Behavioral;
VHDL program for “D – Flip Flop Design” Behavioral design in Xilinx integrated software environment----------------------------------------------------------------------------------- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date: 19:08:41 04/01/12-- Design Name: D FlipFlop Design -- Module Name: DLATCH2 - Behavioral-- Project Name:VHDL Program for "D FlipFlop Design" in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)-- Revision 0.01 - File Created-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;------------------------------------------------------------------------------------ Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;--------------------------------------------------------------------------------entity DLATCH2 is Port ( DATAIN : in std_logic; ENABLE : in std_logic; DATAOUT : out std_logic);end DLATCH2;architecture Behavioral of DLATCH2 is begin process(DATAIN, ENABLE) begin if (ENABLE='1') then DATAOUT <= DATAIN; end if; end process;end Behavioral;
VHDL program for “D – Flip Flop Design” Behavioral design in Xilinx integrated software environment----------------------------------------------------------------------------------- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date: 19:08:41 04/01/12-- Design Name: D FlipFlop Design -- Module Name: DFLIPFLOP3 - Behavioral-- Project Name:VHDL Program for "D FlipFlop Design" in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)
-- Revision 0.01 - File Created-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;------------------------------------------------------------------------------------ Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;--------------------------------------------------------------------------------entity DFLIPFLOP3 is Port ( DATAIN : in std_logic; CLOCK : in std_logic; DATAOUT : out std_logic);end DFLIPFLOP3;architecture Behavioral of DFLIPFLOP3 isbegin process (DATAIN, CLOCK) begin if (CLOCK = '1' and CLOCK'event) then DATAOUT <= DATAIN; end if; end process;end Behavioral;
VHDL program for “D – Flip Flop With Clock and Reset Design” Behavioral design in Xilinx integrated software environment----------------------------------------------------------------------------------- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date: 19:08:41 04/01/12-- Design Name: D FlipFlop with Clock and Reset Design -- Module Name: DFLIPFLOP4 - Behavioral-- Project Name:VHDL Program for "D FlipFlop with Clock and Reset Design" in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)-- Revision 0.01 - File Created-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;--------------------------------------------------------------------------------
---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;--------------------------------------------------------------------------------entity DFLIPFLOP4 is Port ( D : in std_logic; CLOCK : in std_logic; RESET : in std_logic; Q : out std_logic);end DFLIPFLOP4;architecture Behavioral of DFLIPFLOP4 isbegin process (CLOCK) begin if (CLOCK'event and CLOCK='1')then if RESET ='0' then Q <= '0'; else Q <= D; end if; end if; end process;end Behavioral;
VHDL Digital T - Flip Flop Program
VHDL program for “T – Flip Flop Design” Behavioral design in Xilinx integrated software environment----------------------------------------------------------------------------------- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date: 11:35:16 04/02/12-- Design Name: T FlipFlop Design -- Module Name: TFF1 - Behavioral-- Project Name:VHDL Program for "T FlipFlop Design" in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)-- Revision 0.01 - File Created-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;------------------------------------------------------------------------------------ Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;--------------------------------------------------------------------------------entity TFF1 is Port ( T : in std_logic; CLOCK : in std_logic; Q : inout std_logic; QN : inout std_logic);end TFF1;architecture Behavioral of TFF1 isbegin process(CLOCK,T) begin if (CLOCK = '1' and CLOCK'event) then if (T='1')then Q <= NOT Q; QN <= NOT Q after 0.5ns; else Q <= Q;
QN <= NOT Q after 0.5ns; end if; end if; end process;end Behavioral;
VHDL program for “T – Flip Flop Design” Behavioral design in Xilinx integrated software environment----------------------------------------------------------------------------------- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date: 12:00:24 04/02/12-- Design Name: T FlipFlop Design -- Module Name: TFF2 - Behavioral-- Project Name:VHDL Program for "T FlipFlop Design" in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)-- Revision 0.01 - File Created-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;------------------------------------------------------------------------------------ Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;--------------------------------------------------------------------------------entity TFF2 is Port ( T : in std_logic; CLOCK : in std_logic; Q : inout std_logic; QN : out std_logic);end TFF2;architecture Behavioral of TFF2 isbegin process(CLOCK) begin if (CLOCK = '0' and CLOCK'event) then Q <= (T AND (NOT Q)) OR ((NOT T) AND Q) after 10ns; end if; QN <= NOT Q; end process;end Behavioral;
VHDL Digital SR - Flip Flop Program
VHDL program for “SR – Flip Flop Design” Behavioral design in Xilinx integrated software environment----------------------------------------------------------------------------------- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date: 11:35:16 04/02/12-- Design Name: SR FlipFlop Design -- Module Name: SRFF1 - Behavioral-- Project Name:VHDL Program for "SR FlipFlop Design" in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)-- Revision 0.01 - File Created-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;------------------------------------------------------------------------------------ Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;--------------------------------------------------------------------------------entity SRFF1 is Port ( S : in std_logic; R : in std_logic; Q : inout std_logic; QN : inout std_logic);end SRFF1;architecture Behavioral of SRFF1 isbegin process (S,R,Q,QN) begin Q <= R NOR QN; QN <= S NOR Q; end process;end Behavioral;
VHDL program for “Clocked SR – Flip Flop Design” Behavioral design in Xilinx integrated software environment----------------------------------------------------------------------------------- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date: 11:35:16 04/02/12-- Design Name: Clocked SR FlipFlop Design -- Module Name: SRFF1 - Behavioral-- Project Name:VHDL Program for "Clocked SR FlipFlop Design" in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)-- Revision 0.01 - File Created-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;------------------------------------------------------------------------------------ Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;--------------------------------------------------------------------------------entity SRFF1 is Port ( S : in std_logic; R : in std_logic; Q : inout std_logic; QN : inout std_logic);end SRFF1;architecture Behavioral of SRFF1 isbegin process (S,R,Q,QN) begin Q <= R NOR QN; QN <= S NOR Q; end process;end Behavioral;---------------------------------------------------------------------------------- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date: 11:35:16 04/02/12-- Design Name: Clocked SR FlipFlop Design -- Module Name: SRFF2 - Behavioral-- Project Name:VHDL Program for "Clocked SR FlipFlop Design" in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)-- Revision 0.01 - File Created
-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;------------------------------------------------------------------------------------ Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;--------------------------------------------------------------------------------entity SRFF2 is Port ( S : in std_logic; R : in std_logic; CLOCK : in std_logic; M : inout std_logic; N : inout std_logic; Q : inout std_logic; QN : inout std_logic);end SRFF2;architecture Behavioral of SRFF2 iscomponent SRFF1 is Port (S : in std_logic; R : in std_logic; Q : inout std_logic; QN : inout std_logic);end component;begin M <= S AND CLOCK; N <= R AND CLOCK; a1: SRFF1 port map (M, N, Q, QN);end Behavioral;
VHDL Digital JK - Flip Flop Program
VHDL program for “JK – Flip Flop Design” Behavioral design in Xilinx integrated software environment----------------------------------------------------------------------------------- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date: 19:08:41 04/01/12-- Design Name: JK FlipFlop Design -- Module Name: JKFLIPFLOP1 - Behavioral-- Project Name:VHDL Program for "JK FlipFlop Design" in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)-- Revision 0.01 - File Created-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;------------------------------------------------------------------------------------ Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;--------------------------------------------------------------------------------entity JKFLIPFLOP1 is Port ( J : in std_logic; K : in std_logic; CLK : in std_logic; Q : inout std_logic; QN : inout std_logic);end JKFLIPFLOP1;architecture Behavioral of JKFLIPFLOP1 isbegin process(CLK,J,K) begin if (CLK='1' and CLK'event) then if(J='0' and K='0') then Q <=Q;
QN <=QN; elsif(J='0' and K='1') then Q <= '1'; QN <= '0'; elsif(J='1' and K='0') then Q <= '0'; QN <= '1'; elsif(J='1' and K='1') then Q <= NOT Q; QN <= NOT QN; end if; end if; end process;end Behavioral;
VHDL program for “JK – Flip Flop Design” Behavioral design in Xilinx integrated software environment----------------------------------------------------------------------------------- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date: 19:08:41 04/01/12-- Design Name: JK FlipFlop Design -- Module Name: JKFF2 - Behavioral-- Project Name:VHDL Program for "JK FlipFlop Design" in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)-- Revision 0.01 - File Created-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;------------------------------------------------------------------------------------ Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;--------------------------------------------------------------------------------entity JKFF2 is Port ( SN : in std_logic; RN : in std_logic; J : in std_logic; K : in std_logic; CLK : in std_logic; Q : inout std_logic; QN : out std_logic);end JKFF2;architecture Behavioral of JKFF2 is
begin process(SN,RN,CLK) begin if RN='0' then Q <= '0'; elsif SN='0' then Q <= '1'; elsif CLK='0' and CLK'event then q <= (J AND (NOT Q)) OR ((NOT K) AND Q); end if; QN <= NOT Q; end process;end Behavioral;
VHDL program for “JK – Flip Flop with Reset Design” Behavioral design in Xilinx integrated software environment----------------------------------------------------------------------------------- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date: 10:25:40 04/02/12-- Design Name: JK FlipFlop with Reset Design -- Module Name: JKFF3 - Behavioral-- Project Name:VHDL Program for "JK FlipFlop with Reset Design" in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)-- Revision 0.01 - File Created-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;------------------------------------------------------------------------------------ Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;--------------------------------------------------------------------------------entity JKFF3 is Port ( CLOCK : in std_logic; J : in std_logic; K : in std_logic; RESET : in std_logic; Q : out std_logic; QBAR : out std_logic);end JKFF3;architecture Behavioral of JKFF3 issignal state: std_logic;
signal input: std_logic_vector (1 downto 0);begin input <= J & K; p: process(CLOCK,RESET) is begin if RESET = '1' then state <= '0'; elsif (rising_edge(CLOCK)) then case (input) is when"11" => state <= not state; when"10" => state <= '1'; when"01" => state <= '0'; when others => null; end case; end if; end process;end Behavioral;
VHDL Digital EX-OR Gate Program
VHDL program for “XOR Gate” behavioral design in Xilinx integrated software environment---------------------------------------------------------------------------------- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date:20:36:38 03/28/12-- Design Name:XOR Gate Design -- Module Name:XOR1 - Behavioral-- Project Name:VHDL Program for "Universal Logic Gates" in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)-- Revision 0.01 - File Created-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;------------------------------------------------------------------------------------ Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;--------------------------------------------------------------------------------entity XOR1 is Port ( X : in std_logic; Y : in std_logic; F : out std_logic);end XOR1;architecture Behavioral of XOR1 isbeginProcess (X,Y)
begin F <= X XOR Y; end process;end Behavioral;
VHDL program for “XOR Gate” architectural design in Xilinx integrated software environment--------------------------------------------------------------------------------
-- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date:20:36:38 03/28/12-- Design Name:XOR Gate Design -- Module Name:XOR2 - Architectural-- Project Name:VHDL Program for "Universal Logic Gates" in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)-- Revision 0.01 - File Created-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;------------------------------------------------------------------------------------- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;---------------------------------------------------------------------------------entity XOR2 is Port ( X : in std_logic; Y : in std_logic; F : out std_logic);end XOR2;architecture XOR2_arch of XOR2 isbegin process(X,Y) begin if(X/=Y) then F<='1'; else F<='0'; end if; end process;end XOR2_arch;
VHDL Digital EX - NOR Program
VHDL program for “XNOR Gate” behavioral design in Xilinx integrated software environment---------------------------------------------------------------------------------- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date:20:36:38 03/28/12-- Design Name:XNOR Gate Design -- Module Name:XNOR1 - Behavioral-- Project Name:VHDL Program for "Universal Logic Gates" in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)-- Revision 0.01 - File Created-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;------------------------------------------------------------------------------------ Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;--------------------------------------------------------------------------------entity XNOR1 is Port ( X : in std_logic; Y : in std_logic; F : out std_logic);end XNOR1;architecture Behavioral of XNOR1 isbegin
Process (X,Y)begin
F <= X XNOR Y; end process;end Behavioral;
VHDL program for “XNOR Gate” architectural design in Xilinx integrated software environment---------------------------------------------------------------------------------- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date:20:36:38 03/28/12-- Design Name:XNOR Gate Design -- Module Name:XNOR2 - Architectural-- Project Name:VHDL Program for "Universal Logic Gates" in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)-- Revision 0.01 - File Created-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;------------------------------------------------------------------------------------- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;----------------------------------------------------------------------------------entity XNOR2 is Port ( X : in std_logic; Y : in std_logic; F : out std_logic);end XNOR2;architecture XNOR2_arch of XNOR2 isbegin process(X,Y) begin if(X/=Y) then F<='0'; else F<='1'; end if; end process;end XNOR2_arch;
VHDL Digital NOR Gate Program
VHDL program for “NOR Gate” behavioral design in Xilinx integrated software environment---------------------------------------------------------------------------------- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date:20:36:38 03/28/12-- Design Name:NOR Gate Design -- Module Name:NOR1 - Behavioral-- Project Name:VHDL Program for "Universal Logic Gates" in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)-- Revision 0.01 - File Created-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;------------------------------------------------------------------------------------ Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;--------------------------------------------------------------------------------entity NOR1 is Port ( X : in std_logic; Y : in std_logic; F : out std_logic);end NOR1;architecture Behavioral of NOR1 isbegin
Process (X,Y)begin
F <= X NOR Y; end process;end Behavioral;
VHDL program for “NOR Gate” architectural design in Xilinx integrated software environment---------------------------------------------------------------------------------- Company:Techno Global - Balurghat
-- Engineer:Mr. Jitaditya Mondal-- Create Date:20:36:38 03/28/12-- Design Name:NOR Gate Design -- Module Name:NOR2 - Architectural-- Project Name:VHDL Program for "Universal Logic Gates" in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)-- Revision 0.01 - File Created-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;------------------------------------------------------------------------------------- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;----------------------------------------------------------------------------------entity NOR2 is Port ( X : in std_logic; Y : in std_logic; F : out std_logic);end NOR2;architecture NOR2_arch of NOR2 isbegin process(X,Y) begin if((X='0') and (Y='0')) then F<='1'; else F<='0'; end if; end process;end NOR2_arch;
VHDL Digital NAND Gate Program
VHDL program for “NAND Gate” behavioral design in Xilinx integrated software environment---------------------------------------------------------------------------------- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date:20:36:38 03/28/12-- Design Name:NAND Gate Design -- Module Name:NAND1 - Behavioral-- Project Name:VHDL Program for "Universal Logic Gates" in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)-- Revision 0.01 - File Created-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;------------------------------------------------------------------------------------ Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;--------------------------------------------------------------------------------entity NAND1 is Port ( X : in std_logic; Y : in std_logic; F : out std_logic);end NAND1;architecture Behavioral of NAND1 isbegin
Process (X,Y)begin
F <= X NAND Y; end process;end Behavioral;
VHDL program for “NAND Gate” architectural design in Xilinx integrated software environment-
--------------------------------------------------------------------------------- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date:20:36:38 03/28/12-- Design Name:NAND Gate Design -- Module Name:NAND2 - Architectural-- Project Name:VHDL Program for "Universal Logic Gates" in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)-- Revision 0.01 - File Created-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;------------------------------------------------------------------------------------- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;----------------------------------------------------------------------------------entity NAND2 is Port ( X : in std_logic; Y : in std_logic; F : out std_logic);end NAND2;architecture NAND2_arch of NAND2 isbegin process(X,Y) begin if((X='1') and (Y='1')) then F<='0'; else F<='1'; end if; end process;end NAND2_arch;
VHDL Digital NOT Gate Program
VHDL program for “NOT Gate” behavioral design in Xilinx integrated software environment----------------------------------------------------------------------------------- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date: 20:19:26 03/28/12-- Design Name:NOT Gate Design-- Module Name:NOT1 - Behavioral-- Project Name:VHDL Program for "Basic Gates" in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)-- Revision 0.01 - File Created-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;------------------------------------------------------------------------------------ Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;--------------------------------------------------------------------------------entity NOT1 is Port ( X : in std_logic; F : out std_logic);end NOT1;architecture Behavioral of NOT1 isbeginProcess (X)begin F <= NOT X; end process;end Behavioral;
VHDL program for “NOT Gate” architectural design in Xilinx integrated software environment-
--------------------------------------------------------------------------------- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date:20:19:26 03/28/12-- Design Name:NOT Gate Design-- Module Name:NOT2 - Architectural-- Project Name:VHDL Program for "Basic Gates" in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)-- Revision 0.01 - File Created-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;------------------------------------------------------------------------------------- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;---------------------------------------------------------------------------------entity NOT2 is Port ( X : in std_logic; F : out std_logic);end NOT2;architecture NOT2_arch of NOT2 isbegin process(X) begin if(X='1') then F<='0'; else F<='1'; end if; end process;end NOT2_arch;
VHDL Digital OR Gate Program
VHDL program for “OR Gate” behavioral design in Xilinx integrated software environment----------------------------------------------------------------------------------- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date:03:21:43 03/28/12-- Design Name:OR Gate Design -- Module Name:OR1 - Behavioral-- Project Name:VHDL Program for "Basic Gates" in XILINX Integrated Software Environment -- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog) -- Revision 0.01 - File Created-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;------------------------------------------------------------------------------------ Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;--------------------------------------------------------------------------------entity OR1 is Port ( X : in std_logic; Y : in std_logic; F : out std_logic);end OR1;architecture Behavioral of OR1 is begin Process (X,Y) begin F <= X OR Y; end process;end Behavioral;
VHDL program for “OR Gate” architectural design in Xilinx integrated software environment----------------------------------------------------------------------------------- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date:03:21:43 03/28/12-- Design Name:OR Gate Design-- Module Name:OR2 - Architectural-- Project Name:VHDL Program for "Basic Gates" in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)-- Revision 0.01 - File Created-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;------------------------------------------------------------------------------------ Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;--------------------------------------------------------------------------------entity OR2 is Port ( X : in std_logic; Y : in std_logic; F : out std_logic);end OR2;architecture OR2_arch of OR2 isbegin process(X,Y) begin if((X='0') and (Y='0')) then F<='0'; else F<='1'; end if; end process;end OR2_arch;
VHDL Digital AND Gate Program
VHDL program for “AND Gate” behavioral design in Xilinx integrated software environment----------------------------------------------------------------------------------- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date:17:37:18 03/28/12-- Design Name:AND Gate Design-- Module Name:AND1 - Behavioral-- Project Name:VHDL Program for "Basic Gates" in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)-- Revision 0.01 - File Created-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;------------------------------------------------------------------------------------ Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;-------------------------------------------------------------------------------entity AND1 is Port ( X : in std_logic; Y : in std_logic; F : out std_logic);end AND1;architecture Behavioral of AND1 isbegin
Process (X,Y)begin
F <= X AND Y; end process;end Behavioral;
VHDL program for “AND Gate” architectural design in Xilinx integrated software environment----------------------------------------------------------------------------------- Company:Techno Global - Balurghat-- Engineer:Mr. Jitaditya Mondal-- Create Date:03:21:43 03/28/12-- Design Name:AND Gate Design-- Module Name:AND2 - Architectural-- Project Name:VHDL Program for "Basic Gates" in XILINX Integrated Software Environment-- Target Device:XC2S15-- Tool versions:XST(VHDL/Verilog)-- Revision 0.01 - File Created-- Additional Comments:--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;----------------------------------------------------------------------------------- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;-------------------------------------------------------------------------------entity AND2 is Port ( X : in std_logic; Y : in std_logic; F : out std_logic);end AND2;architecture AND2_arch of AND2 isbegin process(X,Y) begin if((X='1') and (Y='1')) then F<='1'; else F<='0'; end if; end process;end AND2_arch;