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EE 107 reference materials for adder/subtractor/ALU ... · Dataflow VI-IDL code for a I-bit full...

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EE 107 reference materials for adder/subtractor/ALU circuits design Instructor: Dr. Qun (Vincent) Zhang [email protected] ECET Dept., 02/13/2019
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Page 1: EE 107 reference materials for adder/subtractor/ALU ... · Dataflow VI-IDL code for a I-bit full adder. Figure 4.2 . cout Yl FAI xo YO FAO so FA3 FA2 Ripple-carry ... VHDL code for

EE 107reference materials for adder/subtractor/ALU circuits design

Instructor: Dr. Qun (Vincent) Zhang

[email protected]

ECET Dept., 02/13/2019

Page 2: EE 107 reference materials for adder/subtractor/ALU ... · Dataflow VI-IDL code for a I-bit full adder. Figure 4.2 . cout Yl FAI xo YO FAO so FA3 FA2 Ripple-carry ... VHDL code for

Dr. Zhang 2

Part 1. Adders & Subtractors

Addition of two 4-bit binary numbers:

Page 3: EE 107 reference materials for adder/subtractor/ALU ... · Dataflow VI-IDL code for a I-bit full adder. Figure 4.2 . cout Yl FAI xo YO FAO so FA3 FA2 Ripple-carry ... VHDL code for

Dr. Zhang 3

The circuit for

the addition of

a signal slice is

known as a full

adder (FA):

Page 4: EE 107 reference materials for adder/subtractor/ALU ... · Dataflow VI-IDL code for a I-bit full adder. Figure 4.2 . cout Yl FAI xo YO FAO so FA3 FA2 Ripple-carry ... VHDL code for

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Page 5: EE 107 reference materials for adder/subtractor/ALU ... · Dataflow VI-IDL code for a I-bit full adder. Figure 4.2 . cout Yl FAI xo YO FAO so FA3 FA2 Ripple-carry ... VHDL code for

Dr. Zhang 5

We connect four FAs together in series, resulting in a

ripple-carry adder for adding two 4-bit operands.

Page 6: EE 107 reference materials for adder/subtractor/ALU ... · Dataflow VI-IDL code for a I-bit full adder. Figure 4.2 . cout Yl FAI xo YO FAO so FA3 FA2 Ripple-carry ... VHDL code for

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Page 7: EE 107 reference materials for adder/subtractor/ALU ... · Dataflow VI-IDL code for a I-bit full adder. Figure 4.2 . cout Yl FAI xo YO FAO so FA3 FA2 Ripple-carry ... VHDL code for

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Carry-Lookahead Adder • Ripple-carry adder is slow (why?)

• Solution: Carry-lookahead adder

• Let’s see how Carry-lookahead adder removes the dependency on the previous carry-out signal

Page 8: EE 107 reference materials for adder/subtractor/ALU ... · Dataflow VI-IDL code for a I-bit full adder. Figure 4.2 . cout Yl FAI xo YO FAO so FA3 FA2 Ripple-carry ... VHDL code for

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Page 9: EE 107 reference materials for adder/subtractor/ALU ... · Dataflow VI-IDL code for a I-bit full adder. Figure 4.2 . cout Yl FAI xo YO FAO so FA3 FA2 Ripple-carry ... VHDL code for

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Subtractor

Page 10: EE 107 reference materials for adder/subtractor/ALU ... · Dataflow VI-IDL code for a I-bit full adder. Figure 4.2 . cout Yl FAI xo YO FAO so FA3 FA2 Ripple-carry ... VHDL code for

Dr. Zhang 10

There is a

better way!

Page 11: EE 107 reference materials for adder/subtractor/ALU ... · Dataflow VI-IDL code for a I-bit full adder. Figure 4.2 . cout Yl FAI xo YO FAO so FA3 FA2 Ripple-carry ... VHDL code for

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Recall: 2’s complement Binary Numbers

Page 12: EE 107 reference materials for adder/subtractor/ALU ... · Dataflow VI-IDL code for a I-bit full adder. Figure 4.2 . cout Yl FAI xo YO FAO so FA3 FA2 Ripple-carry ... VHDL code for

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Page 13: EE 107 reference materials for adder/subtractor/ALU ... · Dataflow VI-IDL code for a I-bit full adder. Figure 4.2 . cout Yl FAI xo YO FAO so FA3 FA2 Ripple-carry ... VHDL code for

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Page 14: EE 107 reference materials for adder/subtractor/ALU ... · Dataflow VI-IDL code for a I-bit full adder. Figure 4.2 . cout Yl FAI xo YO FAO so FA3 FA2 Ripple-carry ... VHDL code for

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Page 15: EE 107 reference materials for adder/subtractor/ALU ... · Dataflow VI-IDL code for a I-bit full adder. Figure 4.2 . cout Yl FAI xo YO FAO so FA3 FA2 Ripple-carry ... VHDL code for

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Page 16: EE 107 reference materials for adder/subtractor/ALU ... · Dataflow VI-IDL code for a I-bit full adder. Figure 4.2 . cout Yl FAI xo YO FAO so FA3 FA2 Ripple-carry ... VHDL code for

Part 2. Arithmetic Logic Unit (ALU)

• ALU is one of the main components inside a microprocessor

• Responsible for performing arithmetic + logic operations

• Use ideas in constructing the adder-subtractor combination circuit

• Implement arithmetic + logic functions by inserting some combinational circuitry in front of the input operands.

Page 17: EE 107 reference materials for adder/subtractor/ALU ... · Dataflow VI-IDL code for a I-bit full adder. Figure 4.2 . cout Yl FAI xo YO FAO so FA3 FA2 Ripple-carry ... VHDL code for

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Page 18: EE 107 reference materials for adder/subtractor/ALU ... · Dataflow VI-IDL code for a I-bit full adder. Figure 4.2 . cout Yl FAI xo YO FAO so FA3 FA2 Ripple-carry ... VHDL code for

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Page 19: EE 107 reference materials for adder/subtractor/ALU ... · Dataflow VI-IDL code for a I-bit full adder. Figure 4.2 . cout Yl FAI xo YO FAO so FA3 FA2 Ripple-carry ... VHDL code for

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Page 20: EE 107 reference materials for adder/subtractor/ALU ... · Dataflow VI-IDL code for a I-bit full adder. Figure 4.2 . cout Yl FAI xo YO FAO so FA3 FA2 Ripple-carry ... VHDL code for

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Page 21: EE 107 reference materials for adder/subtractor/ALU ... · Dataflow VI-IDL code for a I-bit full adder. Figure 4.2 . cout Yl FAI xo YO FAO so FA3 FA2 Ripple-carry ... VHDL code for

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