PRIYADARSHINI COLLEGE OF ENGINEERING

• Seminar On:-Xilinx xc 3000

• yogesh s. watileSub:MDS-1

M-tech I Sem.(VLSI)

XC3000-Series Field Programmable Gate Arrays (FPGAs)provide a group of high-performance, high-density, digitalintegrated circuits.

Their regular, extendable, flexible,user-programmable array architecture is composed of aconfiguration program store plus three types of configurable elements: I/O Blocks (IOBs), Configurable Logic Bocks (CLBs) and resourcesfor interconnection.

The XC3000 Field Programmable Gate Array families provide a variety of logic capacities, package styles, temperature ranges and speed grades.

Xilinx FPGAs - Generic Features High Performance at different voltages

Footprint Compatibility- Devices within each family are

compatible.

Low power consumption/high performance

Integrated Software

XC2000 First FPGA Family from Xilinx. Two members:

XC2064 1000 GatesXC2018 1500 Gates

Ext. Crystal Oscillator. No Tri State Buffers. XACT 1.0 Development System.

Advantages of XC3000 over xc2000 Replaces TTL, MSI and other PLD logics.

Integrates complete subsystem into single Package.

System clock Speed up to 50 MHz.

On-chip crystal Oscillator. Over 20 different Packaging Options.

XC3000 Series of FPGA devices:

• XC3000A Family • XC3000L Family • XC3100A Family • XC3100L Family

Fig. Layout of part of a programmable logic cell array

Fig. Configuration Memory cell

The static memory cell used for the configuration memoryin the Field Programmable Gate Array has been designedspecifically for high reliability and noise immunitythe basic memory cell consists of two CMOSinverters plus a pass transistor used for writing and readingcell data.

Xilinx XC3000 CLB A 32-bit look-up table ( LUT ) CLB propagation delay is fixed (the LUT

access time) and independent of the logic function

7 inputs to the XC3000 CLB: 5 CLB inputs (A–E), and 2 flip-flop outputs (QX and QY)

2 outputs from the LUT (F and G). Since a 32-bit LUT requires only five variables

to form a unique address (32 = 25), there are multiple ways to use the LUT

Xilinx XC3000 CLB Use 5 of the 7 possible inputs (A–E, QX, QY) with the

entire 32-bit LUT the CLB outputs (F and G) are then identical

Split the 32-bit LUT in half to implement 2 functions of 4 variables each choose 4 input variables from the 7 inputs (A–E, QX, QY). you have to choose 2 of the inputs from the 5 CLB inputs (A–E);

then one function output connects to F and the other output connects to G

You can split the 32-bit LUT in half, using one of the 7 input variables as a select input to a 2:1 MUX that switches between F and G to implement some functions of 6 and 7 variables

Xilinx XC3000 CLB The block diagram

for an XC3000 family CLB illustrates all of these features

To simplify the diagram, programmable MUX select lines are not shown

Combinational function is a LUT

LUT

XC3000 CLB

Fig. Combinatorial Logic options

(A) Combinatorial Logic Option FG generates two functions of four variables each. One variable, A, must becommon to both functions. The second and third variablecan be any choice of B, C, QX and QY. The fourth variable can be any choice of D or E.

(B). Combinatorial Logic Option F generates any functionof five variables: A, D, E and two choices out of B, C, QX,QY.

(C). Combinatorial Logic Option FGM allows variable E toselect between two functions of four variables: Both havecommon inputs A and D and any choice out of B, C, QXand QY for the remaining two variables. Option 3 canthen implement some functions of six or seven variables.

Fig. Xilinx 3000 series I/O block

Programmable interconnects:

General purpose interconnects

Direct interconnect between adjacent CLB’s

Long line

Fig: General purpose interconnects

Direct interconnects between adjacent CLB’s

Vertical and horizontal long lines:

Crystal oscillator:

thank you