01/04/09 A. Salamon – TDAQ WG - CERN 1

LKr calorimeter L0 trigger

V. Bonaiuto, L. Cesaroni, A. Fucci,A. Salamon, G. Salina, F. Sargeni

01/04/09 A. Salamon – TDAQ WG - CERN 2

L0 LKr trigger

• L0 LKr trigger (photon veto): cluster counting with 1-2 ns time resolution• Use existing hardware (NA48 and LHC)• Use the NA48 analog sums (2x8 cells) and cables replacing the “old”

system with a new TELL1 based system

01/04/09 A. Salamon – TDAQ WG - CERN 3

L0 LKr trigger

• Use analog sums (2x8 cells) and all the cables already exist• Need to design the trigger processor

read-out boards

13k analogchannels

analogsums

LKr calorimeter

DAQ

864 analogchannels

L0 LKrtrigger

read-outafter L0

CTP

01/04/09 A. Salamon – TDAQ WG - CERN 4

The TELL1 board

• LHCb general purpose data acquisition board• 5 user programmable FPGAs, large on-board DDR memories• mezzanines for 4 x 1 gbit ethernet output

analog mezzanine16 x 10 bit

Stratix FPGA25k logic elem

Stratix FPGA40k logic elem

digital mezzanine12 x 16 bit

parallel bus32 bit @ 160 MHz

output interface4 x gbit ethernet

01/04/09 A. Salamon – TDAQ WG - CERN 5

FE boards: pulse reconstr (time, position, energy)

TELL

1

28 boards

CTP

L0 LKr Trigger: architecture

• Need to design two mezzanines:– one FE + ADC mezzanine– one ethernet concentrator mezzanine

•Two 9U crates!

13248 channels for the readout 864 channels (2x8 pixel supercells) for the trigger!

AD

C

mezz

32 supercells

Concentrator boards: merging, sorting

TELL

1

24 ch

5 boards

Eth

ern

et

mezzethernet

1 meter

32 ch

01/04/09 A. Salamon – TDAQ WG - CERN 6

L0 Lkr trigger: architecture

Concentrator TELL1: merging, sorting24 Front-End TELL1

Front-End TELL1: pulse reconstruction (time, position and energy)32 analog channels (1 channel = 2x8 liquid krypton cells analog sum)

1 analog sum (supercell) =

2x8 channels

28 FE TELL1s, 5 concentrator TELL1s, 32 supercells per TELL1

01/04/09 A. Salamon – TDAQ WG - CERN 7

Front-End ADC mezzanine

• At the moment we are preparing a test stand using an existing LHCb mezzanine

• New mezzanine later

TELL

1

28 boards

CTPA

DC

m

ezz

32 supercells

TELL

1

24 ch

5 boards

Eth

ern

et

mezz

ethernet

32 ch

01/04/09 A. Salamon – TDAQ WG - CERN 8

FE to concentrator link I (new receiver)

• Use existing gbit ethernet output mezzanine and design new ethernet receiver on the concentrator

• Up to 24 ethernet input on the concentrator = 8 FE TELL1 (3 gbit per TELL1)

• 24 ethernet connector is (mechanically) difficult but possible

• Pros: lower design effort, bidirectional, added FPGA processing power on the receiver, flexible (same link for trigger and readout)

• Cons: ethernet overhead, lower bandwidth

TELL

1

Concentr

Eth

ern

et

mezz

ethernet

Front-End

Eth

TXTE

LL1

NEW!!

01/04/09 A. Salamon – TDAQ WG - CERN 9

FE to concentrator link II (new TX)

• Use existing optical receiver input mezzanine on the concentrator and design new ethernet + fiber optic transmitter

• Cons: higher design effort, monodirectional, no added FPGA processing power on the receiver

• Pros: no ethernet and added latency on the trigger path, higher bandwidth

TELL

1

Concentr

Opti

cal m

ezz

ethernet

Front-End

Eth

+

op

t TXTE

LL1

NEW!!

01/04/09 A. Salamon – TDAQ WG - CERN 10

Pulse reconstruction (FE TELL1)

Peak in spacePeak in time

Over threshold

7 bit reconstructed fine time

Parabolic fitPeak processor(one channel)

Peak finder (one channel)

01/04/09 A. Salamon – TDAQ WG - CERN 11

80 MHz sampling: 50 ps/binfull scale pulse -> 100 ps rms

40 MHz sampling: 100 ps/bin1/40 full scale pulse + noise and jitter -> 700 ps rms

simul

ation

simul

ation

simul

ation

simul

ation

Some plots (digital simulation!!!)

01/04/09 A. Salamon – TDAQ WG - CERN 12

Front-End PP FPGA

multipliers, dividers: lot of Logic Elements

Fmax ~ 80 MHz80% device usageon an EP1S25

01/04/09 A. Salamon – TDAQ WG - CERN 13

Front-End PP FPGA (new!!)

multipliers, dividers: lot of Logic Elements

RATE:5 samples @ 80 MHz = 16 MHz / PP FPGA

01/04/09 A. Salamon – TDAQ WG - CERN 14

Hit rates (Front-End TELL1s)

• Instantaneous design hit rate (Marco’s TDAQ note): 30 MHz

• Rate in the central region (Giuseppe’s private communication): 3 times mean hit rate

• Clusters of 256 liquid krypton cells (conservative)

• All hits generate a shower (conservative)

( 30 MHz / 28 ) x 3 = 3.2

( 30 MHz / 28 ) x 3 = 3.2

( 30 MHz / 28 ) x 3 / 8 = 0.4

TOTAL RATE = 10.8 MHzvs

64 bit/cluster over 3 gbit eth links

01/04/09 A. Salamon – TDAQ WG - CERN 15

Hit rates (PP FPGA = ¼ TELL1)

• Same assumptions• Fast communication between PP

FPGAs in the same TELL1 -> rate reduction

( 30 MHz / 28 ) x 3 / 8 = 0.4

TOTAL RATE = 4.8 MHzvs

64 bit/cluster over 32b @ 160 MHz

( 30 MHz / 28 ) x 3 /4 = 0.8

( 30 MHz / 28 ) x 3 / 4 = 0.8

01/04/09 A. Salamon – TDAQ WG - CERN 16

Concentrator TELL1 (overlkap handling and hit rates)

Maximum in the red area: the cluster is handled by the “red” TELL1 concentrator

Maximum in the blue area: the cluster is handled by the “blue” TELL1 concentrator

Double counting resolved at the level of the concentrator

Only 4 over 8 Front-End TELL1s contribute to the output hit rate:

OUTPUT RATE = (30 MHz / 28) x 3 x 4 = 12.9 MHz

vs64 bit/cluster over 3 gbit eth links

01/04/09 A. Salamon – TDAQ WG - CERN 17

Lab tests: front-end

• We are preparing our test station for the Front-End mezzanine

• AWG 2021 -> mezzanino analog sums -> cable -> TELL1 analog mezzanine -> TELL1

• Same signal in two different analog sums channels

• time resolution rms = sigma(T1-T2)/sqrt(2)

Arbitrary waveform generator: AWG2021

NA48 analog sum card

TELL1

TELL1 analog mezzanine

01/04/09 A. Salamon – TDAQ WG - CERN 18

Lab tests: concentrator link

• We are also working at the test station for our receiver

• Use an altera development kit (Stratix II 60k Logic Elements) to validate and study the receiver

ethernet

01/04/09 A. Salamon – TDAQ WG - CERN 19

Time schedule

• End of april – beginning of may: FE and ethernet link tests in the lab• Then start mezzanines desing• Then try to test the system on the liquid krypton (with LHCb ADC

mezzanine first)