24/03/2010 TDAQ WG - CERN 1

LKr L0 trigger status report

V. Bonaiuto, G. Carboni, L. Cesaroni, A. Fucci, G. Paoluzzi, A. Salamon, G. Salina, E. Santovetti, F. Sargeni

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L0 LKr trigger

• Use analog sums (2x8 cells) and all the cables already existing• New pixel based trigger processor• Low granularity readout independent from the full granularity

readout• Fast readout for software triggers

read-out boards

13k analogchannels

analogsums

LKr calorimeter

DAQ

864 analogchannels

L0 LKrtrigger

read-outafter L0

L0TS

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L0 Lkr trigger: architecture

Concentrator TELL1: merging, sorting8 Front-End TELL1

Front-End TELL1: pulse reconstruction (time, position and energy)32 analog channels (1 channel = 2x8 liquid krypton cells analog sum)

1 analog sum (supercell) =

2x8 channels

28 FE TELL1s, 7 concentrator TELL1s, 32 supercells per TELL1

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FE boards: pulse reconstr (time, position, energy)

L0 LKr Trigger: architecture

• Three new mezzanines:– FE + ADC mezzanine - 2010– TX mezzanine (custom link for the trigger + ethernet for the readout) –

being designed– RX mezzanine (custom link for the trigger) – tested

•Two 9U crates!•Depending on L0TS implementation a final TELL1 maybe will be needed

13248 channels for the readout 864 channels (2x8 pixel supercells) for the trigger! Concentrator boards:

merging, sorting

TELL

1

28 boards

L0TS

FE+

AD

C M

.

32 supercels

TELL

1

8 ch

7 boards

8 R

X t

rig lin

k

1-3 m copper

32 ch

2 E

th +

2 t

rig

TX

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TELL1 NA62 RX mezzanine

Four links per mezzanine, eight links per TELL1, 1-3 meters copper

6.4 Gbps

0.6 Gbps

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TELL1 NA62 RX mezzanine

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Test setup

2m copper cable

RX mezzanine

Development kit

•“Final” cable cut and rearranged to connect to the development kit

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Test setup

• Developed software and firmware to receive digital data on the TELL1• Control (enable, disable, ecc) the link and read data from the CCPC

• Pattern Generator -> National Semiconductors development board -> (2 meters) cable

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Test setup

• (2 meters) cable -> RX mezzanine -> PP0 FPGA on the TELL1 -> Logic Analyzer connector on the TELL1 -> Logic Analyzer

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Test result (PG/LA snapshot)

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Test result (PG/LA snapshot)

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Comment on cables

• 3M cable suggested by National Semiconductors• At the moment for the test we bought the version of the cable assembly

available on the market even if the connector is too big (few millimeters)• Got from 3M the quotation for a special version with a smaller connector

(this new connector will not have the big screw of the existing ones, however is a standard 3M connector used in other cable assemblies)

• Got from 3M 1 sample of the “final cable” (3 meters)• Minimum Order Quantity = 100 pcs of the same length

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ADC mezzanine test setup (on hold)

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ADC mezzanine test setup (on hold)

• The technician working in our group (G. Paoluzzi) assembled the hardware for ADC tests

• Next step: simulated or measured data from the Arbitrary Waveform Generator -> received and digitized with the TELL1

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TELL1 components procurement

Components for NA62 global TELL1 production (E. Santovetti) • 100 CCPC + 80 RAM modules - 1 CCPC + 1 RAM: 300 CHF• 320 TELL1 input connectors (4 per TELL1, 80 TELL1s) – 1 QSS-100-

01FDA: 6.80 Euro• 70 Intel 4-port Ethernet MAC (obsolete) + Marvell Ethernet transceiver

(150 Euro) • Material database on-line

TELL1 test stationA second TELL1 test station has been implemented to host the TELL1

boards for the production phase

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Requitements/caveat (TELL1++)

• TELL1++: power consumption (and noise) should not increase – we will have 18 TELL1s per crate (like LHCb)

• L0TS: L0 LKr output -> assuming a (very) conservative estimate for the output of 30 MHz hit x 64 bit word = 2 Gbps the L0TS must have an adequate input bandwidth for the L0 LKr (using a link at full bandwidth implies an increase in the average latency: OK for the readout but not for the trigger)

• We are designing the TX (2 GBE + 2 trigger link) board• After the TX board we will start the design of the interface with the Lkr

readout system

Requitements/caveat (TELL1++)

Requitements/caveat (Lkr interface)