1

A 90nm 512Mb 166MHz Multilevel Cell Flash Memory with 1.5MByte/s Programming

Adopted from ISSCC Dig. Tech. Papers, Feb.2005, Intel Corporation[2.6]

Presented By: Nadereh HatamiClass Presentation

Advanced VLSI Design Course

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Outline

Floating Gates introduction Multilevel Flash Cell Approach Device Information Multilevel Cell Sense Budget Stepped Gate (SG) Sensing Negative Deselected Row (NDR) Customer Selectable Output Drive Technology Conclusions

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A Typical Flash Memory Cell

Adopted From [2]

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2-Bit Intel MLC Digital Code Assignment

Charge LevelDigital Code

Level 300

Level 201

Level 110

Level 011

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Device Information

512Mb (8 partitions, 64Mb each) 256 independently erasable blocks

Object/Control Mode Programming 65ns Asynchronous mode access Synchronous Burst

166MHz zero wait state 8W / 16W / Continuous Burst Modes Selectable Output Strength

Low Power Operation Deep Power-Down Mode (5uA) 1.7 – 2.0V core power supply (VCC) 1.35V – 2.0V output driver power supply (VCCQ)

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Multilevel Cell Sense Budget

R1

Read Reference Level 3 (R3)

Erase Verify (EV)

PV1

R2

PV2

Program Verify Level 3 (PV3)

Max VT limited by Cell and Program Placement Performance

Min VT limited by Column Leakage Impact on Erase

Incr

easi

ng

VT (

~3V

bet

wee

n R

1 an

d R

3)

Some sense budget componentsFloating Gate (FG) to FG CouplingApparent VT Change due to ΔVS

VT Margin Required for SensingProgram State Width Post Retention BakeErase State Width Post Retention Bake

L0

L1

L2

L3

Count

From [1]

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Floating Gate (FG) to FG Coupling

Drain Shields Poly 1 FG-FG CouplingFG Coupling

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Apparent VT Change due to ΔVS

Cell A = L1 Cell B = L0

Cell A = L1 Cell B = L3

From [1]

128 Cells Read in Parallel 1st Program Operation Places Cell A = L1 2nd Program Operation Places Cell B = L3 Source Voltage Lowers for Cell A during L1 sense Result: Lower Apparent VT

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Minimizing FG-FG Coupling & ΔVS

Programming cells in an 8Kbit region in a single program operation:

Eliminates impact of Apparent ΔVT due to ΔVS Minimizes impact of FG-FG Coupling

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Stepped Gate (SG) vs. Constant Gate (CG) Sensing

R3

R2

R1

CG Sensing Voltage

Gate voltage varies for SG sensing

1 2VGS

IDS

3

Ref cell current varies depending on VT for CG sensing

SG Sensing uses a fixed reference current CG Sensing uses a fixed gate voltage

Ref cell current is constant for SG sensing

From [1]

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Stepped Gate Sensing Scheme Concept

From [1]

12

Stepped Gate Sensing

From [1]

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Negative Deselected Row (NDR)

IREF

- VT

Cell w/ -VT Swamps Comparator

Comp

Erase VT Distribution

Over-eased Cells

Under-erased Cells

VEV

0V

0Vw/o NDR

w/ NDR

From [1]

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Multilevel Cell Sense Margin ImprovementIn

crea

sin

g V

T (

~3V

bet

wee

n R

1 an

d R

3)

Some sense margin componentsSense Margin ImprovementFloating Gate (FG) to FG CouplingVT Margin Required for SensingProgram State Width Post Retention BakeErase State Width Post Retention Bake

Result of Sense Margin Improvements Can allow wider VT distribution to achieve faster program performance. Can widen budget by lowering EV because Min VT is not limited by Column Leakage Impact on Erase.

R1

R3

EV

PV1

R2

PV2

PV3

L0

L1

L2

L3

Count From [1]

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Customer Selectable Output Drive

P

N

XP

XN

DQPAD

DQ0

DQ3

VCCQ1

VSSQ1

DQ4

DQ7

VCCQ2

VSSQ2

DQ8

DQ11

VCCQ3

VSSQ3

DQ12

DQ15

VCCQ4

VSSQ4

XP:P

XN:N

XP:P

XN:N

XP:P

XN:N

XP:P

XN:N

XP:P

XN:N

XP:P

XN:N

XP:P

XN:N

XP:P

XN:N

StrengthControl

StrengthControl

StrengthControl

StrengthControl

StrengthControl

StrengthControl

StrengthControl

StrengthControl

StrengthControlLogic

CustomerOutputDriver

Registers

XP’:P’

XN’:N’

OutputLatch

Data

OutputLatch

Data

OutputLatch

Data

OutputLatch

Data

OutputLatch

Data

OutputLatch

Data

OutputLatch

Data

OutputLatch

DataCLK

Data0

CLKData3

CLKData4

CLKData7

CLKData8

CLK

Data11

CLKData12

CLKData15

16:1MUX/Latch

256-BitSensing

256 16

4

ClockGenerator

MuxControlLogic

N-1 clk

N clkCLK Pad

Buffer

No. of legs reflectsDrive strength multiples

XN:N

XP:P

VCCQ

VSSQ

WP/LP

WXP/LXP

WXN/LXNWN/LN

P

N

XP

XN

DQPAD

DQ0

DQ3

VCCQ1

VSSQ1

DQ4

DQ7

VCCQ2

VSSQ2

DQ8

DQ11

VCCQ3

VSSQ3

DQ12

DQ15

VCCQ4

VSSQ4

XP:P

XN:N

XP:P

XN:N

XP:P

XN:N

XP:P

XN:N

XP:P

XN:N

XP:P

XN:N

XP:P

XN:N

XP:P

XN:N

StrengthControl

StrengthControl

StrengthControl

StrengthControl

StrengthControl

StrengthControl

StrengthControl

StrengthControl

StrengthControlLogic

CustomerOutputDriver

Registers

XP’:P’

XN’:N’

OutputLatch

Data

OutputLatch

Data

OutputLatch

Data

OutputLatch

Data

OutputLatch

Data

OutputLatch

Data

OutputLatch

Data

OutputLatch

DataCLK

Data0

CLKData3

CLKData4

CLKData7

CLKData8

CLK

Data11

CLKData12

CLKData15

16:1MUX/Latch

256-BitSensing

256 16

4

ClockGenerator

MuxControlLogic

N-1 clk

N clkCLK Pad

Buffer

No. of legs reflectsDrive strength multiples

XN:N

XP:P

VCCQ

VSSQ

WP/LP

WXP/LXP

WXN/LXNWN/LN

From [1]

Customer Selectable Output Drive Strength for matching system load

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Die Photo

Prog Control Circuits

One Block

½ Partition

½ Partition

X-Decoder

Y-Select

Sensing / Bitline Sel

Die Size = 42.5mm2

From [1]

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Technology

Triple Well 90nm CMOS 3 Cu Interconnect Layers Dual Poly Layers, Co-Salicide Flash Cell

Effective Bit Size 0.038μm2 Tunnel Oxide Thickness 88Å Interpoly Dielectric Thickness 140Å

Periphery Transistor Oxide Thickness 150Å High Voltage 45Å Low Voltage

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Conclusions Significant Sense Budget Consumers

FG-FG Coupling Apparent VT change due to change in data pattern

storage Apparent VT change due to temperature change between

cell placement verify and read. Design Techniques that Improve Budget

2-row programming SG sensing NDR

Combining 90nm CMOS technology with multilevel cell Flash and the design techniques that have been presented delivers world-class performance of: 166MHz Synchronous Burst Read 1.5 MByte/s Program

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References

[1] Intel, Folsom, CA, “A 90nm 512Mb 166Mhz Multilevel Cell Flash Memory With 1.5MB/s Programming”, ISSCC Dig. Tech. Papers, Feb. 2005

[2] Bauer, M. et al., “A Multilevel-cell 32Mb Flash Memory,” ISSCC Dig. Tech. Papers, pp.132-133, Feb., 1995.

[3] Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic,” Digital Integrated Circuits, A Design Perspective,2th edition”, Book Slides.

[4] ISSCC Press Kit 2005[5] http://www.siliconfareast.com/flash-memory.htm [6] http://www.intel.com