Design and CAD Challenges in sub-90nm CMOS Technologies Kerry Bernstein, Ching-Te Chuang, Rajiv Joshi, Ruchir Puri IBM Thomas J Watson Research Center, Yorktown Hts, NY kbernste,ctchuang,rvjoshi,ruchir @us.ibm.com This paper discusses design challenges of scaled CMOS circuits in sub-90nm technologies for high-performance digital applications. To continue scaling of the CMOS devices deep into sub-90nm tech- nologies, fully depleted SOI, strained-Si on SiGe, FinFETs with double gate, and even further, three-dimensional circuits will be uti- lized to design high-performance circuits. We will discuss unique design aspects and issues resulting from this scaling such as gate- to-body tunneling, self-heating, reliability issues, and process vari- ations. As the scaling approaches various physical limits, new SOI design issues such as Vt modulation due to leakage, low-voltage impact ionization, and higher to maintain adequate , continue to surface. With an eye towards the future, design and CAD issues related to sub-65nm device structures such as double gate FinFET will be discussed. Scaling the conventional MOSFET beyond the 90nm technology node requires innovations to circumvent barriers due to the fun- damental physics that constrains the conventional MOSFET. The limits most often cited are: quantum-mechanical tunneling of car- riers through thin gate oxide, from drain to source, and from drain to body; control of the density and location of dopants to provide high ratio; and finite subthreshold slope. These funda- mental limits have lead to the pessimistic predictions of the im- minent end of technological progress in semiconductor industry. However, the push to scale conventional MOSFET has continued to show remarkable progress. Continued scaling and demand for performance are pushing for lower supply voltage and , shorter channel length, thinner gate oxide, higher body doping concentra- tion, and thinner Si film thickness. In addition, new materials such as strained-Si channel on relaxed SiGe layer are on the semicon- ductor roadmap to enhance the mobility and current drive. New device structures such as double-gate FinFETs and 3D circuits are being aggressively pursued for 65nm technology and beyond. Such aggressive scaling and new device structures give rise to several unique design issues which must be dealt with before any of these technologies will gain mainstream acceptance. SOI technology has been widely accepted for use in mainstream high-performance logic applications in sub-90nm technologies. The design issues resulting from the floating-body in partially depleted SOI device structure, such as parasitic bipolar effect and hysteretic variation, are now well-understood and circuit/design techniques to mitigate these effects have been developed. However, as the scaling approaches various physical limits, unique/new SOI design issues continue to evolve/surface. In this paper, we discuss the design challenges of sub-90nm CMOS circuits with particular emphasis on the implications and impact of each individual device scaling element on circuit design. In CMOS technologies below 90nm, the Field Effect Transistor will remain the fundamental design element of choice for the high speed logic designer. Changes to this device will be evolutionary rather than revolutionary. Improvements will be aimed at increas- ing mobility and decreasing extrinsic capacitance and resistance. Because a number of factors influence these parameters, multiple mechanisms and structures are proposed for extending CMOS be- low 90nm. A subset of them are described below. The Partially-depleted floating-body MOSFET was the first SOI transistor adopted for general high speed use, due in part to its pro- cessing similarities to common Bulk CMOS. The PD-SOI device is largely identical to the bulk device, except for the addition of a buried oxide (“BOX”) layer, isolating the body of the given device from the bodies of other devices. Isolated below by BOX, to the left and right by diffusion junction diodes, and above by gate insulator, the body’s potential “floats”; this voltage bias is influenced by both static and dynamic effects. SOI offers three main contributions to improved performance: (1) reduced junction capacitance, (2) lower average threshold, and (3) reduced body effect/source follower ac- tion. This performance is at the cost of some design complexity asserted by the floating body of the device, namely parasitic bipo- lar action and variable drive strength. The reader can reference [1, 2, 3] for a more thorough treatment of these effects. In addition, a number of CAD solutions have been developed to mitigate these problems [4, 6]. In order to maintain balance of electric fields and capacitance within the SOI device, the active silicon thickness must be reduced with scaling. In the PD-SOI MOSFET, a “quasi-neutral region” existed deep within the body which remained un-inverted even as the given device went into saturation. A number of device structure alter- ations have been asserted to preserve and extend this partial deple- tion. As active silicon scales thinner, however, the depletion region within the body must expand laterally to satisfy the call for minority carriers at the gate oxide interface, to the point where the depletion region completely encompasses or consumes the body. In this fully depleted FET, the threshold of the device is now defined by the amount of charge obtainable within the isolated body. Other novel devices are by their nature intrinsically fully depleted, as we will see shortly. Figure 1: Schematic cross-section of a strained-Si nMOSFET. Inducing tension on silicon substrates has been known to im- prove carrier mobility [7]. Specifically, tensile strain lifts the six- fold degeneracy in Silicon’s conduction band. Of these six conduc- tion sub-bands, the D2 and D4 band splits are exaggerated when under tension, which suppresses carrier scattering and enhances mobility and drive current. Tensility has been achieved through various means; mechanical strain and epitaxial strain are two pop- ular approaches. In one approach of mechanical strain, processing of the passivation nitride covering the device is altered to cause strain. In the epitaxial approach, a thin pseudomorphic silicon is 129 Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. ICCAD’03, November 11-13, 2003, San Jose, California, USA. Copyright 2003 ACM 1-58113-762-1/03/0011 ...$5.00.
Transcript
Design and CAD Challenges in sub-90nm CMOS Technologies
Kerry Bernstein, Ching-Te Chuang, Rajiv Joshi, Ruchir PuriIBM Thomas J Watson Research Center, Yorktown Hts, NY�
kbernste,ctchuang,rvjoshi,ruchir� @us.ibm.com����������� �This paper discusses design challenges of scaled CMOS circuits insub-90nm technologies for high-performance digital applications.To continue scaling of the CMOS devices deep into sub-90nm tech-nologies, fully depleted SOI, strained-Si on SiGe, FinFETs withdouble gate, and even further, three-dimensional circuits will be uti-lized to design high-performance circuits. We will discuss uniquedesign aspects and issues resulting from this scaling such as gate-to-body tunneling, self-heating, reliability issues, and process vari-ations. As the scaling approaches various physical limits, new SOIdesign issues such as Vt modulation due to leakage, low-voltageimpact ionization, and higher����� � ��� to maintain adequate� ��� ����� ,continue to surface. With an eye towards the future, design andCAD issues related to sub-65nm device structures such as doublegate FinFET will be discussed.� ��� ����! #"$��� � � �Scaling the conventional MOSFET beyond the 90nm technologynode requires innovations to circumvent barriers due to the fun-damental physics that constrains the conventional MOSFET. Thelimits most often cited are: quantum-mechanical tunneling of car-riers through thin gate oxide, from drain to source, and from drainto body; control of the density and location of dopants to providehigh %'& ��( % &*)+) ratio; and finite subthreshold slope. These funda-mental limits have lead to the pessimistic predictions of the im-minent end of technological progress in semiconductor industry.However, the push to scale conventional MOSFET has continuedto show remarkable progress. Continued scaling and demand forperformance are pushing for lower supply voltage and� � , shorterchannel length, thinner gate oxide, higher body doping concentra-tion, and thinner Si film thickness. In addition, new materials suchas strained-Si channel on relaxed SiGe layer are on the semicon-ductor roadmap to enhance the mobility and current drive. Newdevice structures such as double-gate FinFETs and 3D circuits arebeing aggressively pursued for 65nm technology and beyond. Suchaggressive scaling and new device structures give rise to severalunique design issues which must be dealt with before any of thesetechnologies will gain mainstream acceptance.
SOI technology has been widely accepted for use in mainstreamhigh-performance logic applications in sub-90nm technologies. Thedesign issues resulting from the floating-body in partially depletedSOI device structure, such as parasitic bipolar effect and hysteretic� � variation, are now well-understood and circuit/design techniquesto mitigate these effects have been developed. However, as thescaling approaches various physical limits, unique/new SOI designissues continue to evolve/surface.
In this paper, we discuss the design challenges of sub-90nmCMOS circuits with particular emphasis on the implications andimpact of each individual device scaling element on circuit design., �.-/�#�0 #132 � �.14�� ��5 ���76 � � � 198: #132 � �;13�In CMOS technologies below 90nm, the Field Effect Transistorwill remain the fundamental design element of choice for the highspeed logic designer. Changes to this device will be evolutionaryrather than revolutionary. Improvements will be aimed at increas-ing mobility and decreasing extrinsic capacitance and resistance.Because a number of factors influence these parameters, multiple
mechanisms and structures are proposed for extending CMOS be-low 90nm. A subset of them are described below.,=<>� ?A@'B*CEDF@HGFGFI KJML G J C JONP� DFGQDFR'S9TVUWS9T3UX�FT3Y[Z3GQ@�CES�BThe Partially-depleted floating-body MOSFET was the first SOItransistor adopted for general high speed use, due in part to its pro-cessing similarities to common Bulk CMOS. The PD-SOI deviceis largely identical to the bulk device, except for the addition of aburied oxide (“BOX”) layer, isolating the body of the given devicefrom the bodies of other devices. Isolated below by BOX, to the leftand right by diffusion junction diodes, and above by gate insulator,the body’s potential “floats”; this voltage bias is influenced by bothstatic and dynamic effects. SOI offers three main contributions toimproved performance: (1) reduced junction capacitance, (2) loweraverage threshold, and (3) reduced body effect/source follower ac-tion. This performance is at the cost of some design complexityasserted by the floating body of the device, namely parasitic bipo-lar action and variable drive strength. The reader can reference[1, 2, 3] for a more thorough treatment of these effects. In addition,a number of CAD solutions have been developed to mitigate theseproblems [4, 6].,=< , \'ZVGFGFI 7JML G J C JMN]� DFGFDQR'S9T3UWS3T3UX�^TVY[Z3GF@HCES�BIn order to maintain balance of electric fields and capacitance withinthe SOI device, the active silicon thickness must be reduced withscaling. In the PD-SOI MOSFET, a “quasi-neutral region” existeddeep within the body which remained un-inverted even as the givendevice went into saturation. A number of device structure alter-ations have been asserted to preserve and extend this partial deple-tion. As active silicon scales thinner, however, the depletion regionwithin the body must expand laterally to satisfy the call for minoritycarriers at the gate oxide interface, to the point where the depletionregion completely encompasses or consumes the body. In thisfullydepleted FET, the threshold of the device is now defined by theamount of charge obtainable within the isolated body. Other noveldevices are by their nature intrinsically fully depleted, as we willsee shortly.,=< _ � CEB*@HDFT JON4� DFGFDQR'S9T ��` @HTVT J G
Figure 1: Schematic cross-section of a strained-Si nMOSFET.
Inducing tension on silicon substrates has been known to im-prove carrier mobility [7]. Specifically, tensile strain lifts the six-fold degeneracy in Silicon’s conduction band. Of these six conduc-tion sub-bands, the D2 and D4 band splits are exaggerated whenunder tension, which suppresses carrier scattering and enhancesmobility and drive current. Tensility has been achieved throughvarious means; mechanical strain and epitaxial strain are two pop-ular approaches. In one approach of mechanical strain, processingof the passivation nitride covering the device is altered to causestrain. In the epitaxial approach, a thin pseudomorphic silicon is
129
Permission to make digital or hard copies of all or part of this work forpersonal or classroom use is granted without fee provided that copies arenot made or distributed for profit or commercial advantage and thatcopies bear this notice and the full citation on the first page. To copyotherwise, to republish, to post on servers or to redistribute to lists,requires prior specific permission and/or a fee. ICCAD’03, November 11-13, 2003, San Jose, California, USA. Copyright 2003 ACM 1-58113-762-1/03/0011 ...$5.00.
Figure2: Schematicillustration of a FinFET; inset is a SEM mi-crographof a FinFET.
grown on a SiGesubstrate,causinglatticestrain. Both techniquesare capableof improving currentdrive by perhaps25% at satu-ration, andby perhaps50% in linear mode. Figure1 shows theschematiccross-sectionof astrained-SichannelMOSFET.,=< a S3Z3b3G J UW6c@HC J]-/�d� \ 13� YThedouble-gate(DG) MOSFEToffersanappealingbut temporaryreprieve to scaling.Themostpopularrealizationof theDG deviceis the “FinFET”, initially advancedby work publishedby Univer-sity of California- Berkeley [8]. TheFinFETis a non-planar, fullydepleted,double-gatedevice built uponan insulatingoxide layer;its structureis shown in Figure2. Thesedevicesachieve superiordrive currentthrough(a) effective suppressionof short-channelef-fect, (b) near-idealsubthresholdswing,and(c) an improvedbodyfactor. Further, this device is still eligible for the samematerialchangesadvocatedfor planardevices,namelymetalgatesandhigh-permittivity gatedielectrics.TheFinFETcarrieswith it, however,a new complication:device-widthquantization.In planardevices,theonly device width quantawasassertedby thegrid stepsizeinthedesigndatabaseused.In FinFETtechnology, devicewidthsaredispensedin unitsof wholefinsonly.
In the following section,we discusssomeof the major de-signissueswhichwill significantinfluenceoncircuitsin sub-90nmCMOStechnologies._ -/�ce��fg #13� �^6h�i� �� "j13�Technologiesof thedeep-submicronerahaverespondedto thenon-scalabilityof thresholdvoltagesbyaccommodatinghigherandhigherstatic IDD currents.For a while, this worked, but now a numberof problemsarisingfrom continuedscalingconfrontthedesigner.Theseissuesincludeexcessive power dissipationdensity, gateox-ide tunnelingcurrent,self heatingof the device andinterconnect,and a host of subsequentreliability issues. Theseissuesare re-viewedbelow._=<>� 6c@HC J UWCES9U � S N I � Z3T3T J GFDQT3k9l 5MJ @Hm'@Hk Jn� ZVB*B J TVCAs thegateoxide thicknessis scaledto maintaingatecontrol, � � ,andperformance,theoxidetunnelingleakageincreases(Figure3)[9, 10]. Nitridedoxide,whichreducestheleakageby orderof mag-nitude,hasbeenwidely usedin theindustryto containthis leakage.Nevertheless,theoxidetunnelingleakageincreasesby 2.5X for ev-ery 0.1nm decreasein oxidethickness.This amountsto over 30Xincreaseper technologygeneration.On the contrary, the channelleakageincreasesby about3X - 5X pertechnologygeneration.Assuch,theoxidetunnelingleakagehasquickly approached% &*)+) , andwill surpass% &*)+) at room temperaturefor oxide thicknessaround1.0nm or below, thusbecominga seriousconcernfor overall chipleakage.Furthermore,at1.0nm, thetunnelingleakagefor nitridedoxidereaches100A/ o�prq , while thetraditionalreliability criterionfor oxide leakageis 1.0 A/ o�p q . Recentstudyshowed thatat 100A/ o�psq , staticCMOSanddominocircuits in bulk CMOSstill ex-hibit “acceptablefunctionalityandnoisemargin” [9].
Figure4: (a)Differenttunnelingcomponentsin aSi/ tHuwv q /Si struc-ture:electrontunnelingfrom conductionband(ECB),electrontun-nelingfrom valanceband(EVB), andholetunnelingfrom valanceband(HVB) [10], and(b) MeasurednMOSgatecurrentcharacter-istics. %yxzx is thetotalgatecurrent,% x|{ is thegate-to-bodytunnelingcurrent[11].
Theoxide tunnelingcurrentconsistsof several componentsasshown in Figure4(a)[10]. Theelectrontunnelingfrom thevalanceband(EVB) generatesthesubstratecurrentin bothnMOSandpMOS.This substratecurrentcomponentis significantlylessthanthetun-nelingcurrentbetweenthegateandthechannel(Figure4(b)), andits effect canusuallybeneglectedin bulk CMOS.In partially de-pletedSOI devices,however, this substrate(body)currentcharges/dischargesthe body, thuschanging� � andaffecting circuit oper-ation [11]. As this gate-to-bodytunnelingcurrenthasa weakertemperaturedependencethanthe channelcurrent,andotherleak-ageandbody charging/discharging currentcomponents,its effectis morepronouncedat lower temperature[12]. Also noticethatasthe channellength is scaled,the gate-to-sourceandgate-to-draintunnelingcurrentsbecomeincreasinglysignificantdueto thefacts(1) thegate-source/drainoverlapregionsconstitutea largerportionof total gate length, and (2) the source/drainand extensionsareheavily doped,henceall theappliedvoltagedropsacrossthegateoxide.Figure5(a)shows thechangeof individualdevicestrengthin aPD-SOI staticCMOS inverter in different initial quiescentstatesdueto the presenceof the gate-to-bodytunnelingcurrent. Dependingon the initial conditionandinput transition,the inverterdelaycanslow-down or speed-upup to 10%- 15%in a 1.5V, 0.18 } m PD-SOI technologywith ~���)+) = 0.075}9p , �E�A�]�����F� nm,and�[� � ����*�
nm. In thesametechnology, it causesfrom 4% slow-down to6% speed-upat � � & C in thecritical pathdelaysof a 1.1GHz,115W, 170 million transistor, 64b Power4 PowerPCmicroprocessor(Figure5(b)) [12].Forpass-transistorbasedcircuits,studiesbasedona1.2V, 0.13}9pPD-SOItechnologywith ~�� & � � = 0.075 }9p , physical� �A� � � � �nm, �[� � � � � � nm,and�[�V�A��� �z�H� nmindicatedthatthegate-to-body tunnelingcurrentcancausedelaychangesup to 11% - over13% at room temperaturefor single-endedanddual-rail CPL cir-cuits[13]. In thesametechnology, standardCMOSlatchesexhibitdelaychangesupto 6%- 7%,while thefirst cycle latchset-uptime
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(a)
(b)
Figure5: (a) A partially depletedSOI CMOSinverterin quiescentstatewith input initially at “Low” and“High”, respectively, and(b)pathcountsvs percentchangesof pathdelaysdueto % x|{ at � � & Cfor critical pathsin Power4microprocessor[12].
for amaster-slacelatchpaircanchangeupto 12%- 20%[14]. Theresultsclearlyindicatedthatthegate-to-bodytunnelingcurrenthasto be carefully accountedfor in the timing of scaledSOI CMOScircuits.
Figure6 depictsthe changesin the strengthof cell transistorsin thequiescentstateof a 6T PD-SOICMOSSRAM cell. Detailedstudyon a 34Kb L1 directorySRAM showed that thepresenceofgate-to-bodytunnelingcurrentresultedin much moresignificantdegradationin the “Write” operationcomparedwith the “Read”operation.On theotherhand,theinitial cycleparasiticbipolardis-turb resultingfrom the aggregateeffect of unselectedcells in thesamebitline wasreduced[15].
The gate-to-bodytunnelingcurrentincreasesthe disparitybe-tweenthe1stswitchand2ndswitch. As shown in Figure5(a),for1stswitchwith input initially at “Low”, thebodyof nMOSsitsata diodecut-in voltage. So, thereis a “small” negative biasacrossthe gateandthe body, resultingin a “small” body-to-gatetunnel-ing currentto discharge the body and thereforelower pre-switchbodyvoltage.For the2ndswitchwith theinput initially at “High”,the body sits at “Ground”, and thereis full ���� acrossthe gateandthebody, resultingin a “large” gate-to-bodytunnelingcurrentto charge up the body andthereforehigherpre-switchbody volt-age[11, 12]. Thegate-to-bodytunnelingcurrentcanalsocause(or“aid”) thefull-depletionof thebodywhenthedevice is in accumu-lationmode(suchasin pass-gateconfigurationwith thesourceanddrain at “High” andgateat “Low”) [16]. In accumulationmode,thegate-to-bodytunnelingcurrentflows from thebodyto thegate,thusdischarging thebody. This extra bodydischarging currentcanpotentiallyresultin full-depletionof thebody in deviceswith thinSi film, causingsituationsof “quasi-depletion”.
Excessive gatetunnelingalsohaschangedastandingparadigmin power usage.In performance-sortinghardwareat thetester, it isexpectedthat theslowesthardwarehasthelongestchannels.Withlow long-channelsubthresholdleakage,theslow-sortchipsexhib-ited the loweststaticpower, but relatively high dynamicpower ata fixed frequency (due to larger gatearea). With gatetunnelingnow contributingapproximatelyhalf of totalstaticpowerconsump-
Figure6: A SOI CMOS SRAM cell in quiescentstate.Thepres-enceof gate-to-bodytunnelingcurrentchangesthestrengthof celltransistors[15].
Figure7: Temperaturerisein device junctionandat M1 asa func-tion of numberof active fingersin a multi-fingerdevices[17].
tion, theslow performancesorthardwarenow alsohashigh staticpower. Unfortunately, this high staticpower from gatetunnelingis relatively unresponsive to temperature,eliminatinga meansfor-merly availableto control leakage.Elevating VDD hasalsobeena powerful meansof enrichingfastbin performancesortedhard-ware, but hereagainthe thinner gateoxide becomesa problem;gateoxide intoleranceof overvoltagereducesthe amountof per-formanceavailableby supplyboost. The implication for productsin sub-90nmtechnologiesis that theoptimumdevice designpointis muchmorestronglydependenton applicationrequirements.Insomecases,a designis betterserved by usinga previous devicegenerationat highervoltagesand/ or shorterchannels._=< , ��J GF�#� J @HC|DQT3k�S9� KJM� DFR J @HT N �FT3C J B*RMS9T3T J R'CThe reducedthermalconductivity of low-K dielectricmaterialsintheinterconnectin additionto over two ordersof magnitudelowerthermalconductivity of theburiedoxide layer in SOI devices,re-sultsin local self-heatingof devices.This is particularlya concernfor devicesthatareon mostor all the time (e.g. biasingelements,currentsource,currentmirror, bleeder, etc.),andfor circuits withhigh duty cycle andslow slew rate(suchasclock distribution, I/Odriver) [1]. If the device channelis consideredasa heatsource,the bell-shapedspatial temperaturedistribution due to local self-heatinghasa characteristicwidth determinedby thethermaldiffu-sion length in silicon ( �����A�� �¡ q , which is a measureof the lengthover which the transienttemperaturefluctuationsare significant,where � is the thermaldiffusivity of silicon. � is the clock pe-riod. It is typically in the sub-50nm range). For a multi-fingerdevice within thesamebody, the spatialtemperaturedistributionsdueto individualactivefingeroverlapeachother(localself-heatingaffecting nearbyneighbors). This closethermalcouplingamongnearbyfingersincreasestheeffective thermalresistance,resultingin muchmoresevereself-heatingthanthat predictedfor a singleisolateddevice.
Figure7 shows the temperaturerise in thedevice junctionandatM1 basedonadetailed3D thermalanalysisfor a0.18 } m, ~ �¢)X)= 0.10 } m SOI technologywith tungstenlocal interconnectand7layersof Cu interconnect[17]. Noticethatasthenumberof activefinger increases,the temperaturerise (or equivalently, the thermalresistance)increases.The increasesaturatesat about9 active fin-gers,wherethe temperaturerise is about3 timesthat for the sin-
131
Figure8: Thermalresistanceasa functionof Si film thickness£ � �with theburiedoxidethickness£3&W¤ asa parameter[18].
gle finger. Noticethatthis saturationoccurswhenthedistancebe-tweenthecenterfingerandthefar-awayfingeris ontheorderof thecharacteristicwidth of thebell-shapedspatialtemperaturedistribu-tion. For scaledtechnologywith smallerandtighter groundrules,thesaturationwill occursathighernumberof activefingersandtheincreasein thermalresistancewill belargersincemorefingerswillbe thermallycoupled.This large increasein thermalresistanceisparticularlyimportantfor clock driver, line drive, andI/O drivers,wherelargemulti-fingerdevicesaretypically used.
Scaling/thinningof the Si film degradesthe thermalconduc-tivity andincreasesthethermalresistancedueto phonon-boundaryscattering.Figure8 showsthethermalresistanceasafunctionof Sifilm thicknesswith theburiedoxidethicknessasa parameter[18].Noticethattheincreaseis particularlysignificantfor thinnerSi filmwith thick buriedoxide.
Thelow thermalconductivity of enhanced-permittivity dielectricsalsocausesproblemswith theinterconnect’s performanceandreli-ability. Theinterconnect’sThermalCoefficientof Resistance(“TCR”)canrangeanywherefrom 0.1 to 1% perdegreeC. This resistancechangecanbean issuein high speedor long distancebusses.Aspower dissipatedin thewire aswell asin theFEOL increases,av-eragetemperaturesin thewire shouldbeanticipatedwhencalculat-ing RC delay. Thereliability implicationsarereviewedin thenextsection._=< _ J GFDQ@�bVDFGFDFCzI��FY[Y[Z J YSub-90nmtechnologiesdonot introducenew reliability exposures,but insteadshow mechanismsthathave evolvedwith reducedfilmthicknessesand structuredimensions. Wear-out mechanismsofconcernincludeHot CarrierInjection(HCI), NegativeBiasThresh-old Instability(NBTI), Time-DependentDielectricBreakdown (TDDB)in the front-end-of line and Electromigration(EM) in the back-end-of-line;advancedmodelsandCAD checkingtoolshave beendevelopedto anticipatethe magnitudeof theseeffectsspecifictothe applicationconditionsof a given product. HCI, or commonly“Hot electrons”occurwhenthelateralelectricfield in a MOSFETelevatesthe energy of minority carriersabove the ionization po-tential of a silicon lattice atom,observed mainly in N-MOSFETS[19]. ImpactIonizationgenerateselectron-holepairs;of the pairsthat do not spontaneouslyrecombine,thesefree chargescan al-ter the thresholdof the device over time, eitherby remainingres-ident, creatingnegative trap sites in the gateoxide, or by accu-mulatingpositive charge in the SOI floating body. The so-called“prompt shift” observed in devices at stressis actually HCI oc-curring out at the gate-overlap region of the rain. Hot carrieref-fectsarediminishingin sub-90nmtechnologiesdueto the reduc-tion in operatingvoltage. NBTI hasbecomea first-orderconcernin CMOS [22]. Affecting predominantlythe P-MOSFET, NBTIis thoughtto becausedby moistureoriginatingin photoresistma-terials becomingtrappedbelow the device’s nitride layer, whereoperatingconditionssuchashigh voltageand/ortemperaturecanionize it. This mobilecharge hastheability over time to increase
theabsolutevalueof P-MOSFETthreshold.As overdrive hasbe-comemore preciouswith voltagereduction,the impactof NBTIhasbecomeprofound. While incompletelyunderstood,NBTI hasbeenthoroughly characterizedand modeled,allowing designersto anticipatelong term performanceimpacts. As gate insulatorthicknesseshave beenreducedto maintain influenceover chan-nel inversion, its ability to maintainhigh dielectric integrity hasbeendiminished. Failure of thicker gate insulators(2.5nm andabove) tendedto be suddenin onset,and catastrophic.The ad-vent of thin gateinsulators,however, haspresenteda new failuremode,soft breakdown. [20]. High electricfieldssustainedover ex-tendedperiodsof timeagesthedielectric,causingsteadilyincreas-ing time-dependentbreakdown currents. At a cross-over point, thebreakdown reverts to the more traditional hard breakdown. It isbelievedthatsustainedfieldsslowly establishdefectcentersin thegateinsulator. Giventhattheseinsulatorsarenow lessthan6 atomsthick, defecttoleranceis understandablylow. Theadditionof otherspeciesin theSiO2 to mitigatedirect tunneling currentsis knownto modulatetheseeffects. TDDB currentsareat least2 decadeshigher than, and quite different from, typical tunnelingcurrents.TDDB is alsoaccuratelycapturedin reliability lifetime modelingsoftware. Electromigrationeffects in sub-90nmCMOS areexac-erbatedby the rising averagetemperaturesin CMOS, andby theinferior thermalgenerations,except that scalinghasinduceddra-maticincreasesin instantaneouscurrentdensitiesandjouleheating.EM is well modeledandcan be checked asa chip releasecrite-ria. Otherreliability mechanismsaremorecloselyassociatedwiththe productsapplicationenvironment. Gateoxide damagefromElectrostaticDischarge(ESD)duringcomponenthandling,assem-bly, or systemmalfunctioncan causefailure modespost-testingthat are not discovereduntil the part is in the field. SoftErrorsinducedby materials(alphaparticles)or extraterrestrially(cosmicrays)usedto be confinedto upsetsof the 6-device SRAM mem-ory cell. In sub-90nmtechnologies,logic circuitry andlatchesarebecomingincreasinglyvulnerable.CAD solutionsfor addressingSERin logic areonly now becomingavailable,andonly canad-dressa portionof thiscomplex problem.
parasiticbipolar transistor. The parasiticbipolar currentand theFET leakage(causedby the lowered � � dueto high bodyvoltage)result in a lossof charge on the precharge (or dynamic)nodeandcanpotentiallycausecircuit failure. The effect is typically moresignificantat first cycle after long time of dormancy. In SRAMbitline structure,theaggregateparasiticbipolareffect of theunse-lectedcellson theselectedbitline causesdisturbin theRead/Writeoperationsandlimits thenumberof cells thatcanbeattachedto abitline pair. Variouscircuit/designtechniquesto mitigatethepara-sitic bipolareffect have beendeveloped[25, 26, 2, 27, 28, 29].
While the “basewidth” of the parasiticbipolar transistorde-creasesasthe channellength is scaled,the reductionin � �=� re-ducestheoverdrive availableacrossthebody-sourcejunction.Thehigh dopingconcentrationandsteepprofile in scaleddevices in-creasethebaseGummelnumber, thusreducingthecurrentgainoftheparasiticbipolar transistor. Thethinningof theSi film reducesthe base-emitter(body-source)junction area. Hencethe parasiticbipolareffectbecomeslesssignificantwith respectto theincreasedFET currentdrive. Thereduced-� � FET leakageis alsocontained,relative to the increasedFET currentdrive, dueto the lower ����andlow bodyfactorin high-performancelow- � � transistor.a=<>�9< , �7IMY[C J B J CEDFR � � 2 @'B*DF@HCEDFS9T«@HT Nr5 S�¬U 2 S9GFCE@Hk J �F®nUL @HR'C¯�FS9T3DQ°±@�CEDFS3TThe hysteretic � � variationdue to long time constantsof variousbodycharging/discharging mechanisms(impactionizationcurrent,GIDL, andjunctionleakage/current)andgain/loseof bodychargesthroughthe switchingcycleshaslong beenthe mostchallengingtaskin thedesignof floating-bodySOI CMOScircuits [25, 2, 30,31, 32, 33, 34,35, 36] Variousbodyvoltageestimationandbound-ing schemeshave beendevelopedfor circuit simulationandstatictiming [37, 4].
Theimpactionizationcurrentplaysanimportantrole in deter-mining the SOI floating-bodybehavior. As � �=� is scaled,con-ventionalwisdom basedon electric field inducedimpact ioniza-tion mechanismexpectssignificantreductionin theimpactioniza-tion current.However, recentstudyon state-of-the-artSOI devicesshowed that theonsetof thekink in the I-V characteristicsis wellbelow thesilicon bandgap(²jx�³ 1.2 eV), andtheunderlyinglowvoltageionizationmechanismcouldnot be explainedby the con-ventionalwisdom[38, 39]. Experimentaldataindicatedthatwhilethedriving forceof impactionizationathigh � �=� wastheelectricfield inducedby thedrain,it switchesto latticetemperatureasdrainvoltageis reducedto below 1.2V [38, 39]. This thermallyassistedimpactionizationmechanismat low voltageis particularlyimpor-tant in scaledSOI devices/circuitssinceself-heatingin the thin Sifilm wouldsignificantlyenhancethismechanism.Scaling/thinningof Si film hasother implication on hysteretic � � variation,whichwill be discussedlater. Furthermore,high doping concentrationandsteepdopinggradientin scaleddevicesincreasesthereversed-biasedband-to-bandjunction tunnelingcurrentbetweenthe drainandthebody, resultingin higherbodychargingcurrent.
One of the commonlyusedgaugefor hysteretic � � variation(or “history effect” asknown in SOI community)is the disparityin thebodyvoltagesanddelaysbetweentheso-called“1st switch”and“2nd” switch [2, 33, 11]. The “1st switch” refersto the casewhereacircuit (e.g.inverter)startsin aninitial quiescentstatewithinput at “Low” and thenundergoesan input-rising transition. Inthiscase,theinitial DC equilibriumbodypotentialof theswitchingnMOSis determinedprimarily by thebalanceof theback-to-backdrain-to-bodyandbody-to-sourcediodes.The“2nd” switchrefersto the casewherethe circuit is initially in a quiescentstatewithinput at “High”. The input first falls, and then rises(hencethename“2nd switch”). For this case,thepre-switchbodyvoltageisdeterminedby capacitive couplingbetweenthedrainandthebody.In early generationsof SOI technology(e.g. 0.25 } m and 0.18
} m), the pre-switchbody voltageis typically higher(thuscircuitdelaylower) for the 1st switch dueto high diodebalancevoltageat high � �� . For scaleddevices,the lower � �� resultsin lowerdiode balancevoltagewhile the capacitive coupling betweenthedrain andbody increasesdue to higherdopingconcentrationandsteepdopinggradient. Thus, the pre-switchbody voltagefor 1stswitch decreases,while that for the 2ndswitch increases,andthe2ndswitchtendsto becomefasterthanthe1stswitch.a=<>�9< _ �KDFk `VJ B � ��� � �Q�SOI devicesaretypically designedwith a larger ����� � ��� (thresholdvoltageat low drain bias)comparedwith bulk CMOS [40]. Thisis becauseas the drain voltageis raised,the floating-bodyeffectcausesthe thresholdvoltageto decrease,resultingin significantlylower � ��� �¢��� (thresholdvoltageat high drain bias). Thus,higher����� � �Q� is necessaryto maintainadequate� ��� ���z� to containleakage.The higher ����� � �Q� hasadverseeffects on the performance,espe-cially for circuit configurationswhere devices spendsubstantialamountof time in linear region during switching transient,suchaspass-gate,stackdevices,andSRAM bitline structure,etc.. It isalsowell known that the � � lossin passinga “High” statethrougha nMOS-onlypass-gatedegradesboth the performanceandnoisemargin, especiallyat low supplyvoltage.While full transmission-gatecanandshouldbeusedto alleviatethis problemfor logic cir-cuits, it is not practicalandoffersno benefitfor SRAM read/writepass-transistorsdueto impacton density. Fortunately, it hasbeenshown that as � �� is scaled,the decreasein � ��� ����� dueto float-ing bodyeffect becomesmuchlessdueto reductionin theelectricfield inducedimpact ionization. Thus,for low � �� , the require-mentsfor higher ����� � ��� in SOI devices is relaxed. Furthermore,theoptimumSOI device designmatchesthe %'&*)X) to thoseof bulkCMOSat theshortestchannellengthof thegiventechnologyat thechipoperatingtemperature.Thisallowshigher% &*)X) at thenominalchannellength(sinceSOI device hasbettershort-channelroll-off)androomtemperaturefor theSOI devices,thusalleviating there-quirementfor higher � ��� � �Q� aswell [40].a=< , � R'@HGFDFTVk�S9� � DFUX\HDFGF®�´7�¢B*S9®µ? U ��� �CES¶\ U ��� �Themajorbenefitsof scaling/thinningof Si film are: (1) reductionof junction capacitancefor performanceimprovement,(2) bettershortchannelroll-off, (3) bettersoft error rate (SER)due to lesschargegeneration/collectionvolumn.In addition,thehistoryeffect(disparitybetween1stswitchand2ndswitch)is alsoreduced.Thereducedjunctioncapacitanceimprovesdelaysof both1stand2ndswitches.However, for the2ndswitch(which tendsto bethefasteronein scaledtechnologiesasmentionedpreviously), the reducedjunction capacitancereducesthe capacitive couplingbetweenthedrainandbody, causinga decreasein thepre-switchbodyvoltagefor the2ndswitch,thuspartially offsetstheperformanceimprove-ment[11].
On thedown side,thethinningof Si film degradesthebodyre-sistance,renderingbodycontactlesseffective andeventuallyuse-less. Self-heatingbecomesmoresevere. Furthermore,asthefilmthicknessis scaledto below 50nm,thedevicemaybecomedynam-ically fully-depleted(or quasi-depleted),wherethebodywouldbe-comefully-depletedundercertainbiasconditionsor duringcertaincircuit switchingtransient. This necessitatesan unified partially-depleted/full-depleteddevicemodelwith smoothandseamlesstran-sition amongdifferentmodesof operation.Typically, this is mod-eledby varyingthebuilt-in potentialbetweenthebodyandsourcejunction, thuschangingthe amountof body chargesthe body-to-sourcediode can sink for a given changein the body potential.Thepresenceof dynamicfull depletionalsocomplicatesthestatictiming methodology, wherethe variousbody voltageboundses-tablishedbasedon the assumptionof partial-depletionneedto be
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extendedto cover this new phenomena.Notice that dynamicde-pletion· tendsto occurfirst in long channel,low- � � devices. Forshortchanneldevices, the proximity of the heavily dopedHALOincreasestheeffective bodydoping,andthedevice is lesslikely tobedynamicallyfully-depleted.a=< _ � CEB*@HDFT JMN4� DFGFDFR'S3T ��` @HT3T J GStrained-SisurfacechannelCMOShasrecentlyemergedasastrongcontenderfor future high-performanceapplicationsdueto highermobility andimproved % & � [41, 7]. The latticemismatchbetweenthe Si channeland the underlying relaxed SiGe layer resultsinbiaxial tensilestrain, which reducesthe intervalley scatteringbyincreasingsubbandsplitting andenhancescarriertransportby re-ducingconductivity effectivemass.Combiningstrained-SichannelandSOI (Figure1) complementsthe improved % & � of strained-Sichanneldevice with thebenefitof SOI [42, 43] However, therearequite a few designimplications. The narrower bandgapof SiGelayercausesheterostructuralbandoffset,which reduces� � andin-creases% &z)+) . The mobility enhancementfor nMOS and pMOSmay be quite different due to device designandprocessintegra-tion constraints[41, 7], which may upsetthe ¸ (p/n strength)ra-tio while migrating existing designs. The tensilestrain is “biax-ial”, somobility enhancement(therefore% & � improvement)arethesamealongX- andY-axis. However, in somehigh densitydesign(e.g. SRAM cell), “bent gates”at
��� & anglearesometimesused,which would result in disparity in mobility enhancementand % & �improvement. The SiGe layer has7¹ higherdielectric constantand10¹ lower built-in potentialduethenarrower bandgap,result-ing in higher junction capacitance[41, 43]. Furthermore,higherbodydopingdensitycouldbeneededto compensatefor the � � re-duction,whichfurtherincreasesthejunctioncapacitance.Thether-malconductivity of theSiGelayeris about15X lower thanthatforSi, thusaggravatingtheself-heatingeffect [41].
The presenceof the SiGe layer also significantly affects thefloating-bodyeffect[43]. For20¹ Gecontent,thebandgapisabout90¹ of that for Si. This narrower bandgapresultsin a higher( ³10X) intrinsic carrier density º � , and thus proportionallyhigherrecombinationcurrentat the body-to-sourcejunction. However,the narrower bandgapand higher dielectric constantof the SiGelayer, andthe higherbody dopingto compensatefor the lowered� � causedby thebandoffset,give rise to largerband-to-bandtun-neling currentandtrapped-assistedtunnelingcurrentat thedrain-to-bodyjunction. The lattereffect mayoverpower the increaseinrecombinationcurrentat the body-to-sourcejunction, resultinginmoresignificantfloating-bodyeffect.a=< a S3Z3b3G J UW6c@HC J]-/�d� \ 13� YAlthough the FinFET is still a CMOStransistor, its physicalreal-izationrequiresdesignaccommodation.Section2.4alludedto thequantizednatureof non-planardoublegatedMOSFETs. The de-vicewidth quantumfor theFinFETis theheightH of thefin. Eachfin provides 2H of device width. Designersin planar technolo-gieshave beenrelatively unconstrainedin selecteddevice widths,suchthatappropriateratiosof drivestrengthin N-MOSFETandP-MOSFETdeviceswill achieve desiredtrade-offs in performance,power consumption,andnoiseimmunity. To achieve comparableflexibility usingFinFETs,morefins of potentiallylongerchannellengthsmay be neededto achieve a given betaratio. If not mon-itored,active andstandbypower canbe sub-optimal.Conversely,selectedfunctionssuchasdigital delaylinesor programmablecur-rentsourcesmayexploit thefixedincrementsthatfins enable.Re-strictionsin deviceorientationto reduceacross-chiplinewidth vari-ationarebecomingcommonin VLSI, andthefin enjoysthosesamebenefits.By orientingfin channelsin parallel,imageclockdistribu-tion andpower conventionscomparableto thosein planardevicesmayberealized.
» ���� ¼� � �h5V5A1 �76 19�½� � g� ? ? �f��" �d� � � 19�DesignandCAD issuesrelatedto bothpartially andfully depletedSOI circuits have beendiscussedat lengthin the literature[2][6].In addition,recentresearchhasalsofocusedon the issueof gate-leakagereduction[5]. However the CAD challengesarisingwiththe new device structuressuchasdouble-gateMOSFETsin sub-65nmcircuit technologieshasnot beendiscussed.In this section,we focuson the impactof double-gateMOSFETson Designau-tomationtools.
Designautomationhasanimportantrole in theintroductionofFinFETs,andalsomustaddressnew complexities. Dual-gatedde-vicesdiffer significantlyfrom their traditionalCMOSdevicecoun-terpartsby providing two gatecontrolsfor thesamechannel.Thus,they provideapproximatelytwice thedrivecurrentbut alsopresenttwice the capacitanceto previous stage. If the two gatesare al-waystied togetheror the backgateis usedasa biasterminal formodulatingdevice threshold,the impacton DA toolswould benomore severe than the introductionof a typical scaledtechnologywith multiple thresholdvoltages. The major innovation that willcauseDA tools to becomeinadequateis the useof two gatesofdouble-gateMOSFETto becontrolledby independentsignals.Inthat case,a single device can provide an OR function andmanyof the DA tools would be impacted.In the following, we discussthe impactof double-gateMOSFETtechnologieson varioustoolsstartingfrom fron-endsynthesistool.
Synthesis:Standard-Cellsynthesiswill not beimpactedexten-sively sinceit doesnot requireselectionof transistortopologieswhich arepreselectedin the standard-celllibrary. However, tran-sistorlevel synthesismustbeawareof theflexibility of dualgateddevices in order to exploit functionality of both the gatesfor im-plementingsingle device OR function. Sincethe thresholdvolt-agein double-gatedevicescanbedynamicallyvariedby changingthebackgatesignal,this presentsa new opportunityfor logic syn-thesisto exploit the performancevs power consumptiontradeoff.For new designs,synthesisof logical functionsfrom higher leveldescriptionsmay be performedin FinFET technologies,but withappropriateaccommodationfor quantization.
PlacementandRouting:Becauseof theability to performOR-ing of two signalswith a singledevice, CMOScellsmaynot haveanequalnumberof P andN devices. Thusthecells maybecomenon-rectangular. Effective block placementshouldhave theabilityto handlethenew shapes.Theimpacton routingwill probablynotbe severe. The ability to provide two signalsto the samedevicemayplacemoreconstraintson thelocationof cell pins.
SimulationandTuning: Transistorlevel simulationmustcon-sideranadditionalgateterminalof double-gatedevices.Tuningofexisting layout topologieswill probablynot be impactedseverely,but tuning of schematicswill have to considerthe new option ofalternatewaysof fingeringanOR device.
Layout and Migration: Creatingnew cell layouts with dualgateddevices will presentnew challenges. However, since thetrendis toward fewer cell topologies(e.g.,primitive gatessuchasNAND2, NAND3, NOR2,simpleAOIsetc),manualdesignshouldbe able to addressthe new challengesof how to createrectangu-lar cells andhow to utilize the additionalinterconnectcapabilityprovidedby thebackgatepoly. Migration from a singlegatetech-nology to a dual gatetechnologywill presentconsiderablechal-lengessinceit violatesoneof the premisesof migration,namelythepreservationof topology. Theconversionof planardesignsintodiscretefinsmaybeachieved“behindthecovers”,for themostparttransparentto thedesigner. Transistorlayoutconversionandroundoff to theclosestnumberof Finsmaybeautomated.Thiscapabilitywill beimportantfor designsmigratedinto FinFETtechnologies.
Checking:Extractionmustrecognizenew typesof devicesde-finedwith two gates.A new level of interconnectmustbehandledand back and front gatesignal connectivity must be determined.
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Figure9: Plot showing reductionin areaof control with scaling.Cross-chiplatency with absolutediesizeheldconstantis observedto increaseeachgeneration.
techniqueto implement3D integration calls for the independentfabricationof eachlayer followed by handle-wafer removal andbonding[45]. Figure10 illustratesthe technique.Multiple tech-nologiesmustconvergeto realizethisstructurein manufacturing:¿ Stackedsubstratealignmentcapability¿ Temperaturemanagementvia electricalor mechanicalmeans¿ 3D Modelingof device andinterconnect,CAD productivity¿ Defectmanagement,rework capability¿ Manufacturingcost3D integrationmay be achieved with existing processesandtool-ing, with only minor additional innovation necessary. New ad-vancesneededbeforethis conceptis embracedby theindustryre-sidein themanagementof manufacturingcostanddefectdensity.¾=< , - S9G J R'Z3GF@MB � S3® L ZVCEDFT3kThedevelopmentof smallswitchesexhibiting gainrepresentsoneof themostexciting frontiersin our industry. Building transistorsat molecularscaleshaslong beena goalin thedrive to achieve bi-ological computationefficiency. The valueof sucha systemis inits ability to respondto eachof thechallengespresentedby scaling- power, performance,area,reliability, andcost. A numberof or-ganicmoleculeshavebeenexamined[46], andmuchof thework innano-electronicsand micro-electronic-machining(MEMS) is ap-plicable.TheCarbonnanotubeField-effect-Transistor(CNFET)isthefarthestalongof any moleculardevice. Carbon,whenproperlyformedinto self-closingtubes,presentsfield-effect behavior, andexhibits gain, comparableor superiorto state-of-the-artSilicon-basedMOSFETs.Figure11 shows a schematicrepresentationof aCNFETAs expectedtherearesubstantialhurdleswhich first needto beovercome.¿ DiameterandChirality of thenanotubemustbetightly con-
trolled. Bandgapof thenanubeis a functionof its diameter.¿ Nanotubesemiconductorsneedtobedifferentiatedfromnan-otubemetals,which form regularly duringprocessing.¿ Nanotubeslike to grow in bundles.Separationanddistribu-tion of nanotubesis a key requirement¿ CNT placementanddevice connectivity mustbedeterminedby thedesigner. A numberof techniqueshavebeenproposed.Proposeddevicesusingotherorganicmoleculeshave advo-cated“self-organizingsystems”to overcomethequestionofhow to assertstructureanddisciplineinto thesedevices.¿ Interconnectsstill remainto bedefinedbetweenCNTs. Thecontactto a CNT is a Schottky barrierdiode,so innovativetechniqueswill beneededto achieve goodlevel transfer.
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Along with commonscaling,designerproductivity hashadto alsoincreaseÀ in orderto harnessthe larger transistorcountmadeavail-able. At theCNFETcountwhich maysomeday be integratedona commonsubstrate,CAD productivity tools will be an essentialenablement.Á � S9T3R'GQZ3Y[DFS9TWehavediscussedtheimplicationsandimpactof devicescalingonthecircuit designof sub-90nmCMOScircuits.Major designissuessuchasgate-to-bodytunneling,self-heating,reliability issues,andprocessvariationswerediscussed.Thegateoxide tunnelingleak-agehasemergedto becomea seriousconcernandhasto be care-fully consideredfor propercircuit operationand timing. Propermodelingandconsiderationof thermalresistanceincreasedue tothermalcouplingin multi-fingerdevicesandin thin Si film arecru-cial for accuratelypredictingtheself-heatingeffect. New SOI de-signissuessuchasVt modulationdueto leakage,low-voltageim-pactionization,andhigher ����� � �Q� to maintainadequate� ��� ���z� , thatwill surfacedue to device scalingwere also discussed.StrainedSi-channelon SOI improvesthedevice mobility andcurrentdrivewith new materialproperties,devicedesignconsiderations,andcir-cuit implications.Looking beyond65nmtechnologies,designandCAD issuesrelatedto device structuressuchasdoublegateFin-FETswerealsodiscussedandsomeemergingtrendswereoutlined.
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