A Versatile LowA Versatile Low--Jitter PLLJitter PLLin 90nm CMOS forin 90nm CMOS for

SerDesSerDes Transmitter ClockingTransmitter ClockingA. A. LokeLoke, R. Barnes, T., R. Barnes, T.--T. Wee, M. T. Wee, M. OshimaOshima*, C. Moore, *, C. Moore, R. Kennedy, J. Barnes, R. Zimmer, K. R. Kennedy, J. Barnes, R. Zimmer, K. AraveArave, H. Pang, , H. Pang,

T. T. CynkarCynkar, A. , A. VolzVolz, J. , J. PfiesterPfiester, R. Martin, R. Miller,, R. Martin, R. Miller,D. Hood, G. Motley, E. Rojas, T. D. Hood, G. Motley, E. Rojas, T. WalleyWalley & M. & M. GilsdorfGilsdorf

Enterprise ASIC Enterprise ASIC SerDesSerDes R&DR&DFort Collins, Colorado & *Santa Clara, CaliforniaFort Collins, Colorado & *Santa Clara, California

OutlineOutline•• ObjectiveObjective•• DualDual--Path PLL ArchitecturePath PLL Architecture•• Design ConsiderationsDesign Considerations•• MeasurementsMeasurements•• Performance SummaryPerformance Summary•• ConclusionsConclusions

ObjectiveObjective

•• TxTx clocking for embedded clocking for embedded wirelinewireline SerDesSerDes applications applications (Ethernet, (Ethernet, FibreChannelFibreChannel, , PCIePCIe, SAS/SATA, XFI, SONET, , SAS/SATA, XFI, SONET, ……))

•• Support of multiple rates, protocols & reference clock Support of multiple rates, protocols & reference clock frequencies per frequencies per TxTx--Rx channelRx channel

•• Backward compatibility with existing serial linksBackward compatibility with existing serial links•• Strategy: flexible loop dynamics, wide tuning range, Strategy: flexible loop dynamics, wide tuning range,

versatile divider configurations & small sizeversatile divider configurations & small size

PLLPLLREFCLKREFCLK

ChannelChannelRECEIVERRECEIVERTRANSMITTERTRANSMITTER

ParallelParallelDataData

OutlineOutline•• ObjectiveObjective•• DualDual--Path PLL ArchitecturePath PLL Architecture•• Design ConsiderationsDesign Considerations•• MeasurementsMeasurements•• Performance SummaryPerformance Summary•• ConclusionsConclusions

DualDual--Path PLL ArchitecturePath PLL Architecture

PFDPFD

KKpppp

+REFCLKREFCLK

KKipip

CalibrationCalibrationLogicLogic

ProgrammableProgrammableDivider (Divider (÷÷NN ))

DIVCLKDIVCLK

UPUP

DNDN

+

VVREF1REF1

VVREF2REF2

RSTRST

CCipip

CCpppp

LCLC--VCOVCO

Proportional PathProportional Path

Integrating PathIntegrating Path

PLLPLLOUTPUTOUTPUTCLOCKCLOCK

KKvppvpp

KKvipvipΣ

CoarseCoarseTuningTuning

PLL ClosedPLL Closed--Loop DynamicsLoop DynamicsTransfer function has 1 zero (Transfer function has 1 zero (z) & 2 poles () & 2 poles (p1 & & p2))

22

2

2 nn

n

sszs

zH(s)

ωζωω

+++

⋅≈

ip

vipip

vpppp

CKK

N

KK

2=ζ

NCKK

ip

vipip

n =ω

For For overdampedoverdamped case (case (ζ > 1), > 1), z cancels cancels p1

NKK

p vppppndB =≈−≈− ζωω 223

ip

pp

KK

∝ζ

bandwidthbandwidth

inverse peakinginverse peaking

OutlineOutline•• ObjectiveObjective•• DualDual--Path PLL ArchitecturePath PLL Architecture•• Design ConsiderationsDesign Considerations

–– Loop Filter Proportional PathLoop Filter Proportional Path–– Mismatch in Loop Filter Phase OffsetsMismatch in Loop Filter Phase Offsets–– LCLC--VCO ArchitectureVCO Architecture–– InversionInversion--Mode Mode nFETnFET VaractorsVaractors–– Tuning Range FactorsTuning Range Factors

•• MeasurementsMeasurements•• Performance SummaryPerformance Summary•• ConclusionsConclusions

Loop Filter Proportional PathLoop Filter Proportional Pathbasic basic lowpasslowpass phase phase lead compensation Timing DiagramTiming DiagramUPUP lead compensation

•• Stretch Stretch VVOUTOUT pulse in time to reduce reference spurpulse in time to reduce reference spur•• VVOUTOUT pulse ~50% duty cycle, independent of divider ratiopulse ~50% duty cycle, independent of divider ratio•• ResistorlessResistorless areaarea--efficientefficient

REFCLKREFCLK

DIVCLKDIVCLK

VVREF1REF1

DNDN

UPUP

DNDN

UPUP RSTRST

VVOUTOUTDNDN

VVREF1REF1

RSTRSTREFCLKREFCLKDIVCLKDIVCLK

VVOUTOUT

Proportional Path ImplementationProportional Path Implementation

W/2 switch W/2 switch feedthroughfeedthrough & & charge cancellation charge cancellation FETsFETs

IIREFREF

RSTRST

RSTRST

UPUP

DNDN

UPUPdlydly

DNDNdlydly

VVREF1REF1

UPUPdlydly UPUP

DNDNdlydly DNDN

VVOUTOUT

VVT T -- trackingtrackingbiasbias

IIcpcp

RSTRSTREFCLKREFCLKDIVCLKDIVCLK

UPUPdlydlyUPUP

DNDNdlydlyDNDN

IIcpcp

Effect of Mismatched Loop Filter Effect of Mismatched Loop Filter Phase OffsetsPhase Offsets

φφos,ppos,pp

Sim

ulat

ed P

LLSi

mul

ated

PLL

RM

S Ji

tter (

RM

S Ji

tter (

psps))

||φφos,ppos,pp –– φφos,ipos,ip| (| (psps))00 100100 200200 300300

0.00.00.20.20.40.40.60.60.80.81.01.01.21.2

Σ

Σ

φφos,ipos,ip

IdealIdealProportionalProportional

PathPath

IdealIdealIntegratingIntegrating

PathPath

Σ

VCOVCO

÷÷NN

+

++

++

PFDPFD

•• Minimize Minimize φφosos mismatch between all loop filter paths to mismatch between all loop filter paths to reduce PLL jitterreduce PLL jitter

•• Charge pump dynamic range issue: need big switches for Charge pump dynamic range issue: need big switches for large large IIcpcp but may compromise but may compromise φφosos at small at small IIcpcp

LCLC--VCO ArchitectureVCO Architecture

Calibration Setting (CS)Calibration Setting (CS)

Proportional Path TuningProportional Path Tuning

Integrating Path TuningIntegrating Path Tuning

AmplitudeAmplitudeControlControl

1212

1010

1010

127127

127127

44

multilevelmultilevelhelicalhelical

inductorsinductors

analoganalog

PVTPVT--insensitiveinsensitivecapacitance capacitance

averaging duringaveraging duringcalibrationcalibration

analoganalog

digitaldigital

differentialdifferentialoutputsoutputs

InversionInversion--Mode Mode nFETnFET VaractorsVaractors

CC--VV flatness for flatness for supply noise supply noise rejectionrejection

VVcontrolcontrol

VVgategate

inversioninversion

depletiondepletion

1.01.0 0.70.71.31.31.01.0

0.00.0

VVgategate (V)(V)

VVcontrol

control (V)(V)

Sim

ulat

ed

Sim

ulat

ed CC

gate

gate

0.50.5

•• Critical for Critical for integration integration with digital with digital systemssystems

Tuning Range FactorsTuning Range Factors•• Large tuning range Large tuning range maximize maximize CCmaxmax::CCminmin ratioratio•• Large Large CCmaxmax large large WW ×× LL•• Small Small CCminmin long long LL to reduce to reduce CCovov & & CCsubsub, reduced , reduced QQCC

minimize wiring minimize wiring parasiticsparasitics (contact(contact--toto--poly)poly)•• Reduce channel mechanical stress Reduce channel mechanical stress increase increase QQCC

pp--SiSi

sourcesource

nitridenitridespacerspacer

poly poly gategate

contactcontact

draindrainhalo/pockethalo/pocket

implantsimplantsSTISTI

lowlowdopingdoping

highhighdopingdoping

OutlineOutline•• ObjectiveObjective•• DualDual--Path PLL ArchitecturePath PLL Architecture•• Design ConsiderationsDesign Considerations•• MeasurementsMeasurements

–– PLL ClosedPLL Closed--Loop DynamicsLoop Dynamics–– PLL Output JitterPLL Output Jitter–– VCO TuningVCO Tuning–– VDD & Temperature SensitivitiesVDD & Temperature Sensitivities–– Die MicrographDie Micrograph

•• Performance SummaryPerformance Summary•• ConclusionsConclusions

11

0011

00

00

55

1010

IntegratingIntegrating

Path GainPath Gain

Proportional

ProportionalPath Gain

Path Gain

110011

00

00

55

1010

ModeledModeled

MeasuredMeasured

001100

11

00

22

44

00

1100

11

00

22

44

PLL ClosedPLL Closed--Loop DynamicsLoop Dynamics-- 3

dB B

W (M

Hz)

3dB

BW

(MH

z)

Peak

ing

(dB

)Pe

akin

g (d

B)

Peak

ing

(dB

)Pe

akin

g (d

B)

-- 3dB

BW

(MH

z)3d

B B

W (M

Hz)

IntegratingIntegrating

Path GainPath Gain

Proportional

ProportionalPath Gain

Path Gain

PLL Output Spectrum @ 10Gb/sPLL Output Spectrum @ 10Gb/s

•• 101010... data pattern (no ISI), 101010... data pattern (no ISI), NN=50=50•• Extracted RMS Jitter = 0.81ps Extracted RMS Jitter = 0.81ps

5.05.04.74.7 5.35.3

00

--2020

--4040

--6060

--80

Rel

ativ

e Po

wer

(dB

)R

elat

ive

Pow

er (d

B)

--54.8dBc54.8dBcreferencereferencespurspur

0.2GHz0.2GHz

80

Frequency (GHz)Frequency (GHz)

VCO Coarse Frequency TuningVCO Coarse Frequency Tuning

VCO Frequency (GHz)VCO Frequency (GHz) (log scale)(log scale)

Cal

ibra

tion

Setti

ng

Cal

ibra

tion

Setti

ng

(( CSCS ))

22 33 44 55 66 77 88 99 1010 1212002020404060608080

100100120120

•• CSCS = coarse= coarse--tuning tuning varactorvaractor inputs tied to inputs tied to VVDDDD•• 7 VCO variants shown, each with 45% tuning range7 VCO variants shown, each with 45% tuning range•• Coverage of practical Coverage of practical SerDesSerDes protocolsprotocols•• Loop filter outputs midLoop filter outputs mid--railed during calibrationrailed during calibration

VCO PostVCO Post--Calibration TuningCalibration TuningC

SCS

coarse tuning curvescoarse tuning curvesacross across VVDD DD & Temp corners & Temp corners

VCO FrequencyVCO Frequency

BBAA

0022446688

1010

Frequency (GHz)Frequency (GHz)

CSCS

Ran

geR

ange

22 33 44 66 88 101055 77 0022446688

1010

Frequency (GHz)Frequency (GHz)22 33 44 66 88 101055 77 00

22446688

1010

Frequency (GHz)Frequency (GHz)22 33 44 66 88 101055 77

0.90.9--1.1V, 01.1V, 0--110110°°CC 0.90.9--1.1V @ 851.1V @ 85°°CC 00--110110°°C @ 1.0VC @ 1.0V

VCO has VCO has ±±10 10 varactorsvaractors of tuning of tuning to correct for VCO sensitivities to to correct for VCO sensitivities to VVDDDD & Temp drifts after calibration& Temp drifts after calibration

Measure Measure CSCS RangeRange (A(A––B)B)

7 VCO7 VCOvariantsvariants

VCO Temperature SensitivitiesVCO Temperature Sensitivities

LC

RC RL2

2

2

22

11

111

1

11

L

C

C

L

Q

QLC

LCR

LCR

LC +

+⋅≡

−

−⋅=ω

For For QQLL << << QQCC::

TCRL

RdTd L

LC

⋅−≈ 2

2

ωω

,

TCRLCR

dTdC L

L

⋅−≈222

,ω

0022446688

1010

Frequency (GHz)Frequency (GHz)22 33 44 66 88 101055 77

00--110110°°C @ 1.0VC @ 1.0V

CSCS

Ran

geR

ange

Resonance for Resonance for lossylossy LCLC tank:tank:

ω

Die MicrographDie Micrograph

ProporPropor--tionaltionalPathPath

& & VVREF1REF1

PFDPFD DividerDivider

IntegratingIntegratingPathPath

ChargeChargePumpPump

VVREF2REF2 Op AmpOp Amp

IntegratorIntegrator

CapacitorCapacitor

OpOpAmpAmp

200

200

µµ mm

280 280 µµmm

VCOVCO

Performance SummaryPerformance SummaryTechnologyTechnology 90nm CMOS (8M)90nm CMOS (8M)SupplySupply 1.0 V (core)1.0 V (core)RMS JitterRMS Jitter 0.81 0.81 psps @ 10 @ 10 Gb/sGb/sSelectable Selectable --3dB BW3dB BW 0.460.46––7.5 MHz7.5 MHz

PeakingPeaking 0.00.0––3.9 dB3.9 dBDivider RatioDivider Ratio 10, 20, 10, 20, ……, 100, 100

VCO VCO ƒƒcentercenter RangeRange 2.92.9––9.8 GHz9.8 GHzTuning RangeTuning Range 45%45%

Silicon AreaSilicon Area 0.056 mm0.056 mm22

Power / Power / SerDesSerDes ChannelChannel 82 82 mWmW @ 10 @ 10 Gb/sGb/s

ConclusionsConclusions•• Presented PLL offers significant versatility to Presented PLL offers significant versatility to

meet variety of meet variety of SerDesSerDes TxTx applicationsapplications•• ResistorlessResistorless dualdual--path loop filter provides areapath loop filter provides area--

efficient & flexible control of PLL dynamicsefficient & flexible control of PLL dynamics•• Phase offsets in multiplePhase offsets in multiple--path loop filters must path loop filters must

be reduced to suppress reference spursbe reduced to suppress reference spurs•• Process considerations are critical for VCO Process considerations are critical for VCO

tuning range optimizationtuning range optimization•• VCO inductor loss & VCO inductor loss & varactorvaractor CC--VV flatness flatness

determine postdetermine post--calibration tuning & jitter calibration tuning & jitter sensitivity sensitivity