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COMP541COMP541

Combinational Logic - 3Combinational Logic - 3

Montek SinghMontek Singh

Jan 21, 2010Jan 21, 2010

TopicsTopics

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Other gates, XOROther gates, XOR X’s – don’t caresX’s – don’t cares

Using encoder as exampleUsing encoder as example

Z’s – floating valuesZ’s – floating values Multiplexers and DecodersMultiplexers and Decoders Quick look at timing and glitchesQuick look at timing and glitches

Other Types of GatesOther Types of Gates

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In practical terms, doesn’t matter for our FPGAIn practical terms, doesn’t matter for our FPGA But does for other technologiesBut does for other technologies

Exclusive ORExclusive OR

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Exclusive ORExclusive OR What lay people mean by What lay people mean by

“or”“or” Symbol is Symbol is

Plus in a circlePlus in a circle

Parity FunctionParity Function

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Recall how parity worksRecall how parity works Ask classAsk class

Write truth table for two input even parityWrite truth table for two input even parity What needs to be generated for parity bit?What needs to be generated for parity bit?

What function of two inputs gives you this?What function of two inputs gives you this?

XOR Gives Odd FunctionXOR Gives Odd Function

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As many inputs as necessaryAs many inputs as necessary How do you get odd parity?How do you get odd parity? Design even parity generator for 3-bit signalDesign even parity generator for 3-bit signal

Perhaps make truth table and K-MapPerhaps make truth table and K-Map Draw with XOR, then sum-of-products w/ NAND gatesDraw with XOR, then sum-of-products w/ NAND gates

How do you design a detector?How do you design a detector? How about a 7-bit ASCII character?How about a 7-bit ASCII character?

OthersOthers

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CMOS Transmission GatesCMOS Transmission Gates

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Act like electronic switchesAct like electronic switches

XOR w/ Transmission Gate XOR w/ Transmission Gate

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Introduction to CircuitsIntroduction to Circuits

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A logic circuit is A logic circuit is composed of:composed of: InputsInputs OutputsOutputs Functional specificationFunctional specification Timing specificationTiming specification

inputs outputsfunctional spec

timing spec

CircuitsCircuits NodesNodes

Inputs: A, B, CInputs: A, B, C Outputs: Y, ZOutputs: Y, Z Internal: n1Internal: n1

Circuit elementsCircuit elements E1, E2, E3E1, E2, E3 Each a circuitEach a circuit

A E1

E2

E3B

C

n1

Y

Z

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Types of Logic CircuitsTypes of Logic Circuits Combinational LogicCombinational Logic

MemorylessMemoryless Outputs determined by Outputs determined by

current values of inputscurrent values of inputs

Sequential LogicSequential Logic Has memoryHas memory Outputs determined by Outputs determined by

previous and current values previous and current values of inputsof inputs

inputs outputsfunctional spec

timing spec

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Rules of Combinational Rules of Combinational CompositionCompositionComposition rules:Composition rules:

Every circuit element is itself combinationalEvery circuit element is itself combinational Every node of the circuit is either designated as an Every node of the circuit is either designated as an

input to the circuit or connects to exactly one output input to the circuit or connects to exactly one output terminal of a circuit elementterminal of a circuit elementno output shortsno output shorts

The circuit contains no cyclic pathsThe circuit contains no cyclic pathsevery path through the circuit visits each circuit node at every path through the circuit visits each circuit node at

most once (latches are made via a cyclic path)most once (latches are made via a cyclic path) Example:Example:

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Aside: Circuit Schematics with Aside: Circuit Schematics with StyleStyle

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Drawing style/conventions: (where possible)Drawing style/conventions: (where possible) Inputs are on the left (or top) side of a schematicInputs are on the left (or top) side of a schematic Outputs are on the right (or bottom) side of a Outputs are on the right (or bottom) side of a

schematicschematic Gates should flow from left to rightGates should flow from left to right Straight wires are better to use than jagged wiresStraight wires are better to use than jagged wires

Circuit Schematic Rules (cont.)Circuit Schematic Rules (cont.)Wire connectionsWire connections

A dot where wires cross indicates a connectionA dot where wires cross indicates a connection Wires crossing without a dot make no connectionWires crossing without a dot make no connection Wires always connect at a T junctionWires always connect at a T junction

wires connectat a T junction

wires connectat a dot

wires crossingwithout a dot do

not connect

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Multiple Output CircuitsMultiple Output Circuits

A0

A1

PRIORITYCiIRCUIT

A2

A3

Y0

Y1

Y2

Y3

0

A1 A0

0 00 11 01 1

0

00

Y3 Y2 Y1 Y0

0000

0011

0100

A3 A2

0 00 00 00 0

0 0 0 1 0 00 10 11 01 10 0

0 10 10 11 0

0 11 01 01 10 00 1

1 01 01 11 1

1 01 11 11 1

0001

1110

0000

0000

1 0 0 01111

0000

0000

0000

1 0 0 01 0 0 0

Output assertedOutput asserted

corresponding corresponding toto

most significantmost significant

TRUE inputTRUE input

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Priority Encoder HardwarePriority Encoder Hardware

A1 A0

0 00 11 01 1

0000

Y3 Y2 Y1 Y0

0000

0011

0100

A3 A2

0 00 00 00 0

0 0 0 1 0 00 10 11 01 10 0

0 10 10 11 0

0 11 01 01 10 00 1

1 01 01 11 1

1 01 11 11 1

0001

1110

0000

0000

1 0 0 01111

0000

0000

0000

1 0 0 01 0 0 0

A3A2A1A0Y3

Y2

Y1

Y0

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Don’t Cares (X)Don’t Cares (X)

A1 A0

0 00 11 01 1

0000

Y3 Y2 Y1 Y0

0000

0011

0100

A3 A2

0 00 00 00 0

0 0 0 1 0 00 10 11 01 10 0

0 10 10 11 0

0 11 01 01 10 00 1

1 01 01 11 1

1 01 11 11 1

0001

1110

0000

0000

1 0 0 01111

0000

0000

0000

1 0 0 01 0 0 0

A1 A0

0 00 11 XX X

0000

Y3 Y2 Y1 Y0

0001

0010

0100

A3 A2

0 00 00 00 1

X X 1 0 0 01 X

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Meanings of XMeanings of X

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Don’t careDon’t care Contention (illegal input value)Contention (illegal input value) Uninitialized valueUninitialized value

In a simulatorIn a simulator

Floating: ZFloating: Z Floating, high impedance, open, high ZFloating, high impedance, open, high Z

Floating output might be 0, 1, or somewhere in Floating output might be 0, 1, or somewhere in betweenbetween

A voltmeter won’t indicate whether a node is floatingA voltmeter won’t indicate whether a node is floating Allows connecting outputsAllows connecting outputs

E A Y0 0 Z0 1 Z1 0 01 1 1

A

E

Y

Tristate Buffer

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Combinational Building BlocksCombinational Building Blocks MultiplexersMultiplexers DecodersDecoders EncodersEncoders

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Multiplexer (Mux)Multiplexer (Mux)

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Selects between one of Selects between one of N inputs to connect to N inputs to connect to the output.the output.

loglog22N-bit select input – N-bit select input – control inputcontrol input

Example: 2:1 MuxExample: 2:1 MuxY

0 00 11 01 1

0101

0000

0 00 11 01 1

1111

0011

0

1

S

D0Y

D1

D1 D0S Y01 D1

D0

S

Multiplexer ImplementationsMultiplexer Implementations Logic gatesLogic gates

Sum-of-products formSum-of-products form

TristatesTristates For an N-input mux, For an N-input mux,

use N tristatesuse N tristates Turn on exactly one to Turn on exactly one to

select the appropriate select the appropriate inputinput

Y

D0

S

D1

D1

Y

D0

S

Y = D0S + D1S

Multiplexer with Hi-ZMultiplexer with Hi-Z

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Normal operation is blue areaNormal operation is blue area

Smoke

Logic using MultiplexersLogic using Multiplexers Using the mux as a Using the mux as a

lookup tablelookup table A B Y0 0 00 1 01 0 01 1 1

Y = AB

00

Y0110

11

A B

Verilog for MultiplexerVerilog for Multiplexer

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Just a conditional statement. For example,Just a conditional statement. For example,

module mux2(input [3:0] d0, d1, module mux2(input [3:0] d0, d1,

input s,input s,

output [3:0] y);output [3:0] y);

assign y = s ? d1 : d0; assign y = s ? d1 : d0;

endmoduleendmodule

DecodersDecoders N inputs, 2N inputs, 2NN outputs outputs ““One-hot” outputsOne-hot” outputs

only one output HIGH at only one output HIGH at any timeany time

2:4Decoder

A1

A0

Y3Y2Y1Y000

011011

0 00 11 01 1

0001

Y3 Y2 Y1 Y0A0A1

0010

0100

1000

Decoder ImplementationDecoder Implementation

Y3

Y2

Y1

Y0

A0A1

Aside: EnableAside: Enable Enable is a common input to logic functionsEnable is a common input to logic functions See it in memories and today’s logic blocksSee it in memories and today’s logic blocks

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2-to-4 Decoder with Enable2-to-4 Decoder with Enable

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VerilogVerilog

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DecodersDecoders How about a…How about a…

1-to-2 decoder?1-to-2 decoder? 3-to-8 decoder?3-to-8 decoder? (N+1)-to-2(N+1)-to-2(N+1)(N+1) decoder? decoder?

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3-to-8 Decoder: Truth Table3-to-8 Decoder: Truth Table

Notice they are mintermsNotice they are minterms

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3-to-8 Decoder: Schematic3-to-8 Decoder: Schematic

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3-to-8 Decoder: Multilevel Circuit3-to-8 Decoder: Multilevel Circuit

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3-to-8 Decoder: 3-to-8 Decoder: Enable used for Enable used for expansionexpansion

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Multi-Level 6-to-64 DecoderMulti-Level 6-to-64 Decoder

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Uses for DecodersUses for Decoders Binary number might serve to select some Binary number might serve to select some

operationoperation CPU op codes are encodedCPU op codes are encoded

Decoder lines might select add, or subtract, or Decoder lines might select add, or subtract, or multiply, etc.multiply, etc.

Memory address linesMemory address lines

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Logic using DecodersLogic using Decoders OR the ON-set OR the ON-set

mintermsminterms2:4

Decoder

AB

00011011

Y = AB + AB

Y

ABABABAB

Minterm

= A B

DemultiplexerDemultiplexer Takes one inputTakes one input Out to one of 2Out to one of 2nn possible outputs possible outputs

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Demux is a DecoderDemux is a Decoder With an enableWith an enable

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EncoderEncoder Encoder is the opposite of decoderEncoder is the opposite of decoder 22nn inputs (or fewer) inputs (or fewer) n outputsn outputs

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Truth TableTruth Table

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Inputs are MintermsInputs are Minterms Can OR them together appropriatelyCan OR them together appropriately AA00 = D = D11 + D + D33 + D + D55 + D + D77

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What’s the Problem?What’s the Problem? What if D3 and D6 both high?What if D3 and D6 both high? Simple OR circuit will set A to 7Simple OR circuit will set A to 7

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Priority EncoderPriority Encoder Chooses one with highest priorityChooses one with highest priority

Largest number, usuallyLargest number, usually

Note “don’t cares”Note “don’t cares”

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What if all inputs are zero?

Need Another OutputNeed Another Output A “Valid” outputA “Valid” output

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Valid is OR of inputsValid is OR of inputs

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Code Converters Code Converters One code to anotherOne code to another Book puts seven-segment decoder in this Book puts seven-segment decoder in this

categorycategory Typically multiple outputsTypically multiple outputs

Each output has function or truth tableEach output has function or truth table

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Seven-Segment DecoderSeven-Segment Decoder LAST Friday’s lab: Verilog of hex to LEDsLAST Friday’s lab: Verilog of hex to LEDs

Extended version of book exampleExtended version of book example

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TimingTiming What is Delay?What is Delay?

Time from input change to Time from input change to output changeoutput changeTransient responseTransient response

e.g., rising edge to rising e.g., rising edge to rising edgeedge

Usually measured from 50% Usually measured from 50% pointpoint A

Y

Time

delay

A Y

DelaysDelays Transport delay = “pure” delayTransport delay = “pure” delay

Output after a specified timeOutput after a specified time

Inertial delayInertial delay No effect if input occurs for time that is too short No effect if input occurs for time that is too short

(can’t overcome inertia)(can’t overcome inertia)can filter out glitchescan filter out glitches

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Effect of Transport Delay (blue)Effect of Transport Delay (blue) Delay just shifts signal in timeDelay just shifts signal in time

focus on the blue bars; ignore the black onesfocus on the blue bars; ignore the black ones

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Effect of Inertial DelayEffect of Inertial Delay

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Blue – Propagation delay time Black – Rejection timeBlue – Propagation delay time Black – Rejection time

Propagation & Contamination Propagation & Contamination DelayDelay Propagation delay: Propagation delay: ttpdpd

maxmax delay from input to delay from input to outputoutput

Contamination delay: Contamination delay: ttcdcdminmin delay from input to delay from input to

outputoutput

A

Y

Time

A Y

tpd

tcd

Propagation & Contamination Propagation & Contamination DelayDelay Delay is caused byDelay is caused by

Capacitance and resistance in a circuitCapacitance and resistance in a circuitMore gates More gates driven,driven, longer delay longer delayLonger wires at output, longer delayLonger wires at output, longer delay

Speed of light is the ultimate limitationSpeed of light is the ultimate limitation

Reasons why Reasons why ttpdpd and and ttcdcd may be vary: may be vary: Different rising and falling delaysDifferent rising and falling delays

What is typically reported? Greater of the twoWhat is typically reported? Greater of the two Multiple inputs and outputs, some faster than othersMultiple inputs and outputs, some faster than others Circuits slow down when hot and speed up when coldCircuits slow down when hot and speed up when cold

So, both maximum and typical given So, both maximum and typical given

Specs provided in data sheetsSpecs provided in data sheets

Propagation & Contamination Propagation & Contamination DelayDelay

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Critical (Long) Path: tpd = 2tpd_AND + tpd_OR

Short Path: tcd = tcd_AND

Critical and Short PathsCritical and Short Paths

AB

C

D Y

Critical Path

Short Path

n1

n2

Critical (Long) and Short Paths

GlitchesGlitches What is a Glitch?What is a Glitch?

a non-monotonic change in a signala non-monotonic change in a signal e.g., a single input change can cause multiple e.g., a single input change can cause multiple

changes on the same outputchanges on the same output a multi-input transition can also cause glitchesa multi-input transition can also cause glitches

Are glitches a problem?Are glitches a problem? Not really in synchronous designNot really in synchronous design

Clock time period must be long enough for all glitches to Clock time period must be long enough for all glitches to subsidesubside

Yes, in asynchronous designYes, in asynchronous designAbsence of clock means there should ideally be no Absence of clock means there should ideally be no

spurious signal transitions, esp. in control signalsspurious signal transitions, esp. in control signals It is important to recognize a glitch when you see one It is important to recognize a glitch when you see one

in simulations or on an oscilloscopein simulations or on an oscilloscope Often cannot get rid of all glitchesOften cannot get rid of all glitches

Glitch ExampleGlitch Example What happens when:What happens when:

A = 0, C = 1, andA = 0, C = 1, and B goes from 1 to 0?B goes from 1 to 0?

Logically, nothingLogically, nothing Because although 2nd Because although 2nd

term goes to falseterm goes to false 1st term now is true1st term now is true

But, output may glitchBut, output may glitch if one input to OR goes if one input to OR goes

low before the other input low before the other input goes highgoes high

AB

C

Y

Y = AB + BC

Glitch Example (cont.)Glitch Example (cont.)

A = 0B = 1 0

C = 1

Y = 1 0 1

Short Path

Critical Path

B

Y

Time

1 0

0 1

glitch

n1

n2

n2

n1

Fixing the GlitchFixing the Glitch Add redundant logic Add redundant logic

termterm

Y = AB + BC + AC

B = 1 0Y = 1

A = 0

C = 1

NextNext Hierarchical DesignHierarchical Design

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