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Home > Documents > 1 EEL 4783: HDL in Digital System Design Lecture 6: Verilog Examples Prof. Mingjie Lin.

1 EEL 4783: HDL in Digital System Design Lecture 6: Verilog Examples Prof. Mingjie Lin.

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1 EEL 4783: HDL in Digital System Design Lecture 6: Verilog Examples Prof. Mingjie Lin

Transcript

Page 1: 1 EEL 4783: HDL in Digital System Design Lecture 6: Verilog Examples Prof. Mingjie Lin.

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EEL 4783: HDL in Digital System Design

Lecture 6: Verilog Examples

Prof. Mingjie Lin

Page 2: 1 EEL 4783: HDL in Digital System Design Lecture 6: Verilog Examples Prof. Mingjie Lin.

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Shift Register

Page 3: 1 EEL 4783: HDL in Digital System Design Lecture 6: Verilog Examples Prof. Mingjie Lin.

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SR with Parallel Loads

Page 4: 1 EEL 4783: HDL in Digital System Design Lecture 6: Verilog Examples Prof. Mingjie Lin.

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Barrel SR ------------

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Barrel SR

Page 6: 1 EEL 4783: HDL in Digital System Design Lecture 6: Verilog Examples Prof. Mingjie Lin.

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Universal RF

Page 7: 1 EEL 4783: HDL in Digital System Design Lecture 6: Verilog Examples Prof. Mingjie Lin.

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Bi-Directional Bus

Page 8: 1 EEL 4783: HDL in Digital System Design Lecture 6: Verilog Examples Prof. Mingjie Lin.

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Bi-Directional Bus

Page 9: 1 EEL 4783: HDL in Digital System Design Lecture 6: Verilog Examples Prof. Mingjie Lin.

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When a FF is created?

Page 10: 1 EEL 4783: HDL in Digital System Design Lecture 6: Verilog Examples Prof. Mingjie Lin.

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Sync. Data Swapping

Page 11: 1 EEL 4783: HDL in Digital System Design Lecture 6: Verilog Examples Prof. Mingjie Lin.

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Sync. Data Swapping

Page 12: 1 EEL 4783: HDL in Digital System Design Lecture 6: Verilog Examples Prof. Mingjie Lin.

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Sync. Data Swapping

Page 13: 1 EEL 4783: HDL in Digital System Design Lecture 6: Verilog Examples Prof. Mingjie Lin.

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S

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S

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S

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S

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S

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Final issues

• Please fill out the student info sheet before leaving

• Come by my office hours (right after class)

• Any questions or concerns?

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