1 Operating Systems for Reconfigurable Computing Systems Xuequn(Robin) Li Instructor: Prof. Shawki...

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Operating Systems for Operating Systems for Reconfigurable Computing Reconfigurable Computing

Systems Systems

Xuequn(Robin) LiXuequn(Robin) Li

Instructor: Prof. Shawki AreibiInstructor: Prof. Shawki Areibi

School of EngineeringSchool of Engineering

University of GuelphUniversity of Guelph

Mar 30, 2004Mar 30, 2004

22Operating Systems for Reconfigurable Computing SystemsOperating Systems for Reconfigurable Computing SystemsPresented by Robin (Xuequn) LiPresented by Robin (Xuequn) Li

OutlineOutline

IntroductionIntroductionTasksTasks– AllocationAllocation– PartitioningPartitioning– PlacementPlacement– RoutingRouting

Case StudyCase Study– Design ConceptsDesign Concepts– Implementation ConceptsImplementation Concepts

SummarySummaryReferencesReferences


IntroductionIntroductionReconfigurable Computing SystemReconfigurable Computing System– Tradeoff between ASIC (Performance)Tradeoff between ASIC (Performance)

and General Processor (Flexibility)and General Processor (Flexibility)– Logic (FPGA)Logic (FPGA)– Embedded ControlEmbedded Control– Computer based RCComputer based RC

Traditional OSTraditional OS– Device managementDevice management– Process & resource managementProcess & resource management– Memory managementMemory management– File managementFile management


OS for RCSOS for RCS

With the development of the reconfigurable With the development of the reconfigurable computing systems, designers are looking computing systems, designers are looking towards multitasking reconfigurable computerstowards multitasking reconfigurable computersMultitasking an FPGA will require an OS to Multitasking an FPGA will require an OS to manage the loading, swapping and allocation of manage the loading, swapping and allocation of the tasks to the FPGA surfacethe tasks to the FPGA surfaceAs the status of the FPGA changes in time, the As the status of the FPGA changes in time, the designs will have to be completed at run-time, designs will have to be completed at run-time, and not statically compiled.and not statically compiled.The partitioning, placement and routing need be The partitioning, placement and routing need be handled by the OS.handled by the OS.


HistoryHistory

1996, G. Brebner first presented the 1996, G. Brebner first presented the description of hardware multitaskingdescription of hardware multitasking

1999, Wigley discussed the services of OS 1999, Wigley discussed the services of OS for RCS, including devices partitioning, for RCS, including devices partitioning, placement and routingplacement and routing

2003,Herbert Walder proposed a 2003,Herbert Walder proposed a Reconfigurable Hardware OS prototypeReconfigurable Hardware OS prototype

…………


BenefitsBenefits

Speed up development cyclesSpeed up development cycles– Re-use tested and reliable codes and circuitsRe-use tested and reliable codes and circuits

Increase portabilityIncrease portability– Recompilation/resynthesisRecompilation/resynthesis

Ease system re-partitioningEase system re-partitioning– Between different HW components or even Between different HW components or even

between HW and SW componentsbetween HW and SW components

Simplify debugging Simplify debugging – Monitor and trigger facilitiesMonitor and trigger facilities


Tasks of OS for RCSTasks of OS for RCS

General TasksGeneral Tasks– LoaderLoader– SchedulerScheduler– Memory managementMemory management– Circuit protectionCircuit protection– I/OI/O– Inter-process communicationInter-process communication

Special TasksSpecial Tasks– AllocationAllocation– PartitioningPartitioning– PlacementPlacement– Routing multiple circuits on one or more FPGARouting multiple circuits on one or more FPGA


Scheduling AlgorithmsScheduling Algorithms

First-in-first-served algorithmsFirst-in-first-served algorithms– simple but not efficientsimple but not efficient

Genetic algorithms: Reduce the time delay Genetic algorithms: Reduce the time delay in serving large number of tasksin serving large number of tasks– Belong to the class of stochastic search Belong to the class of stochastic search

methodsmethods– Other than operate on a single solution to the Other than operate on a single solution to the

problem at hand, genetic algorithms operate problem at hand, genetic algorithms operate on a population of solutionson a population of solutions


Allocation in OS for RCSAllocation in OS for RCS

Take the next application from the loader Take the next application from the loader to be executed on the real surface and to be executed on the real surface and given minimum area requirementgiven minimum area requirement

Search the logic frame free list for an area Search the logic frame free list for an area contiguous set of frames which meet the contiguous set of frames which meet the area requirementarea requirement

Determine where or if the free logic is Determine where or if the free logic is available for the applicationavailable for the application


Allocation AlgorithmsAllocation Algorithms

Compare the free space on the real FPGA Compare the free space on the real FPGA surface with the total required areasurface with the total required area– If not enough, partition the application, with parts If not enough, partition the application, with parts

executing, and the others being held elsewhere executing, and the others being held elsewhere on the real surface or on the virtual surfaceon the real surface or on the virtual surface

Determine of there is an available free frame Determine of there is an available free frame on the real FPGA surfaceon the real FPGA surfaceOnce the frame has been found, the space Once the frame has been found, the space will be marked; otherwise, OS will invoke the will be marked; otherwise, OS will invoke the partitioning algorithmspartitioning algorithms


Partitioning in OS for RCSPartitioning in OS for RCS

The process in which a large circuit is The process in which a large circuit is broken into smaller ones to fit onto broken into smaller ones to fit onto available space on the FPGA available space on the FPGA – Increase the performanceIncrease the performance– Minimize communication between Minimize communication between

partitionspartitions


Partitioning in OS for RCS Partitioning in OS for RCS (contd)(contd)

Identify a rearrangement of the running Identify a rearrangement of the running task on the FPGA that free sufficient logic task on the FPGA that free sufficient logic for the waiting taskfor the waiting task Use a scheduler mechanism to minimize Use a scheduler mechanism to minimize the delay in the execution time of the the delay in the execution time of the chosen taskschosen tasks The deterministic and bounded run time is The deterministic and bounded run time is important to avoid unpredictable time important to avoid unpredictable time which would reduce the ability of OSwhich would reduce the ability of OS


Partitioning AlgorithmsPartitioning Algorithms

Calculate the As Soon As Possible Calculate the As Soon As Possible (ASAP) execution levels of each node(ASAP) execution levels of each nodeUse these levels to allocate the nodes to Use these levels to allocate the nodes to the desired partition until the partition the desired partition until the partition reaches the user selected capacityreaches the user selected capacityInvoke the placement algorithm and if the Invoke the placement algorithm and if the placement fails, the OS reduces the user placement fails, the OS reduces the user selected capacity and attempts to re-selected capacity and attempts to re-partition and re-place the application.partition and re-place the application.


Placement in OS for RCSPlacement in OS for RCSDetermining where modules of the application Determining where modules of the application partitions are located in logic partitionspartitions are located in logic partitions

Minimizing the area, routing delays and run timeMinimizing the area, routing delays and run time

After successful complete placement, the router will After successful complete placement, the router will be invoked by OSbe invoked by OS

5

4

32

6

1


Placement AlgorithmsPlacement Algorithms

Objective: Placing the connecting logic Objective: Placing the connecting logic modules close to each othermodules close to each otherPlace the first node to the right of the Place the first node to the right of the parentparentPlace the second mode on top of the Place the second mode on top of the parentparentRepeat until all modules have been Repeat until all modules have been placed; otherwise, re-allocate or reduce placed; otherwise, re-allocate or reduce the number of logic modulesthe number of logic modules


Routing in OS for RCSRouting in OS for RCSCreate an electrical connection between two Create an electrical connection between two logic modules by setting the appropriate logic modules by setting the appropriate routing switchesrouting switches

Routing must haveRouting must have

a predicable timea predicable time

All logic modulesAll logic modules

have been have been

internallyinternally

placed and routedplaced and routed


Routing AlgorithmsRouting Algorithms

Modeled on a simple rule-based routerModeled on a simple rule-based router

Route all nearest neighbour connectionsRoute all nearest neighbour connections

Handle those routes that are not nearest Handle those routes that are not nearest neighbourneighbour

Create a list for the detail of each route, so OS Create a list for the detail of each route, so OS can easily rip up the fail routes or removed can easily rip up the fail routes or removed routesroutes

If routing fails, OS restart to invoke allocation If routing fails, OS restart to invoke allocation algorithm with different specificationsalgorithm with different specifications


Case StudyCase StudyAn OS for RCS PrototypeAn OS for RCS Prototype

Design concepts that define basic Design concepts that define basic abstractions & operating system servicesabstractions & operating system services

Implement concepts on Xilinx technology, Implement concepts on Xilinx technology, including a multitasking environment, including a multitasking environment, memory management unit, and device memory management unit, and device drivers & triggers to connect external I/Odrivers & triggers to connect external I/O


Design Concepts Design Concepts

Reconfigurable Reconfigurable Surface PartitioningSurface Partitioning– OS frameOS frame– User areaUser area

Hardware TasksHardware Tasks

OS modulesOS modules– Host CPUHost CPU– FPGAFPGA


OS for RCS BenchmarkOS for RCS Benchmark

A set of benchmark applications to evaluate OS A set of benchmark applications to evaluate OS for RCSfor RCS

Not available right now, but should include these Not available right now, but should include these quality metricsquality metrics– Area overheadsArea overheads– Runtime overheadsRuntime overheads– FragmentationFragmentation

External fragmentationExternal fragmentation

Internal fragmentationInternal fragmentation


Implementation ConceptsImplementation ConceptsTarget technology and PlatformTarget technology and Platform– XESS XSV-800 as platformXESS XSV-800 as platform– A Virtex XCV-800 SRAM-based FPGAA Virtex XCV-800 SRAM-based FPGA– A set of I/O devices: Ethernet, RS232,display elements, DAC etc.A set of I/O devices: Ethernet, RS232,display elements, DAC etc.

FPGA Surface PartitioningFPGA Surface Partitioning– OS –frameOS –frame– Task slotsTask slots

Task SlotsTask SlotsPlaceholders for HW tasksPlaceholders for HW tasks– WidthWidth– STI (Standard task interface)STI (Standard task interface)– IFCC (Inter-frame communication channels)IFCC (Inter-frame communication channels)


XESS Prototyping BoardXESS Prototyping Board


ExampleExample

Function: Function: – Generate an artificial audio signalGenerate an artificial audio signal– Display light patterns on LED barDisplay light patterns on LED bar– Receive UDP (User Datagram Protocol ) Receive UDP (User Datagram Protocol )

packets via the Ethernet interface and forward packets via the Ethernet interface and forward to RS232 interface or the audio codecto RS232 interface or the audio codec

– Reply to incoming ARP (Address Resolution Reply to incoming ARP (Address Resolution Protocol) and ICMP (Internet Control Protocol) and ICMP (Internet Control Message Protocol) echo requestsMessage Protocol) echo requests


SummarySummary

New technologyNew technology

Future worksFuture works– Larger FPGAsLarger FPGAs– Improved algorithmsImproved algorithms– More practicableMore practicable

Thanks !Thanks !


ReferencesReferences

[1] Operating System----A modern Perspective [1] Operating System----A modern Perspective

By Gary Nutt By Gary Nutt

[2] The Development of an Operating System for Reconfigurable computing[2] The Development of an Operating System for Reconfigurable computing

By Grant Wigley, David KearneyBy Grant Wigley, David Kearney Univ. of South Australia Univ. of South Australia

[3] Reconfigurable Hardware Operating Systems: From Design Concepts to [3] Reconfigurable Hardware Operating Systems: From Design Concepts to RealizationsRealizations

By Herbert Walder and Macor Platzner Swiss Federal Institute of TechnologyBy Herbert Walder and Macor Platzner Swiss Federal Institute of Technology

[4] Reconfigurable Hardware OS Prototype[4] Reconfigurable Hardware OS Prototype

By Herbert Walder and Macor Platzner Swiss Federal Institute of TechnologyBy Herbert Walder and Macor Platzner Swiss Federal Institute of Technology


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