Congestion Driven Placement for VLSI Standard

Cell Design

Shawki Areibi and Zhen Yang

School of Engineering, University of Guelph, Ontario, Canada

December 2003

(sareibi@uoguelph.ca, zyang@uoguelph.ca)

ICM 2003, Cairo

Outline

Congestion Optimization

Motivation

Experimental Results

Summary & Conclusions

Background

Introduction

ICM 2003, Cairo

Introduction

• The interconnect has become a critical determiner of circuit performance in the deep sub-micron regime.

• Circuit placement is starting to play an important role in today’s high performance chip designs.

• In addition to wire length optimization, the issue of reducing excessive congestion in local regions such that the router can finish the routing successfully is becoming another important problem.

ICM 2003, Cairo

VLSI Design

Physical Design

Partitioning

Routing

Placement

4

Specification

Architectural design

Circuit design

Physical design

Test/Fabrication

Logic design

Layout Styles

Semi Custom

Full Custom

Standard Cell

Cell-Based Array-Based

Macro Cell Gate Array FPGA

Layout Style

5

Standard Cell Layout Style

Feature: Row based layout

Standard cells

Routing channel

Advantages: High productivity More efficient space Well-suited for automated design

Standard cell

Routing Channel

I/O PadsFeedthrough

6

Circuit Layout - Partitioning

8

Partition circuit into several sub-circuits.

Minimize the number of connections between the components.

Make the size of each

Objectives

component within prescribed ranges

Task

Circuit Layout - Placement

2

1

4

3

8

6

5

7

In8

In7

In6In5

In4In3

In2In1

Out1

8

1 5 2

3 6 4

7

In8

In5

In2

In1 In3

In4

In6

In7

Out1

Minimize the total estimated wire length of all the nets.

Minimize the interconnect congestion.

8

Circuit Layout – Global Routing

Minimize the total wire length and critical path delay.

10

Objectives

Circuit Layout

Typical Objectives

Minimize the chip area

Minimize the interconnect

delay

L

D W

H

OR

L

E

T

O

LH OLE

W LO R D

Determine the location of modules. Connect the modules inside the boundary of a VLSI chip.

10

Why Is Placement Important?

The first phase in the VLSI design that determines the physical layout of a chip.

- The quality of the attainable routing is highly determined by the placement.

11

- Circuit Placement becomes very critical in today’s high performance VLSI design.

The circuit delay, power dissipation and area are dominated by the interconnections.

1.0um 0.5um 0.25um

1.0

0.1

Minimum Feature Size

Dela

y

(ns0

Gate delay

Interconnect delay

Placement Techniques

Placement Algorithms

Constructive Placement

Iterative Improvemen

t

Partitioning Placement

NumericalOptimizatio

n

ClusterGrowth

Technique

SimulatedAnnealin

g

Force-directed

Placement

Genetic Placement

12

Traditional Placement Approach

Initial (global) Placement

by Constructive Algorithms

Initial (global) Placement

by Constructive Algorithms

Improve (detailed) Placement

by Iterative Algorithms

Improve (detailed) Placement

by Iterative Algorithms

Valid Coordinates for each cell

Produce a good initial placement in reasonable time

Produce a good final placement

Circuit Generated

From Logical Description

13

Multi-Level Clustering1. Bottom-up procedure (clustering)2. Top-down procedure (de-clustering)

initial placement iterative improvement

a simple interchange heuristic

a high quality solution

de-cluster

clusters formedfrom cells in

previous level

cluster de-cluster

cluster

Level n

Level 1

Level 0

(Flat)

.

.

.

.

14

Traditional Methods: Drawbacks

• May lead to routing detours around the

regions ( i.e. larger routed wire length).

• May create an unroutable placement( i.e

leads to replacement and repartitioning).

• Congestion reduction in placement stage

would be

more effective.

ICM 2003, Cairo

Congestion

ICM 2003, Cairo

Global Bin Global Bin Edge

Routing demand = 3Assume routing supply is 1,overflow = 3 - 1 = 2 .

Overflow on each edge = Routing Demand - Routing Supply0 (otherwise)

Total Overflow = overflowall edges

Congestion Reduction Techniques

CongestionReduction

IntegratedTechnique

Post-processing Technique

Partitioning Based Placement

SimulatedAnnealing

QuadraticPlacment

Congestion

Reduction During

Placment

ICM 2003, Cairo

Congestion Optimization

ICM 2003, Cairo

Initial Placement

Congestion Reduction

Iterative Improvement

Valid Coordinates for each cell

Module Description& Netlist

Routing Estimation

Congested RegionExpanding

Congested RegionIdentification

Congestion Reduction

Routing Estimation Bounding Box Routing Estimation.

bin(0,0)

bin(0,2)

bin(2,0)

Net K Total Horizontal Routing Demand of net K :2

For each yellow bin, the Horizontal Routing Demand of net K is:1/3

Based on the probability of having a wire within a global bin covered by the bounding box of net K:

ICM 2003, Cairo

Congestion Cost Function

Cost = Routing Demand +( Overflow)2

Wire length Overflow

Horizontal Routing Demand: 2Vertical Routing Demand: 2

Total Bounding Box Based Wire length: 4

ICM 2003, Cairo

Identifying Congested Regions• A global bin is congested if one of its four global

edges is congested.• A maximum number of congested bins in one

congested region is set to prevent forming too large congested regions.

ICM 2003, Cairo

Bin(i,j)Neighborhoodbins Congested

Reg_3

Congested Reg_1

Congested Reg_2

Congested Region Expansion

• For a single congested region, the larger the expansion area is, the better the optimization result can be obtained.

• However, the expansions of multiple congested regions may lead to new congested regions.

ICM 2003, Cairo

Original Congested Region

ExpansionArea

Test Circuits

Circuit cells Pads Nets Pins Rows

Fract 125 24 147 876 6

Prim1 752 81 904 5526 16

Struct 1888 64 1920 5471 21

Ind1 2271 814 2478 8513 16

Prim2 2907 107 3029 18407 28

Bio 6417 97 5742 26947 46

Ind2 12142 495 13419 125555 72

Avq.s 21854 64 22124 82601 80

Avq.l 25114 64 25384 82751 86

Large

Small

Medium

ICM 2003, Cairo

Experimental Results

ICM 2003, Cairo

Test Circuit Statistics (for flat approach)

Circuit cells Nets Grids #c/bin V/H Cap

Fract 125 147 6x9 2.3 6/6

Prim1 752 904 16x21 2.2 11/10

Struct 1888 1920 21x32 2.8 8/7

Ind1 2271 2478 15x54 2.8 19/7

Prim2 2907 3029 28x49 2.1 16/13

Bio 6417 5742 46x60 2.3 11/10

Ind2 12142 13419 72x76 2.2 17/20

Ind3 15059 21940 54x111 2.5 27/20

Avq.s 21854 22124 80x114 2.4 12/10

Avq.l 25114 25384 86x120 2.2 12/10

Congestion Reduction (at flat level)

ICM 2003, Cairo

050

100150200250300350400450

Ind1 Prim2 Bio Ind2 Avq.s Avq.l

Congestion Comparison

Without congestoin reduction

With-congestion reduction

0.0E+00

5.0E+06

1.0E+07

1.5E+07

2.0E+07

2.5E+07

Ind1 Prim2 Bio Ind2 Avq.s Avq.l

Wirelength Comparison

Without congestoin reduction

With-congestion reduction

Average Congestion imp: 51%

Average Wire length Increase: 3%

Average CPU Time Increase: 30%

Congestion Reduction (at level-3)

ICM 2003, Cairo

0

500

1000

1500

2000

25003000

3500

4000

Ind1 Prim2 Bio Ind2 Avq.s Avq.l

Congestion Comparison

Without congestoin reduction

With-congestion reduction

0.0E+00

5.0E+06

1.0E+07

1.5E+07

2.0E+07

2.5E+07

Ind1 Prim2 Bio Ind2 Avq.s Avq.l

Wirelength Comparison

Without congestoin reduction

With-congestion reduction

Results Analysis

• Incorporating a post processing technique into the

hierarchical placement may not be an effective way to

reduce the congestion due to the interplay between the

wire length placement algorithm and congestion

reduction technique.

• The wire length minimization should be performed on

clustering levels, while the congestion optimization

should be only turned on at the flat level.

ICM 2003, Cairo

Congestion Reduction (after hierarchy)

ICM 2003, Cairo

0

500

1000

1500

2000

2500

3000

3500

Ind1 Prim2 Bio Ind2 Avq.s Avq.l

Congestion Comparison

Without congestoin reduction

With-congestion reduction

0.0E+00

5.0E+06

1.0E+07

1.5E+07

2.0E+07

2.5E+07

Ind1 Prim2 Bio Ind2 Avq.s Avq.l

Wirelength Comparison

Without congestoin reduction

With-congestion reduction

Average Congestion imp:37%

Average Wire length Increase: 3%

Conclusions and SummaryA post-processing congestion reduction technique is

implemented and incorporated into the flat and hierarchical

placement.

A post-processing technique can reduce the congestion of

flat placement largely by 51% on average with a slight

increase of wire length.

For hierarchical congestion-driven placement, it seems to

be more beneficial to incorporate the congestion reduction

phase at the flat level rather than within the levels of

hierarchy.

The congestion improvement achieved by performing

congestion optimization at the flat level is 37% on average.

ICM 2003, Cairo

Congestion Driven Placement

D

E F G H

ACB

A

E F G H

DCB

(channel capacities:2)Unroutable Layout

Shorter Wire lengthChannel Density: 3(track: 3)

Longer Wire lengthChannel Density: 2(track: 2)

ICM 2003, Cairo