1

PCBA Reliability

Using

Defects Per Million Opportunities To drive

World Class Printed Circuit Board AssemblyReliability

Jim GreenBill Werner

2

Program Objectives

• Improve PCBA field reliability

• Stop the endless arguments with the CEM

• Lower the cost of production

3

Representative SMT line

•The three defect data entry points * prior to ICT contribute to the DPMO number, but if the defects are

repaired they do not show up in the ICT yield.

• Therefore ICT yield is not an adequate measure of process quality.

• Reducing DPMO lowers the amount of rework and thus lowers the cost of manufacture.

• Is the fact that Ag/Mgis DPMOs have been significantly reduced properly reflected in the GDL quotes?

4

Strategy - overview

• Use the design rules of the supplier, period– E.g. footprints, keep-outs, all DFM requirements– Use and re-qualify all of the CEM’s qualified materials:

Solders, Fluxes, epoxies. The CEM will always have stock and are very familiar with the use, handling and processing

• Use DPMO and Escape % as the basic metrics

• Encourage the supplier to evolve their design rules based on line and field defects.

• Develop a real partnership with the factory– Work at peer level to resolve issues prior to escalation,

this creates trust and you will get the real truth and facts, it results in a win, win scenario.

5

Strategy - design

• Use the design rules of the supplier.

• This ensures they own the quality of what they produce.

• The factory representative signs off in the design review.

• In this way we ensure that defects and failures are never design related and that the supplier can not argue with us that they are.

• This has ended the endless arguments we use to have regarding design vs process problems. The factory now owns both.

6

Strategy - metrics

• We define two factory metrics

– Defects per Million Opportunities (DPMO)

• More on this later

– Escape Percentage

• An Escape is a process defect that reaches ICT that should have been fixed earlier in the process.

• A key element to this is that we acknowledge there may be process defects that can not prevented, but they must be detected and fixed prior to ICT.

• We monitor ICT yields, but they are not a formal metric for us since they are not normalized (to board complexity and coverage).

7

Strategy – continuous improvement

• Encourage the supplier to evolve their design rules based on factory defects and field failures.

• We do not take ownership of the design rules, but we work with the supplier to help them improve theirs in a data driven manner. Field failure data is also used in this step.

• Drive regular (e.g. weekly) meetings with the supplier to identify the root cause of factory defects and to ensure corresponding corrective action.

8

Strategy - partnership

• Drive behavior that fosters open, timely, and honest communication.

• If there is a problem we want to know right away so we can work the issues together.

• Trust, not punishment

9

Metrics

10

DPMO – the key metric to PCBA quality

• What is DPMO?– Defects Per Million Opportunities

• What are PCBA opportunities?– # of components + # of solder joints

• What is a defect?– Any component or solder joint on an assembled PCBA

that is not in compliance with IPC-A-610-D Class III Workmanship Standard.

• How is DPMO calculated?– DPMO = (Defects/Opportunities) * 1,000,000

• DPMO is driven by the design (layout) of the board, and the equipment, processes, and personnel used in the assembly.

11

Sigma Vs. DPMO Vs. Cpk Vs. Yield%

Sigma DPMO Cpk  Yield%  COMMENT

6 3  2 99.999 Rarely Achievable With SMT

5.4 48 99.995 WORLD CLASS

5.2 108 99.989 ORCA DPMO 75 Ag & MGIS DPMO ~ 150 

5 233 1.67  99.98 DPMO Much Better Than Industry Standard 

4.8 483 99.95 DPMO Better Than Industry Standard 

4.6 968 99.90 DPMO Industry Average 

4.4 1866 99.81 DPMO Worse Than Industry Standard 

4 6210  1.33 99.4

3 66811 93.3

2 308770 69.1

The comments aboveapply to low volume high

mix complex PCBA assembles

Ag Q4 Avg-108 MGIS Q4 Avg-127

Often Seen In The Industry

12

Why is lower DPMO better?

• For Reliability– Reduces rework (since defects are fixed)

• Every ‘touch’ of a board risks reliability• A heat cycle is very bad

– The ways in which DPMO are lowered not only means fewer defects, but also improves the robustness of the opportunities that were not defects. (see next slide)

– Lower DPMO also implies fewer Escapes.

• For Cost– Less rework means lower cost (for somebody)

13

Latent reliability risk

defect

The design and process improvements that lower DPMO, moves the distribution to the right, increasing the robustness of all opportunities.

Opportunities

Oppurtunity Robustness

Lowering DPMO moves distribution right

defect

Opportunity Robustness

The red area represents actual factory defects, most of which will be found and fixed. The yellow area represents placements and solder joints that are marginally okay but are at risk to fail in the field. By moving the distribution to the right, we not only lower the number of defects, but also lower the number of placements and solder joints that are marginal – thus improving the reliability.

14

Escape Percentage -> E%

• An Escape is a process defect that reaches ICT that should have been fixed earlier in the process.

• A key element to this is that we acknowledge there may be process defects that can not prevented, but they must be detected and fixed prior to ICT.

• E% = # of process defects that arrive at ICT as a percentage of the total number of process defects generated.

• This is normalized and mostly independent of DPMO

• Process defects include missing component, misaligned component, solder bridge, lifted pin… Non-process defects include component out of spec…

15

ICT First Pass Yield vs DPMO & E%

• The relationship between DPMO and ICT First Pass Yield (FPY) depends on many parameters, and in general is a very weak correlation.

• FPY measures the # of boards that pass ICT In the first attempt, without any rework necessary at that machine center. However, there may have been many defects discovered and fixed prior to the ICT test. These defects are included in the DPMO calculation, but do not impact FPY.

• So, a high FPY indicates either a good process, or a not-so-good process that discovers and fixes the defects prior to ICT.

• Also, FPY is not a normalized metric and different boards will have different FPY based on their complexity and coverage.

• Thus, DPMO is a better measure of process quality that FPY.

• Note – some Escapes are not actually found at ICT, but are found later. This makes the correlation between EP and ICT yield non exact. We have not defined another metric to deal with this.

16

Opportunities 5290 3390 1078ICT Coverage 82% 77% 72%Number of opportunities tested 4338 2610 776

C D E

DPMO(ICT) Yield per opportunity Orca Echo Dude10 0.999990 96% 97% 99%20 0.999980 92% 95% 98%30 0.999970 88% 92% 98%40 0.999960 84% 90% 97%50 0.999950 81% 88% 96%60 0.999940 77% 86% 95%70 0.999930 74% 83% 95%80 0.999920 71% 81% 94%90 0.999910 68% 79% 93%

100 0.999900 65% 77% 93%200 0.999800 42% 59% 86%300 0.999700 27% 46% 79%400 0.999600 18% 35% 73%500 0.999500 11% 27% 68%750 0.999250 4% 14% 56%1000 0.999000 1% 7% 46%2000 0.998000 0% 1% 21%

The percents in columns C, D, E are ICT FPY.Yellow is data we can enter

ICT: FPY Vs. DPMO Vs. Opportunities Vs. Test Coverage

17

Results

18

Flextronics GDL Ag & MGIS PCBA DPMO Trend between Jul-04 - Dec-07 V1.0

0

50

100

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250

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550

600

650

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Jul-04

Sep-0

4

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5

Mar-

05

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Jul-05

Sep-0

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05

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6

Mar-

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7

Mar-

07

May-

07

Jul-07

Sep-0

7

Nov-

07

DP

MO

GDL DPMO DPMO GOAL TREND

Move

Back

To L

ine 1

0

Legacy Boards Were Running Over 1000 DPMO Defects Eliminated In 2007 By DPMO Reduction = 228,327

May-04: All PCBAs Were Designed to Valor, Gold Board Profiling, NPI & Prod. Defect Analysis & CARS Issued

Trips To Guad: Build Support, Error Resolution, Lines Audits, Training & Relationship Building

April-06: Weekly Quality Meetings & CARs

Sep-04: Immersion Silver PCB Finish Qualified

Mar-05: Indium Solder Paste Qualified

MA

KO

R

elea

se

SM

UR

F R

elea

se

CLA

RK

Rel

ease

CLA

RK

& M

AK

O

War

ped

Shi

elds

DPMO Goal Start 250

CLA

RK

& S

MU

RF

P

roce

ss D

efec

ts

Buf

falo

GD

L R

elea

se

OR

CA

Rel

ease

No

DP

MO

Spi

ke

EC

HO

Rele

ase

, 1st

200 p

cs, 81 D

PM

O

Move

d to B

uild

ing -

2

Move

d to

Defe

ctiv

e L

ine -

7

2007: Historical High Defect Rate PADS Revised By MGIS Process Engineering

Jim Green & Bill Werner – 02/20/2008

19

DFM

ITEM PART NUMBER PCBA NAME Flextronics

Manufacturability Score

PCBA QTY

PCBA Ops

Tot OpsDefect

QtyDefect Type(s)

(Process)DPMO

1 TRIAG63360-00-CQ Power 100% 124 797 98828 3Solder Excess Lifted

Pin Wrong Comp.30

2 TRM62180-00-CQ LNA 100% 36 467 16812 0 None 0

3 TRM61697-00-CQ Keypad 100% 124 222 27528 10False Fail, (7)

Component Misaligned, (3)

363

4 TRM62170-00-CQ Dude Unique 100% 14 1095 15330 1 Component Hieght 65

5 TRM63370-00-DQ CPU 100% 8 3164 25312 1 Solder Insufficient 40

6 TRM52260-30-NQ KRYPTON 100% 44 1002 44088 7 Shorted Trace, Bridge, Missing, Height, No Boot

159

7 TRM52610-30-CQ Cradle Swipe 100% 150 20 3000 0 None 0

8 TRM52881-30-EQ Cradle Connector 100% 150 71 10650 0 None 0

9 TRM52981-30-MQ Serial Clip 100% 20 238 4760 0 None 0

10 TRM62280-00-AQ LNA 100% 36 322 11592 0 None 0

11 TRM62170-10-BQ Dude 100% 10 747 7470 1 Missing Component 134

PCBA Post Build Reports, Summary Received Dec-2007 - 2008 DPMO & DEFECTSDESCRIPTION

20

MGIS warranty costs vs previous 12 month average revenue

0.0%

0.5%

1.0%

1.5%

2.0%

2.5%

3.0%

Jan-

06

Feb

-06

Mar

-06

Apr

-06

May

-06

Jun-

06

Jul-0

6

Aug

-06

Sep

-06

Oct

-06

Nov

-06

Dec

-06

Jan-

07

Feb

-07

Mar

-07

Apr

-07

May

-07

Jun-

07

Jul-0

7

Aug

-07

Sep

-07

Oct

-07

Nov

-07

Dec

-07

In an $80M business, a reduction in warranty costs from 2% to 1% is a savings of $800,000 per year.

A measurable portion of this is due to improved PCBA reliability.

21

Slide of first run of older board - buffalo

22

ORCA 1st 200 pc Production BuildPost Build Quality Report

FailWorkCenter (All)

Count of DescriptionDescription Total

Component Missing 57Component Misaligned 53Component Wrong 36Component Height 26False Failure 21Solder Bridge to Leads 14Solder Insufficient 12Upside down component 9Out of Spec Component 7Solder Excessive 7Inverted component 6Contamination 6Manufacturing Error 5Component Electrical Failure 3Epoxy Excessive 2Lifted pin 2Wrong Rework 1Solder Cold 1No Wetting Solder 1Material/Component Damaged 1

Boards run 193 Localización incorrecta del cable 1Total defects 237 DPMO 245 Open trace 1Solder joint + components 5008 Program Wrong/Missing 1Total opportunities 966544 Grand Total 273

DPMO ANALYSIS

23

ECHO 1st 200 pc Production BuildPost Build Quality Report

FailWorkCenter (All)

Count of DescriptionDescription Total

Component Missing 21Solder Insufficient 7Component Height 5False Failure 4Solder Bridge 3Comp. Damaged 3Comp. Misaligned 2Comp. Elect. Fail 2Wrong Polarity 2out of Tolerance 1Contamination 1Open trace 1Comp. Tombstone 1Solder Cold 1Solder Excessive 1Grand Total 55

Boards run 200Total defects 55 DPMO 81Solder joint + components 3390Total opportunities 678000

DPMO ANALYSIS

24

0

50

100

150

200

250

300

350

400

450

500

Dec

-06

Jan-

07

Feb

-07

Mar

-07

Apr

-07

May

-07

Jun-

07

Jul-0

7

Aug

-07

Sep

-07

Oct

-07

Nov

-07

Dec

-07

Jan-

08

Feb

-08

DP

MO

Buffalo ORCA ECHO DPMO Goal

Agriculture PCBA DPMO Trend Dec 06 – Dec 07Buffalo - ECHO - ORCA

Buffalo Production Start, 500 DPMO

ORCA Production Start, 250 DPMO

ECHO Production Start, 81 DPMO

End Q3-2007, Process Issues

25

Ag ICT Yield Trend , Actual & Goal, All Boards Combined, 2008-2009

85%86%87%88%89%90%91%92%93%94%

Jan-

08

Feb

-08

Mar

-08

Apr

-08

May

-08

Jun-

08

Jul-0

8

Aug

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Sep

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Jan-

09

Feb

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-09

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9

Aug

-09

Sep

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Oct

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Dec

-09

ICT

Yie

ldActual ICT Yield ICT Yield Goal

Ag Escapes Trend , Actual & Goal, All Boards Combined, 2008-2009

5%

15%

25%

35%

45%

55%

65%

Jan-

08

Feb

-08

Mar

-08

Apr

-08

May

-08

Jun-

08

Jul-0

8

Aug

-08

Sep

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Oct

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Nov

-08

Dec

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Jan-

09

Feb

-09

Mar

-09

Apr

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May

-09

Jun-

09

Jul-0

9

Aug

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Oct

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Nov

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Dec

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Esc

apes

Per

cen

tag

e

Escape Goal Escape %

Ag DPMO Trend , Actual & Goal, All Boards Combined, 2008-2009

50

60

70

80

90

100

110

Jan-

08

Feb

-08

Mar

-08

Apr

-08

May

-08

Jun-

08

Jul-0

8

Aug

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Sep

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Oct

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Nov

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Dec

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Jan-

09

Feb

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Mar

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Apr

-09

May

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Jun-

09

Jul-0

9

Aug

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Sep

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Oct

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Dec

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DP

MO

DPMO Goal Actual DPMO

26

MGIS ICT Yield Trend , Actual & Goal, All Boards Combined, 2008-2009

90%91%92%93%94%95%96%97%

Jan-

08

Feb

-08

Mar

-08

Apr

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May

-08

Jun-

08

Jul-0

8

Aug

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Sep

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09

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Jul-0

9

Aug

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Sep

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Dec

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ICT

Yie

ld

Actual ICT Yield ICT Yield Goal

MGIS Escapes Trend , Actual & Goal, All Boards Combined, 2008-2009

5%15%25%35%45%55%65%75%85%

Jan-

08

Feb

-08

Mar

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Apr

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May

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Jun-

08

Jul-0

8

Aug

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Sep

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Feb

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Aug

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Esc

apes

Per

cen

tag

e

Escape Goal Escape %

MGIS DPMO Trend , Actual & Goal, All Boards Combined, 2008-2009

5060708090

100110120130140

Jan-

08

Feb

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Mar

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Apr

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May

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Jul-0

8

Aug

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Jun-

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9

Aug

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Sep

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DP

MO

DPMO Goal Actual DPMO

27

ORCA, top 16 Defect Pareto Jan-Dec, 2008

0

250

500

750

1000

1250

1500

1750

2000

2250

2500

2750

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3500C

Mis

sin

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isa

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ed

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rid

ge

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lse

Fa

il

S I

nsu

ffic

C W

ron

g

C T

om

bst

on

e

Mfg

. E

rro

r

Pro

g W

rg/M

issg

C E

lect

Fa

il

Da

ma

ge

Ou

t T

ole

ran

ce

Lift

ed

Pin

C P

ola

rity

Ass

y E

rro

r

Process defects

False fails, decrese DPMO and ICT yield

Electrical failures often result from rework and diagnosis

28

All Products, All Defects, All Work Centers, Top 20 Pareto

0

10

20

30

40

50

60

70

Com

p M

isal

igne

d

Mat

/Com

p D

amag

e

Com

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issi

ng

Fal

se F

ailu

re

Sol

der B

ridge

Com

p E

lect

Fai

l

Out

of T

oler

ance

Ass

embl

ing

Pro

g W

rg/M

issi

ng

Man

ufac

turin

g E

rror

Inve

rted

com

pone

nt

Lifte

d pi

n

Sol

der I

nsuf

ficie

nt

Com

pone

nt H

eigh

t

Com

pone

nt W

rong

Uni

ts B

ack

to IC

T

Pad

Loo

se

Sho

rted

trace

Scr

atch

ed

Con

tam

inat

ion

Qu

antit

y

In Process defect, (Escape), 44.8%

In Process & Other Defects, 55.2%

29

Ag, All Products, All Defects, All Work Centers Top 20 Pareto, Nov-2006 - Jan-2007

0

100

200

300

400

500

600

700

800

900C

omp

Hei

ght

Com

p M

isal

igne

d

Com

p M

issi

ng

Sol

der

Insu

ffici

ent

Fal

se F

ailu

re

Com

p E

lect

Fai

l

Wro

ng P

olar

ity

Sol

der

Brid

ge

Sol

der

Col

d

Mat

/Com

p D

amag

e

Ass

embl

ing

Lifte

d pi

n

Out

of S

pec

Com

p

Mfg

Err

or

Pro

g W

rong

/Mis

sing

No

Wet

ting

Sol

der

Com

pone

nt W

rong

Ups

ide

dow

n co

mp

Con

tam

inat

ion

Tea

red

off c

omp

30

Ag, All Products, All Defects, All Work Centers Top 20 Pareto, Jun-2008 - Aug-2008

0

100

200

300

400

500

600

700

800

900

1000C

omp

Mis

sing

Com

p M

isal

igne

d

Fal

se F

ailu

re

Mat

/Com

p D

amag

ed

Com

p E

lect

Fai

l

Sol

der

Brid

ge

Sol

der

Insu

ffici

ent

Pro

g W

rong

/Mis

sing

Mfg

Err

or

Ass

embl

ing

S/N

Wro

ng/M

issi

ng

Com

pone

nt H

eigh

t

Lifte

d pi

n

Com

pone

nt W

rong

Inve

rted

com

pone

nt

Fue

ra d

e to

lera

ncia

Out

of S

pec

Com

p

Con

tam

inat

ion

Pad

Loo

se

Sub

-ass

y de

fect

ive

31

Typical Process Defects & Corrective Actions

Process Defects, Root Causes, Corrective ActionsMissing Components: Feeder Defective Feeder Repair

Plugged Nozzles Replace Nozzles

Dry Solder Paste Replace Paste

Fuji Program Adjust Program

Preventative Maintenance Perform Maintenance

Tombstones: Old SMT Pad Geometry Update Geometry

Solder Print Misalignment Printer Adjustment

Poor SMT Placement Adjust SMT Program

Misaligned Components: Feeder Maintenance Perform Maintenance

Running Placement to Fast Slow Down Placement

Old un-Balanced Pad Design Update geometry

Fuji Vision Part Definition Adjust Fuji (P/Ds)

Solder Insufficient: Poor Printer Set-up Adjust Printer

Old Solder Paste Replace Paste

Plugged Stencil Clean More Often

Stencil Aperture Design Adjust & New Stencil Solder Bridging: Poor Printer Set-up Adjust Printer

Stencil Aperture Design Adjust, New Stencil

Old Pad Geometry Our new designs fix it

32

Ag, All Products, All Work Centers, Defects & Escapes9.

6%

13.4

%

5.9%

11.0

%

3.7%

0.8%

0.2%

37.5

%

6.0%

0.2% 0.9%

0.6%

0.3%

0.2%

0.0%

0.1%

2.5% 4.

3%

2.5%

0.2%

0

200

400

600

800

1000

1200

1400

1600

1800

2000TR

MBO

T To

tal

TRM

TOP

Tota

l

TRM

BOTA

OI

Tota

l

TRM

TOPA

OI

Tota

l

TRM

PTH

Tota

l

TRM

5DX

Tota

l

TRM

AUDI

TQA

Tota

l

TRM

ICT

Tota

l

TRM

BOAR

DTTo

tal

TRM

LEAK

TTo

tal

TRM

TUNN

IGTo

tal

TRM

QA

Tota

l

TRM

PRG

Tot

al

TRM

SKY

Tota

l

TRM

RFLA

SHTo

tal

TRM

VACT

EST

Tota

l

TRM

LCD

Tota

l

TRM

FTES

TTo

tal

TRM

FT T

otal

TRM

FINS

P To

tal

0.0%

5.0%

10.0%

15.0%

20.0%

25.0%

30.0%

35.0%

40.0%

Qty of Process Defects Percentage of Process Defects

Process Defect Escapes = 55.4%Process Defect Repaired = 44.6%

This slide shows that ~ 55.4% of the process defects are not found until ICT or later. This results in lower ICT, Box Test yields and higher costs. All process defects should be found and repaired prior to ICT. Rework of escapes through the process also impacts reliability.

PCBA Assembly Process

Trimble PCBA Test Stations

33

Cost Avoidance

34

Cost Avoidance of DPMO Reduction

• The prime benefit of DPMO reduction is improved field reliability, and this has been significant.

• However, there is a direct cost savings due to the reduction of rework. At the moment, Trimble does not directly benefit from this cost reduction.

• The following slide shows the beginning of an attempt to understand these savings. We know how many defects we have prevented, but we do not yet know how to determine the cost savings. (Probably a function of the # of boards that require rework + the cost to fix a defect at each machine center * defects fixed at that machine center.)

• Current overall averages (Original baseline = 1000)– Mgis 127– Ag 108

35

Ag - Estimated Cost Savings of DPMO ReductionAg - DPMO Worksheet, v1.0

Delta DPMO = 900Total

Opportunites Total 2007 Total DefectsProduct name PCB Name per board Production Opportunities Prevented

Mako PSD 2,152 9,378 20,181,456 18,163Merf 1,247 9,298 11,594,606 10,435

Orca Main 5,264 16,730 88,066,720 79,260Smart Buffalo RF 1,336 4,066 5,432,176 4,889

Digital 1,792 3,947 7,073,024 6,366I/O 322 3,844 1,237,768 1,114

Buffalo in a Box RF 1,476 3,466 5,115,816 4,604Digital 2,755 3,482 9,592,910 8,634

I/O 141 3,842 541,722 488Ceres Main 5,088 6,000 30,528,000 27,475

Total 64,053 179,364,198 161,428

Percentage Cost per Total TotalWork Center of Defects Defect Defects Cost

SMT 100% -$ 161,428 -$ Wave Solder 0% -$ 0 -$

2nd Ops 0% -$ 0 -$ 5DX 0% -$ 0 -$ ICT 0% -$ 0 -$

Clam Shell 0% -$ 0 -$ Box 0% -$ 0 -$

Final QA 0% -$ 0 -$ OOB Audit 0% -$ 0 -$

Total 100% 161,428 -$

36

The End

• Create a strong partnership with you CEM. Visit them and help them make their jobs easy, be responsive

• PCBAs and Boxes must receive a 100% DFM / post build report ‘score card’ from your CEM

• Be data driven, get all shop floor Pass/Fail and defect type and reference location scans, all work centers

• Use DPMO and In-Process Escape% do not use yields in SMT, Pareto defects, correct high hitters

• Hold weekly / monthly Quality Meetings, issue action items weekly on at least one issue

–

37

Addendum

38

DPMO Reduction - Process

• Ensure DFM design rules are published, understood, followed.– It is the suppliers design rules that count – keep loop closed– Valor, Pantheon DRCs, FAB House DFM reports

• Development of DFM starts with 1st proto and continues through NPI. CEM post build report issues are incorporated in next build.

• Measure and publish detailed defect data per board, all production. Daily internet check of WIP defect issues.

• Drive weekly meetings to determine key problems, perform root cause analysis, and drive corrective action. Monthly metric reviews with management.

• From root causes of factory defects and field failures, update design rules as appropriate. Critical element to close the loop.

• Verify all solder profiles with the ‘Gold Board Profiling Process’.

• Work with Supplier Quality on Factory Health. Regular factory visits.

39

A bit more

40

From the Literature on DPMO

• Creates an environment where the manufacturing process is continuously improved

• Enables accurate estimates of PCBA costs early in the product life cycle for quoting new business

• Creates actionable DFM and DFT processes.• …showing that every heat cycle has a negative impact

on the assembly in some manner.• John Lovell informs me that Seimans does not allow

rework on their VDO boards.

41

Reliability

• Reliability is the ability of the board to work properly over time in the field. It is essentially quality over time. Boards that fail in the field negatively impact the company in many ways.– Warranty costs– Customer dissatisfaction– Costs associated with the logistics of repair,

including lost opportunity costs.

• Defect rework costs are those incurred during the production of the board. As defects are detected (e.g. missing part), they must be fixed. The later in the process the defect is found, the higher the rework cost.

42

Reliability Drivers

• There are several drivers of PCBA reliability– Design

• Schematic level issues, including margin• Parts specifications• DfM – using correct design rules

– Process– Parts quality

• Each of these has an impact on reliability. If parts specifications or design margins are inadequate, or the fab is designed or built poorly matched to the assembly process, or if the assembly process is poor. or if out of spec parts are used, the board is more likely to fail.

43

Process

• A poor process will add defects to the assembly, some of which will be detected and some of which will not.

• Those that are not detected will ship to the field and can result in field failures, often during the warranty period.

• Those that are detected will be repaired, which requires extra handling, generally in ways that risk lowering the resulting reliability, and in all cases, adds cost. The later in the process that the defect is found, the greater the cost add-on. Minimizing rework is the goal, soldering rework absolutely reduces reliability.

• Thus, a key element is the reduction of defects during the assembly process. It is not good enough to merely find and fix the defects, they must be prevented from occurring.

44

Guad Data

45

Combined 12 Month DPMO Trend, 2007

MGIS Combined 12 Month DPMO Trend, 2007

0

100

200

300

400

2007

2007

2007

2007

2007

2007

2007

2007

2007

2007

2007

2007

Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec

DP

MO

Clark & Smurf Combined DPMO Trend GOAL

Ag Combined 12 Month DPMO Trend, 2007

0

50

100

150

200

250

300

2007

2007

2007

2007

2007

2007

2007

2007

2007

2007

2007

2007

Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec

DP

MO

ORCA, MAKO, Buffalo Combined DPMO Trend GOAL

MGIS & Ag NPI & Prod. Weekly Quality Meetings & CARs

Buffalo SMT, 1st ORCA-E, Mako Missing Comps

Smurf U3 Program, High Rate Missing Comps.

Moved To Line 7

Guad Support, Training, Audits

Guad Support, Training, Audits

Updated to Dec-2007

46

SLR Guadalajara, MGIS ProductionDefect Paretos By Quarter 2006 - 2007

Defects Pareto, Q3-2007

0

100

200

300

400

500

600

700

Qu

an

tity

Defects Pareto Q1-2007

0

100

200

300

400

500

600

700

Qu

an

tity

Defects Pareto, Q2-2007

0

200

400

600

800

1000

1200

1400

Qu

an

tity

Defects Pareto, Q-4 2006

0

100

200

300

400

500

600

700

Qu

an

tity

I do not have the data to modify these, however

I did figure out a good

Way to talk to them

47

SLR/Flex Guadalajara, ProductionTop (3) DPMO Defect Trends for 2006

DPMO Trend, Tombstone, 2006

020406080

100120140160180

Ja

n

Fe

b

Ma

r

Ap

r

Ma

y

Ju

n

Ju

l

Au

g

Se

p

Oct

No

v

De

c

DPMO Trend, Missing Components, 2006

020406080

100120140

Ja

n

Fe

b

Ma

r

Ap

r

Ma

y

Ju

n

Ju

l

Au

g

Se

p

Oct

No

v

De

c

DPMO Trend, False Failure, 2006

010203040506070

Ja

n

Fe

b

Ma

r

Ap

r

Ma

y

Ju

n

Ju

l

Au

g

Se

p

Oct

No

v

De

c

CAR Issued CAR Issued

CAR Issued

CAR Issued New SMT pad Geometries were released for small

chips

48

ORCA prod. Jan -2008 3523, ICT Fails 542, iCT Yield %84.64, Qty Fails Per Board

2982

404

93 28 11 2 2 2 10

500

1000

1500

2000

2500

3000

3500

0 Fails 1 Fails 2 Fails 3 Fails 4 Failss 5 Fails 6 Fails 7 Fails 8 Fails

PCBAs PCBA TotalBuilt Opps Opps3523 5290 18,636,670

Tot Defects 1305 DPMO

70

49

Flex Guadalajara, Production CARS

30 solder insuficient on J1 on CPU (TRM53370) Board due to solder mask on the pads

Confirm that GDL has the corporate stencil design guideline to modify apertures for best printing: Confirmed By Antonio Lopez

Antonio Lopez 2-Nov Closed

16 False Failures in Clark. Ask Marco which where the reasons of this false failures

C.Ortiz 18-Jan Closed

13High failure rate Tombstone in PSD (Mako) board related to Pad design

Date to implement re-designed PSD TRM49549 board. Jeanne Cienfuegos informed that the new Mako boards will not be implemented until after the Agriculture season Update: Waiting for new PCB design and see effectiveness of the new board, THIS ACTION IS ON HOLD.

Bill Werner 15-Nov Closed

Apply loctite to RX, this action contain the issue. Antonio Lopez 18-Apr ClosedReview reflow oven conditions. An external supplier came to calibrate teh reflow oven

Daniel Medina 2-May Closed

a) SMT engineer found a damaged vacuum hose in line 7, The hose has been changed

Daniel Medina 2-May Close

b) Investigate why the damaged hose was not detected in the preventive manteinance

Daniel Medina 10-May Close

32Control the quantity of Bigon (Printing machine cleaner)

Antonio Lopez 3-May Close

33

Redesign the stencil aperture for U1 to apply less volume of solder paste. This is the same component used in Orca, and we had same issue.The issue was solved with new stencil appertures, using same as Orca Digital on U13.

Antonio Lopez 9-May Close

35 Wrong component Every reel change must be changed one by one Arturo Alcala Jun 21th Close

34Misaligned / Missing components at SMT Line 7

Evaluate by trhid party the status fo the SMT machines.Solectron will perform a retrofit the SMT line 10, and after this mainteinance, move Trimble products to line 10.

Daniel Medina Jun 30th Close

36 Solder Bridge to leads in J4 Modify ORCA I/O pallets (TRIAG66002-00) Antonio Lopez 14-Jun Close

40Solder insuficient on power board (TRM53360) Location U7, U4, U8

Modify stencil appertures on lacation U7, U8, U4. Antonio Lopez 29-Jun Close

Shorts on TRM52260 location U1

31Misligned components on TRM52170-00-B on RX1 & RX2 components.

4 Misaligned / Missing components at SMT Line 7

(Sample of CARs From Our Weekly Quality Meetings with Guad)

Root cause added to STARS

50

ORCA 66001-00-D PCBAs ICT Yield Trend

0

25

50

75

100

125

150

175

200

225

250

275

300

325

350

375

400

425

450

4753/

16/0

7

3/21

/07

3/22

/07

3/23

/07

3/24

/07

3/25

/07

3/26

/07

3/27

/07

3/28

/07

3/29

/07

3/31

/07

4/1/

07

4/2/

07

4/3/

07

4/7/

07

4/8/

07

4/9/

07

4/10

/07

4/11

/07

4/14

/07

4/23

/07

4/24

/07

4/25

/07

5/12

/07

5/13

/07

5/14

/07

5/15

-23/

07

5/23

-30/

07

6/7

to 6

/15

PC

BA

Qua

ntity

/ D

ay T

este

d @

ICT

0.00%5.00%10.00%15.00%20.00%25.00%30.00%35.00%40.00%45.00%50.00%55.00%60.00%65.00%70.00%75.00%80.00%85.00%90.00%95.00%100.00%105.00%

ICT

Yie

ld

TESTED PASSED FAILED YIELD CURRENT GOAL Linear (YIELD)

462 Pcs Tested in ICTsince 5/23, 88.53% Yield !

C/A's - Reduce ICT FF's, Define Cause, Real time feedback from AOI, ICT to SMT

51

MGIS – Estimated cost savings of DPMO reduction

MGIS - Direct Cost savings in 2007 of DPMO reduction

Delta DPMO = 900Total

Opportunites Total 2007 Total DefectsProduct name PCB Name per board Production Opportunities Prevented

Smurf Digital 1,017 1,625 1,652,625 1,487LNA 250 1,625 406,250 366Dude 759 1,625 1,233,375 1,110

Clark CPU 2,718 13,272 36,073,296 32,466Krypton 663 13,140 8,711,820 7,841

LNA 250 13,056 3,264,000 2,938Power 618 13,851 8,559,918 7,704

Barcelona Main 1,038 625 648,750 584

XRS Combined 2315 545 1,261,675 1,136

Total 58,819 60,550,034 54,495

Percentage Cost per Total TotalWork Center of Defects Defect Defects Cost Saved

SMT 100% -$ 54,495 -$ Wave Solder 0% -$ 0 -$

2nd Ops 0% -$ 0 -$ 5DX 0% -$ 0 -$ ICT 0% -$ 0 -$

Clam Shell 0% -$ 0 -$ Box 0% -$ 0 -$

Final QA 0% -$ 0 -$ OOB Audit 0% -$ 0 -$

Total 100% 54,495 -$

52

Where to from here

• Expand training on integration with box mounting