11

Review OfReview Of

““A 125 MHz Burst-Mode Flexible Read While A 125 MHz Burst-Mode Flexible Read While Write 256Mbit 2b/c 1.8V NOR Flash Memory”Write 256Mbit 2b/c 1.8V NOR Flash Memory”

AdoptedAdopted FromFrom::

““ISSCC 2005 / SESSION 2 / NON-VOLATILE ISSCC 2005 / SESSION 2 / NON-VOLATILE MEMORY / 2.5MEMORY / 2.5

by: C. Villa et al”by: C. Villa et al”Class presentation of Advanced VLSI courseClass presentation of Advanced VLSI course

byby

Ashkan JaliliAshkan Jalili

Instructor: Dr. FakhraieInstructor: Dr. Fakhraie

22

outlineoutline

Floating GatesFloating Gates

Conventional sense amplifiersConventional sense amplifiers

Proposed sense amplifierProposed sense amplifier

Programming schemeProgramming scheme

Chip specificationsChip specifications

Summary Summary

33

FLOATING GATEFLOATING GATE

Based on charges stored on Based on charges stored on FG and changing VFG and changing Vth th

Desired values:Desired values:

value = 1 : no charges on FGvalue = 1 : no charges on FG

value = 0 : specific charge on FGvalue = 0 : specific charge on FG

Applying a specific gate Applying a specific gate voltage:voltage:

I > 0 : cell value = 1I > 0 : cell value = 1

I = 0 : cell value = 0 I = 0 : cell value = 0

Source

N+

Floating Gate

Tunnel OxideDrain

N+

SubstrateP-type

Control Gate

44

MULTILEVEL CHARGINGMULTILEVEL CHARGING

Different levels of charging on the FGDifferent levels of charging on the FG Considering the amount of cell current rather than just Considering the amount of cell current rather than just

sensing it’s presence or absencesensing it’s presence or absence Different VDifferent Vth th for a 2bit/cell resulting in 4 levels of for a 2bit/cell resulting in 4 levels of

current showing 4 states i.e 2bits:current showing 4 states i.e 2bits: IIcellcell < I < Iref3ref3 2bits value = 00 ➱ 2bits value = 00 ➱

IIcellcell < I < Iref2ref2 2bits value = 01 ➱ 2bits value = 01 ➱

IIcellcell < I < Iref1ref1 2bits value = 10 ➱ 2bits value = 10 ➱

IIcellcell > I > Iref1ref1 2bits value = 11 ➱ 2bits value = 11 ➱

55

Conventional SenseConventional Sense AmplifiersAmplifiers

Structure of a conventional sense amplifier[3]Structure of a conventional sense amplifier[3]

66

Disadvantage of Conventional amplifiersDisadvantage of Conventional amplifiers

A constant high voltage is applied to all cells (higher than A constant high voltage is applied to all cells (higher than

the largestthe largest VVthth) resulting in wide range of current:) resulting in wide range of current: The circuit should have the ability to work in wide range of current from The circuit should have the ability to work in wide range of current from

a few uA to several tens of uAa few uA to several tens of uA

The current in cells with lower VThe current in cells with lower Vthth is large: is large: Large current increases the effect of parasitic resistanceLarge current increases the effect of parasitic resistance Lager current increases power dissipationLager current increases power dissipation

77

Sense amplifier schemeSense amplifier scheme

Proposed sense amplifier scheme[1]Proposed sense amplifier scheme[1]

+

- +

-

Precharger - I/V converter

ComparatorLatches

Reference sense out

Bit line

Word line

Iref

Vref

R0

Iref < 10µA Iref < 10µA SA switched off as Icell > IrefSA switched off as Icell > Iref

MSB LSB

88

Read scheme of proposed structureRead scheme of proposed structure

Structure of reading concept[1]Structure of reading concept[1]

Out<1:0>

SA SA SA

SA

Ramp gen

Reference Wordline

Array Wordline

Ref sense out<1:3>Iref

Iref

Ref 1

Ref 2

Ref 3

Decode

Latch

99

Design solution: voltage ramp readDesign solution: voltage ramp read

Read ramp, reference and array sense output[1]Read ramp, reference and array sense output[1]

WL reset by ref3 trigger

time

Vgate01 001011

Vtref1 Vtref2 Vtref3

Reference triggers 000 001 011 111

Array cell trigger

Sense output 01

array cell

Word line ramp

Iref

Icell

•SA trigger

1010

Conventional programming SchemeConventional programming Scheme

Conventional programming:Conventional programming:

Applied constant VApplied constant Vg g [4][4]

Constant VConstant Vg g is applied to all is applied to all cell gatescell gates

Amount of desired charge is Amount of desired charge is tuned by the pulse widthtuned by the pulse width

Disadvantage:Disadvantage: The threshold voltage distribution The threshold voltage distribution

of programmed cells can be of programmed cells can be several volts (not suitable for low several volts (not suitable for low voltage operations)voltage operations)

1111

Programming schemeProgramming scheme

AA samplesample threshold voltage distribution diagram [2]threshold voltage distribution diagram [2]

1212

Improved programming scheme Improved programming scheme Introduced in 1995Introduced in 1995

a) Trapezoidal, b) and staircase, a) Trapezoidal, b) and staircase, programming pulses [4]programming pulses [4]

Easier to control VEasier to control Vth th distribution distribution widthwidth

Higher programming speed Higher programming speed can be obtainedcan be obtained

Easier to generate on chipEasier to generate on chip VVth th will increase with every stepwill increase with every step Changes depend on the amount of Changes depend on the amount of

step step

1313

Programming schemeProgramming scheme

Threshold voltage changes for different voltage steps [2]Threshold voltage changes for different voltage steps [2]

1414

Programming schemeProgramming scheme

Staircase voltage is applied to achieve narrow Staircase voltage is applied to achieve narrow distribution widthdistribution width

The gate voltage in programming phase is varied from The gate voltage in programming phase is varied from 1V to 9v with a step size of 75mV1V to 9v with a step size of 75mV

3 phase is used for programming:3 phase is used for programming:1.1. Content of memory is read and compared to the content of write Content of memory is read and compared to the content of write

bufferbuffer

2.2. Programs “10” and “01” cells executing a program/verify loopPrograms “10” and “01” cells executing a program/verify loop

3.3. Programs “00” cells applying a voltage ramp starting from the last Programs “00” cells applying a voltage ramp starting from the last used voltage level in phase 2, no verify is doneused voltage level in phase 2, no verify is done

1515

16Mbit Bank

Inpu

t

Output

Charge PumpsCtrl logic

256 Mbit flash - Die photo [1]256 Mbit flash - Die photo [1]

16 banks of 16 banks of 64Mb64Mb

16 sectors / bank16 sectors / bank 64Kw / sector64Kw / sector

Independent Independent 64+3 sense 64+3 sense amplifiers per amplifiers per bankbank

Die size 55mmDie size 55mm22 in 130nmin 130nm

Sense amps

Ctrl logic

Die photo [1]Die photo [1]

1616

Access time measurement [1]Access time measurement [1]

65 nsAddress input

Data output

Ref 3 sense out

Word line ramp

10 ns/div

Fastest slope conf

(~250mV / ns)

Access time measurement [1]Access time measurement [1]

1717

Key feature table [1]Key feature table [1]

Specifications of the chip [1]

1818

Summary Summary

A new structure for sense amplifiers was proposed in A new structure for sense amplifiers was proposed in order to remove the undesired effects of high currents order to remove the undesired effects of high currents due to high constant voltage applied to transistors in due to high constant voltage applied to transistors in conventional sense amplifiersconventional sense amplifiers

1919

ReferencesReferences

1.1. C. Villa et al., “A 125 MHz Burst-mode Flexible Read-While-Write C. Villa et al., “A 125 MHz Burst-mode Flexible Read-While-Write 256 Mbit 2b/c 1.8V NOR flash memory,” ISSCC 2005256 Mbit 2b/c 1.8V NOR flash memory,” ISSCC 2005

2.2. Tae-Sung Jung et al., “A 117-mm2 3.3-V Only 128-Mb Multilevel Tae-Sung Jung et al., “A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications,” JSSCC 1996NAND Flash Memory for Mass Storage Applications,” JSSCC 1996

3.3. G. Campardo et al., “40-mm2 3V Only 50-MHz 64-Mb 2b/c NOR G. Campardo et al., “40-mm2 3V Only 50-MHz 64-Mb 2b/c NOR Flash Memory’” JSSCC 2000Flash Memory’” JSSCC 2000

4.4. G.J. Hemink et al., “Fast Accurate Programming Method for Multi-G.J. Hemink et al., “Fast Accurate Programming Method for Multi-Level NAND EEPROMs,” Symposium on VLSI Technology Digest of Level NAND EEPROMs,” Symposium on VLSI Technology Digest of Technical papers 1995Technical papers 1995

Thank youThank you

Any question?Any question?