45
VLSI TECHNOLOGY Jitendra S Sengar Asst. Professor VLSI Division, ECE
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VLSI TECHNOLOGY
Jitendra S Sengar
Asst Professor
VLSI Division ECE
COURSE SYLLABUS Unit 1
Crystal growth amp wafer preparation Processing considerations Chemical cleaning getting the thermal Stress factors etc
Epitaxy [T1]
Vapors phase Epitaxy Basic Transport processes amp reaction kinetics doping amp auto doping equipments amp safety considerations buried layers epitaxial defects molecular beam epitaxy equipment used film characteristics SOI structure
Unit 2
Oxidation [T1]
Growth mechanism amp kinetics Silicon oxidation model interface considerations orientation dependence of oxidation rates thin oxides Oxidation technique amp systems dry amp wet oxidation Masking properties of SiO2
Diffusion [T1]
Diffusion from a chemical source in vapor form at high temperature diffusion from doped oxide source diffusion from an ion implanted layer (
COURSE SYLLABUS
Unit 3
Lithography [T1]
Optical Lithography optical resists contact amp proximity printing projection printing electron lithography resists mask generation Electron optics roster scans amp vector scans variable beam shape X-ray lithography resists amp printing X ray sources amp masks Ion lithography
Unit 4
Etching [T1]
Reactive plasma etching AC amp DC plasma excitation plasma properties chemistry amp surface interactions feature size control amp apostrophic etching ion enhanced amp induced etching properties of etch processing Reactive Ion Beam etching Specific etches processesTrench etching
TEXT AND REFERENCE BOOKS
Text Books
[T1] SM Sze rdquo Modern Semiconductor Device Physicsrdquo John Wiley amp
Sons 2000
Reference Books
[R1]BG Streetman ldquoSolid State Electronics Devicesrdquo Prentice Hall
2002
[R2]ChenldquoVLSI Technologyrdquo Wiley March 2003
Tools Used
Silvaco
OBJECTIVE OF THE COURSE
Understand the impact of the physical and chemical processes of integrated circuit fabrication technology on the design of integrated circuits
Understand physics of the Crystal growth wafer fabrication and basic properties of silicon wafers
Learning contamination reduction and corresponding measurements methods including clean factory wafer cleaning and Gettering
Learning lithography techniques and concepts of wafer exposure system (projection contact and proximity) types of resists (g-line I-line and deep ultra-violate resist) Its measurement methods including mask features defects resist pattern and etched features)
Understand Concepts of thermal oxidation and SiSiO2 interface and its quality measurements (including physical optical and electrical) Modelling and simulation of thermal oxidation
Learn concepts of dopant solid solubility diffusion macroscopic point different solutions to diffusion equation Design and evaluation of diffused layers and its measurement methods
Learn concepts of ion implantation role of the crystals structures high-energy implants ultralow energy implants and ion beam heating methods
Learn concepts of thin film deposition including chemical Vapor Deposition (including APCVD LPCVD PECVD and HDPCVD) and Physical vapor deposition (including evaporation and sputtering)
Learning concepts of Wet etching and Plasma etching mechanism and systems
Learning back-end technology including contacts interconnects vias dielectrics silicided gates sourcedrain regions contact formations global interconnects IMD deposition and planarization Morphological electrical chemical and structure mechanical measurements
A Brief History
Invention of the Transistor
Vacuum tubes ruled in first half of 20th century Large expensive power-hungry unreliable
1947 first point contact transistor (3 terminal devices)
Shockley Bardeen and Brattain at Bell Labs
A Brief History contd
1958 First integrated circuit Flip-flop using two transistors
Built by Jack Kilby (Nobel Laureate) at Texas Instruments
Robert Noyce (Fairchild) is also considered as a co-inventor
smithsonianchipssiedu augarten
Kilbyrsquos IC
A Brief History contd
First Planer IC built in 1961
2003
Intel Pentium 4 processor (55 million transistors)
512 Mbit DRAM (gt 05 billion transistors)
53 compound annual growth rate over 45 years
No other technology has grown so fast so long
Driven by miniaturization of transistors
Smaller is cheaper faster lower in power
Revolutionary effects on society
1970rsquos processes usually had only nMOS transistors
Inexpensive but consume power while idle
1980s-present CMOS processes for low idle power
MOS Integrated Circuits
Intel 1101 256-bit SRAM Intel 4004 4-bit Proc
Moorersquos Law
1965 Gordon Moore plotted transistor on each chip
Fit straight line on semilog scale
Transistor counts have doubled every 26 months
Integration Levels
SSI 10 gates
MSI 1000 gates
LSI 10000 gates
VLSI gt 10k gates
httpwwwintelcomtechnologysiliconmooreslaw
Corollaries
Many other factors grow exponentially
Ex clock frequency processor performance
Year
1
10
100
1000
10000
1970 1975 1980 1985 1990 1995 2000 2005
4004
8008
8080
8086
80286
Intel386
Intel486
Pentium
Pentium ProIIIII
Pentium 4
Clo
ck Speed (M
Hz)
WHY VLSI DESIGN
Money technology civilization
VLSIVERY LARGE SCALE INTEGRATION
Integration Integrated Circuits
multiple devices on one substrate
How large is Very Large SSI (small scale integration)
7400 series 10-100 transistors
MSI (medium scale)
74000 series 100-1000
LSI 1000-10000 transistors
VLSI gt 10000 transistors
ULSI
Integration Improves the Design
bull Lower parasitics higher clocking speed
bull Lower power
bull Physically small
Integration Reduces Manufacturing Costs
bull (almost) no manual assembly
bull About $1-5billionfab
bull Typical Fab 1 city block a few hundred people
bull Packaging is largest cost
bull Testing is second largest cost
bull For low volume ICs Design Cost may swamp
all manufacturing cost
Need of VLSI
bull Specifications
bull IO Goals and Objectives Function Costs
bull Architectural Description
bull VLHD Verilog Behavioral Large Blocks
bull Logic Design
bull Gates plus Registers
bull Circuit Design
bull Transistors sized for power and speed
bull Discrete Logic Technology Mapping
bull Layout
bull Size Interconnect Parasitics
Levels of Design
n+ n+
S
G D
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
WHAT IS ldquoCMOS VLSIrdquo
MOS = Metal Oxide Semiconductor (This used to mean a Metal gate over Oxide insulation)
Now we use polycrystalline silicon which is deposited on the surface of the chip as a gate We call this ldquopolyrdquo or just ldquored stuffrdquo to distinguish it from the body of the chip the substrate which is a single crystal of silicon
We do use metal (aluminum) for interconnection wires on the surface of the chip
CMOSCOMPLEMENTARY MOS
Means we are using both N-channel and P-
channel type enhancement mode Field Effect
Transistors (FETs)
Field Effect- NO current from the controlling
electrode into the output
FET is a voltage controlled current device
BJT is a current controlled current device
NP Channel - doping of the substrate for
increased carriers (electrons or holes)
Complementary Metal Oxide
Semiconductor
PMOS
NMOS
VSS
VDD
X Xrsquo
FOUR VIEWS
Logic Transistor Layout Physical
VLSI DESIGN
The real issue inVLSI is about designing systems
on chips
The designs are complex and we need to use
structured design techniques and sophisticated
design tools to manage the complexity of the
design
We also accept the fact that any technology we
learn the details of will be out of date soon
We are trying to develop and use techniques that
will transcend the technology but still respect it
HELP FROM COMPUTER AIDED DESIGN TOOLS
Tools
Editors
Simulators
Libraries
Module Synthesis
PlaceRoute
Chip Assemblers
Silicon Compilers
Experts
Logic design
Electroniccircuit
design
Device physics
Artwork
Applications - system
design
Architectures
DESIGN STYLES
Full custom
Standard cell
Gate-array
Macro-cell
ldquoFPGArdquo
Combinations
FULL CUSTOM
Hand drawn geometry
All layers customized
Digital and analog
Simulation at transistor level (analog)
High density
High performance
Long design time
FULL CUSTOM
IN Out
Vdd
Gnd
STANDARD CELLS
Standard cells organized in rows (and or flip-flopsetc)
Cells made as full custom by vendor (not user)
All layers customized
Digital with possibility of special analog cells
Simulation at gate level (digital)
Medium density
Medium-high performance
Reasonable design time
STANDARD CELLS
Routing
Cell
IO cell
GATE-ARRAY
Predefined transistors connected via metal
Two types Channel based Channel less (sea of gates)
Only metallization layers customized
Fixed array sizes (normally 5-10 different)
Digital cells in library (and or flip-flopsetc)
Simulation at gate level (digital)
Medium density
Medium performance
Reasonable design time
GATE-ARRAY
Oxide isolation
Gate isolation
PMOS
NMOS
Vdd
Gnd
B A
Out
Vdd
Gnd
A
B
Out
Sea of gates Channel based
NAND gate using gate isolation
Can in principle be used by adjacent cell
Sea of gates
Gate-array
RAM
MACRO CELL
Predefined macro blocks (Processors RAMetc)
Macro blocks made as full custom by vendor
All layers customized
Digital and some analog (ADC)
Simulation at behavioral or gate level (digital)
High density
High performance
Short design time
Use standard on-chip busses
ldquoSystem on a chiprdquo
DSP processor
LCD
cont RAM
ROM ADC
FPGA = FIELD PROGRAMMABLE GATE ARRAY
Programmable logic blocks
Programmable connections between logic blocks
No layers customized (standard devices)
Digital only
Low - medium performance (lt50 - 100MHz)
Low - medium density (up to ~100k gates)
Programmable by SRAM EEROM Anti_fuse etc
Cheap design tools on PCrsquos
Low development cost
High device cost
HIGH PERFORMANCE DEVICES
Mixture of full custom standard cells and
macrorsquos
Full custom for special blocks Adder (data
path) etc
Macrorsquos for standard blocks RAM ROM etc
Standard cells for non critical digital blocks
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large currents
between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between
source and drain
Low power allows very high integration
First patent in the rsquo20s in USA and Germany
Not widely used until the rsquo60s or rsquo70s
MOS TRANSISTORS
Four terminal device gate source drain body
Gate ndash oxide ndash body stack looks like a capacitor
Gate and body are conductors (body is also called the substrate)
SiO2 (oxide) is a ldquogoodrdquo insulator (separates the gate from the body
Called metalndashoxidendashsemiconductor (MOS) capacitor even though gate
is mostly made of poly-crystalline silicon (polysilicon)
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
NMOS PMOS
NMOS OPERATION
Body is commonly tied to ground (0 V)
Drain is at a higher voltage than Source
When the gate is at a low voltage
P-type body is at low voltage
Source-body and drain-body ldquodiodesrdquo are OFF
No current flows transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S
NMOS OPERATION CONT
When the gate is at a high voltage Positive charge on gate of MOS capacitor
Negative charge is attracted to body under the gate
Inverts a channel under gate to ldquon-typerdquo (N-channel hence
called the NMOS) if the gate voltage is above a threshold
voltage (VT)
Now current can flow through ldquon-typerdquo silicon from source
through channel to drain transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
PMOS TRANSISTOR
Similar but doping and voltages reversed
Body tied to high voltage (VDD)
Drain is at a lower voltage than the Source
Gate low transistor ON
Gate high transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
POWER SUPPLY VOLTAGE
GND = 0 V
In 1980rsquos VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 33 25 18 15 12 10
Effective power supply voltage can be lower due
to IR drop across the power grid
HELPING FIELDS FOR IC FABRICATION
Material Engineering
Chemistry
Device Physics
Advanced Technology
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
COURSE SYLLABUS Unit 1
Crystal growth amp wafer preparation Processing considerations Chemical cleaning getting the thermal Stress factors etc
Epitaxy [T1]
Vapors phase Epitaxy Basic Transport processes amp reaction kinetics doping amp auto doping equipments amp safety considerations buried layers epitaxial defects molecular beam epitaxy equipment used film characteristics SOI structure
Unit 2
Oxidation [T1]
Growth mechanism amp kinetics Silicon oxidation model interface considerations orientation dependence of oxidation rates thin oxides Oxidation technique amp systems dry amp wet oxidation Masking properties of SiO2
Diffusion [T1]
Diffusion from a chemical source in vapor form at high temperature diffusion from doped oxide source diffusion from an ion implanted layer (
COURSE SYLLABUS
Unit 3
Lithography [T1]
Optical Lithography optical resists contact amp proximity printing projection printing electron lithography resists mask generation Electron optics roster scans amp vector scans variable beam shape X-ray lithography resists amp printing X ray sources amp masks Ion lithography
Unit 4
Etching [T1]
Reactive plasma etching AC amp DC plasma excitation plasma properties chemistry amp surface interactions feature size control amp apostrophic etching ion enhanced amp induced etching properties of etch processing Reactive Ion Beam etching Specific etches processesTrench etching
TEXT AND REFERENCE BOOKS
Text Books
[T1] SM Sze rdquo Modern Semiconductor Device Physicsrdquo John Wiley amp
Sons 2000
Reference Books
[R1]BG Streetman ldquoSolid State Electronics Devicesrdquo Prentice Hall
2002
[R2]ChenldquoVLSI Technologyrdquo Wiley March 2003
Tools Used
Silvaco
OBJECTIVE OF THE COURSE
Understand the impact of the physical and chemical processes of integrated circuit fabrication technology on the design of integrated circuits
Understand physics of the Crystal growth wafer fabrication and basic properties of silicon wafers
Learning contamination reduction and corresponding measurements methods including clean factory wafer cleaning and Gettering
Learning lithography techniques and concepts of wafer exposure system (projection contact and proximity) types of resists (g-line I-line and deep ultra-violate resist) Its measurement methods including mask features defects resist pattern and etched features)
Understand Concepts of thermal oxidation and SiSiO2 interface and its quality measurements (including physical optical and electrical) Modelling and simulation of thermal oxidation
Learn concepts of dopant solid solubility diffusion macroscopic point different solutions to diffusion equation Design and evaluation of diffused layers and its measurement methods
Learn concepts of ion implantation role of the crystals structures high-energy implants ultralow energy implants and ion beam heating methods
Learn concepts of thin film deposition including chemical Vapor Deposition (including APCVD LPCVD PECVD and HDPCVD) and Physical vapor deposition (including evaporation and sputtering)
Learning concepts of Wet etching and Plasma etching mechanism and systems
Learning back-end technology including contacts interconnects vias dielectrics silicided gates sourcedrain regions contact formations global interconnects IMD deposition and planarization Morphological electrical chemical and structure mechanical measurements
A Brief History
Invention of the Transistor
Vacuum tubes ruled in first half of 20th century Large expensive power-hungry unreliable
1947 first point contact transistor (3 terminal devices)
Shockley Bardeen and Brattain at Bell Labs
A Brief History contd
1958 First integrated circuit Flip-flop using two transistors
Built by Jack Kilby (Nobel Laureate) at Texas Instruments
Robert Noyce (Fairchild) is also considered as a co-inventor
smithsonianchipssiedu augarten
Kilbyrsquos IC
A Brief History contd
First Planer IC built in 1961
2003
Intel Pentium 4 processor (55 million transistors)
512 Mbit DRAM (gt 05 billion transistors)
53 compound annual growth rate over 45 years
No other technology has grown so fast so long
Driven by miniaturization of transistors
Smaller is cheaper faster lower in power
Revolutionary effects on society
1970rsquos processes usually had only nMOS transistors
Inexpensive but consume power while idle
1980s-present CMOS processes for low idle power
MOS Integrated Circuits
Intel 1101 256-bit SRAM Intel 4004 4-bit Proc
Moorersquos Law
1965 Gordon Moore plotted transistor on each chip
Fit straight line on semilog scale
Transistor counts have doubled every 26 months
Integration Levels
SSI 10 gates
MSI 1000 gates
LSI 10000 gates
VLSI gt 10k gates
httpwwwintelcomtechnologysiliconmooreslaw
Corollaries
Many other factors grow exponentially
Ex clock frequency processor performance
Year
1
10
100
1000
10000
1970 1975 1980 1985 1990 1995 2000 2005
4004
8008
8080
8086
80286
Intel386
Intel486
Pentium
Pentium ProIIIII
Pentium 4
Clo
ck Speed (M
Hz)
WHY VLSI DESIGN
Money technology civilization
VLSIVERY LARGE SCALE INTEGRATION
Integration Integrated Circuits
multiple devices on one substrate
How large is Very Large SSI (small scale integration)
7400 series 10-100 transistors
MSI (medium scale)
74000 series 100-1000
LSI 1000-10000 transistors
VLSI gt 10000 transistors
ULSI
Integration Improves the Design
bull Lower parasitics higher clocking speed
bull Lower power
bull Physically small
Integration Reduces Manufacturing Costs
bull (almost) no manual assembly
bull About $1-5billionfab
bull Typical Fab 1 city block a few hundred people
bull Packaging is largest cost
bull Testing is second largest cost
bull For low volume ICs Design Cost may swamp
all manufacturing cost
Need of VLSI
bull Specifications
bull IO Goals and Objectives Function Costs
bull Architectural Description
bull VLHD Verilog Behavioral Large Blocks
bull Logic Design
bull Gates plus Registers
bull Circuit Design
bull Transistors sized for power and speed
bull Discrete Logic Technology Mapping
bull Layout
bull Size Interconnect Parasitics
Levels of Design
n+ n+
S
G D
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
WHAT IS ldquoCMOS VLSIrdquo
MOS = Metal Oxide Semiconductor (This used to mean a Metal gate over Oxide insulation)
Now we use polycrystalline silicon which is deposited on the surface of the chip as a gate We call this ldquopolyrdquo or just ldquored stuffrdquo to distinguish it from the body of the chip the substrate which is a single crystal of silicon
We do use metal (aluminum) for interconnection wires on the surface of the chip
CMOSCOMPLEMENTARY MOS
Means we are using both N-channel and P-
channel type enhancement mode Field Effect
Transistors (FETs)
Field Effect- NO current from the controlling
electrode into the output
FET is a voltage controlled current device
BJT is a current controlled current device
NP Channel - doping of the substrate for
increased carriers (electrons or holes)
Complementary Metal Oxide
Semiconductor
PMOS
NMOS
VSS
VDD
X Xrsquo
FOUR VIEWS
Logic Transistor Layout Physical
VLSI DESIGN
The real issue inVLSI is about designing systems
on chips
The designs are complex and we need to use
structured design techniques and sophisticated
design tools to manage the complexity of the
design
We also accept the fact that any technology we
learn the details of will be out of date soon
We are trying to develop and use techniques that
will transcend the technology but still respect it
HELP FROM COMPUTER AIDED DESIGN TOOLS
Tools
Editors
Simulators
Libraries
Module Synthesis
PlaceRoute
Chip Assemblers
Silicon Compilers
Experts
Logic design
Electroniccircuit
design
Device physics
Artwork
Applications - system
design
Architectures
DESIGN STYLES
Full custom
Standard cell
Gate-array
Macro-cell
ldquoFPGArdquo
Combinations
FULL CUSTOM
Hand drawn geometry
All layers customized
Digital and analog
Simulation at transistor level (analog)
High density
High performance
Long design time
FULL CUSTOM
IN Out
Vdd
Gnd
STANDARD CELLS
Standard cells organized in rows (and or flip-flopsetc)
Cells made as full custom by vendor (not user)
All layers customized
Digital with possibility of special analog cells
Simulation at gate level (digital)
Medium density
Medium-high performance
Reasonable design time
STANDARD CELLS
Routing
Cell
IO cell
GATE-ARRAY
Predefined transistors connected via metal
Two types Channel based Channel less (sea of gates)
Only metallization layers customized
Fixed array sizes (normally 5-10 different)
Digital cells in library (and or flip-flopsetc)
Simulation at gate level (digital)
Medium density
Medium performance
Reasonable design time
GATE-ARRAY
Oxide isolation
Gate isolation
PMOS
NMOS
Vdd
Gnd
B A
Out
Vdd
Gnd
A
B
Out
Sea of gates Channel based
NAND gate using gate isolation
Can in principle be used by adjacent cell
Sea of gates
Gate-array
RAM
MACRO CELL
Predefined macro blocks (Processors RAMetc)
Macro blocks made as full custom by vendor
All layers customized
Digital and some analog (ADC)
Simulation at behavioral or gate level (digital)
High density
High performance
Short design time
Use standard on-chip busses
ldquoSystem on a chiprdquo
DSP processor
LCD
cont RAM
ROM ADC
FPGA = FIELD PROGRAMMABLE GATE ARRAY
Programmable logic blocks
Programmable connections between logic blocks
No layers customized (standard devices)
Digital only
Low - medium performance (lt50 - 100MHz)
Low - medium density (up to ~100k gates)
Programmable by SRAM EEROM Anti_fuse etc
Cheap design tools on PCrsquos
Low development cost
High device cost
HIGH PERFORMANCE DEVICES
Mixture of full custom standard cells and
macrorsquos
Full custom for special blocks Adder (data
path) etc
Macrorsquos for standard blocks RAM ROM etc
Standard cells for non critical digital blocks
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large currents
between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between
source and drain
Low power allows very high integration
First patent in the rsquo20s in USA and Germany
Not widely used until the rsquo60s or rsquo70s
MOS TRANSISTORS
Four terminal device gate source drain body
Gate ndash oxide ndash body stack looks like a capacitor
Gate and body are conductors (body is also called the substrate)
SiO2 (oxide) is a ldquogoodrdquo insulator (separates the gate from the body
Called metalndashoxidendashsemiconductor (MOS) capacitor even though gate
is mostly made of poly-crystalline silicon (polysilicon)
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
NMOS PMOS
NMOS OPERATION
Body is commonly tied to ground (0 V)
Drain is at a higher voltage than Source
When the gate is at a low voltage
P-type body is at low voltage
Source-body and drain-body ldquodiodesrdquo are OFF
No current flows transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S
NMOS OPERATION CONT
When the gate is at a high voltage Positive charge on gate of MOS capacitor
Negative charge is attracted to body under the gate
Inverts a channel under gate to ldquon-typerdquo (N-channel hence
called the NMOS) if the gate voltage is above a threshold
voltage (VT)
Now current can flow through ldquon-typerdquo silicon from source
through channel to drain transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
PMOS TRANSISTOR
Similar but doping and voltages reversed
Body tied to high voltage (VDD)
Drain is at a lower voltage than the Source
Gate low transistor ON
Gate high transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
POWER SUPPLY VOLTAGE
GND = 0 V
In 1980rsquos VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 33 25 18 15 12 10
Effective power supply voltage can be lower due
to IR drop across the power grid
HELPING FIELDS FOR IC FABRICATION
Material Engineering
Chemistry
Device Physics
Advanced Technology
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
COURSE SYLLABUS
Unit 3
Lithography [T1]
Optical Lithography optical resists contact amp proximity printing projection printing electron lithography resists mask generation Electron optics roster scans amp vector scans variable beam shape X-ray lithography resists amp printing X ray sources amp masks Ion lithography
Unit 4
Etching [T1]
Reactive plasma etching AC amp DC plasma excitation plasma properties chemistry amp surface interactions feature size control amp apostrophic etching ion enhanced amp induced etching properties of etch processing Reactive Ion Beam etching Specific etches processesTrench etching
TEXT AND REFERENCE BOOKS
Text Books
[T1] SM Sze rdquo Modern Semiconductor Device Physicsrdquo John Wiley amp
Sons 2000
Reference Books
[R1]BG Streetman ldquoSolid State Electronics Devicesrdquo Prentice Hall
2002
[R2]ChenldquoVLSI Technologyrdquo Wiley March 2003
Tools Used
Silvaco
OBJECTIVE OF THE COURSE
Understand the impact of the physical and chemical processes of integrated circuit fabrication technology on the design of integrated circuits
Understand physics of the Crystal growth wafer fabrication and basic properties of silicon wafers
Learning contamination reduction and corresponding measurements methods including clean factory wafer cleaning and Gettering
Learning lithography techniques and concepts of wafer exposure system (projection contact and proximity) types of resists (g-line I-line and deep ultra-violate resist) Its measurement methods including mask features defects resist pattern and etched features)
Understand Concepts of thermal oxidation and SiSiO2 interface and its quality measurements (including physical optical and electrical) Modelling and simulation of thermal oxidation
Learn concepts of dopant solid solubility diffusion macroscopic point different solutions to diffusion equation Design and evaluation of diffused layers and its measurement methods
Learn concepts of ion implantation role of the crystals structures high-energy implants ultralow energy implants and ion beam heating methods
Learn concepts of thin film deposition including chemical Vapor Deposition (including APCVD LPCVD PECVD and HDPCVD) and Physical vapor deposition (including evaporation and sputtering)
Learning concepts of Wet etching and Plasma etching mechanism and systems
Learning back-end technology including contacts interconnects vias dielectrics silicided gates sourcedrain regions contact formations global interconnects IMD deposition and planarization Morphological electrical chemical and structure mechanical measurements
A Brief History
Invention of the Transistor
Vacuum tubes ruled in first half of 20th century Large expensive power-hungry unreliable
1947 first point contact transistor (3 terminal devices)
Shockley Bardeen and Brattain at Bell Labs
A Brief History contd
1958 First integrated circuit Flip-flop using two transistors
Built by Jack Kilby (Nobel Laureate) at Texas Instruments
Robert Noyce (Fairchild) is also considered as a co-inventor
smithsonianchipssiedu augarten
Kilbyrsquos IC
A Brief History contd
First Planer IC built in 1961
2003
Intel Pentium 4 processor (55 million transistors)
512 Mbit DRAM (gt 05 billion transistors)
53 compound annual growth rate over 45 years
No other technology has grown so fast so long
Driven by miniaturization of transistors
Smaller is cheaper faster lower in power
Revolutionary effects on society
1970rsquos processes usually had only nMOS transistors
Inexpensive but consume power while idle
1980s-present CMOS processes for low idle power
MOS Integrated Circuits
Intel 1101 256-bit SRAM Intel 4004 4-bit Proc
Moorersquos Law
1965 Gordon Moore plotted transistor on each chip
Fit straight line on semilog scale
Transistor counts have doubled every 26 months
Integration Levels
SSI 10 gates
MSI 1000 gates
LSI 10000 gates
VLSI gt 10k gates
httpwwwintelcomtechnologysiliconmooreslaw
Corollaries
Many other factors grow exponentially
Ex clock frequency processor performance
Year
1
10
100
1000
10000
1970 1975 1980 1985 1990 1995 2000 2005
4004
8008
8080
8086
80286
Intel386
Intel486
Pentium
Pentium ProIIIII
Pentium 4
Clo
ck Speed (M
Hz)
WHY VLSI DESIGN
Money technology civilization
VLSIVERY LARGE SCALE INTEGRATION
Integration Integrated Circuits
multiple devices on one substrate
How large is Very Large SSI (small scale integration)
7400 series 10-100 transistors
MSI (medium scale)
74000 series 100-1000
LSI 1000-10000 transistors
VLSI gt 10000 transistors
ULSI
Integration Improves the Design
bull Lower parasitics higher clocking speed
bull Lower power
bull Physically small
Integration Reduces Manufacturing Costs
bull (almost) no manual assembly
bull About $1-5billionfab
bull Typical Fab 1 city block a few hundred people
bull Packaging is largest cost
bull Testing is second largest cost
bull For low volume ICs Design Cost may swamp
all manufacturing cost
Need of VLSI
bull Specifications
bull IO Goals and Objectives Function Costs
bull Architectural Description
bull VLHD Verilog Behavioral Large Blocks
bull Logic Design
bull Gates plus Registers
bull Circuit Design
bull Transistors sized for power and speed
bull Discrete Logic Technology Mapping
bull Layout
bull Size Interconnect Parasitics
Levels of Design
n+ n+
S
G D
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
WHAT IS ldquoCMOS VLSIrdquo
MOS = Metal Oxide Semiconductor (This used to mean a Metal gate over Oxide insulation)
Now we use polycrystalline silicon which is deposited on the surface of the chip as a gate We call this ldquopolyrdquo or just ldquored stuffrdquo to distinguish it from the body of the chip the substrate which is a single crystal of silicon
We do use metal (aluminum) for interconnection wires on the surface of the chip
CMOSCOMPLEMENTARY MOS
Means we are using both N-channel and P-
channel type enhancement mode Field Effect
Transistors (FETs)
Field Effect- NO current from the controlling
electrode into the output
FET is a voltage controlled current device
BJT is a current controlled current device
NP Channel - doping of the substrate for
increased carriers (electrons or holes)
Complementary Metal Oxide
Semiconductor
PMOS
NMOS
VSS
VDD
X Xrsquo
FOUR VIEWS
Logic Transistor Layout Physical
VLSI DESIGN
The real issue inVLSI is about designing systems
on chips
The designs are complex and we need to use
structured design techniques and sophisticated
design tools to manage the complexity of the
design
We also accept the fact that any technology we
learn the details of will be out of date soon
We are trying to develop and use techniques that
will transcend the technology but still respect it
HELP FROM COMPUTER AIDED DESIGN TOOLS
Tools
Editors
Simulators
Libraries
Module Synthesis
PlaceRoute
Chip Assemblers
Silicon Compilers
Experts
Logic design
Electroniccircuit
design
Device physics
Artwork
Applications - system
design
Architectures
DESIGN STYLES
Full custom
Standard cell
Gate-array
Macro-cell
ldquoFPGArdquo
Combinations
FULL CUSTOM
Hand drawn geometry
All layers customized
Digital and analog
Simulation at transistor level (analog)
High density
High performance
Long design time
FULL CUSTOM
IN Out
Vdd
Gnd
STANDARD CELLS
Standard cells organized in rows (and or flip-flopsetc)
Cells made as full custom by vendor (not user)
All layers customized
Digital with possibility of special analog cells
Simulation at gate level (digital)
Medium density
Medium-high performance
Reasonable design time
STANDARD CELLS
Routing
Cell
IO cell
GATE-ARRAY
Predefined transistors connected via metal
Two types Channel based Channel less (sea of gates)
Only metallization layers customized
Fixed array sizes (normally 5-10 different)
Digital cells in library (and or flip-flopsetc)
Simulation at gate level (digital)
Medium density
Medium performance
Reasonable design time
GATE-ARRAY
Oxide isolation
Gate isolation
PMOS
NMOS
Vdd
Gnd
B A
Out
Vdd
Gnd
A
B
Out
Sea of gates Channel based
NAND gate using gate isolation
Can in principle be used by adjacent cell
Sea of gates
Gate-array
RAM
MACRO CELL
Predefined macro blocks (Processors RAMetc)
Macro blocks made as full custom by vendor
All layers customized
Digital and some analog (ADC)
Simulation at behavioral or gate level (digital)
High density
High performance
Short design time
Use standard on-chip busses
ldquoSystem on a chiprdquo
DSP processor
LCD
cont RAM
ROM ADC
FPGA = FIELD PROGRAMMABLE GATE ARRAY
Programmable logic blocks
Programmable connections between logic blocks
No layers customized (standard devices)
Digital only
Low - medium performance (lt50 - 100MHz)
Low - medium density (up to ~100k gates)
Programmable by SRAM EEROM Anti_fuse etc
Cheap design tools on PCrsquos
Low development cost
High device cost
HIGH PERFORMANCE DEVICES
Mixture of full custom standard cells and
macrorsquos
Full custom for special blocks Adder (data
path) etc
Macrorsquos for standard blocks RAM ROM etc
Standard cells for non critical digital blocks
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large currents
between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between
source and drain
Low power allows very high integration
First patent in the rsquo20s in USA and Germany
Not widely used until the rsquo60s or rsquo70s
MOS TRANSISTORS
Four terminal device gate source drain body
Gate ndash oxide ndash body stack looks like a capacitor
Gate and body are conductors (body is also called the substrate)
SiO2 (oxide) is a ldquogoodrdquo insulator (separates the gate from the body
Called metalndashoxidendashsemiconductor (MOS) capacitor even though gate
is mostly made of poly-crystalline silicon (polysilicon)
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
NMOS PMOS
NMOS OPERATION
Body is commonly tied to ground (0 V)
Drain is at a higher voltage than Source
When the gate is at a low voltage
P-type body is at low voltage
Source-body and drain-body ldquodiodesrdquo are OFF
No current flows transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S
NMOS OPERATION CONT
When the gate is at a high voltage Positive charge on gate of MOS capacitor
Negative charge is attracted to body under the gate
Inverts a channel under gate to ldquon-typerdquo (N-channel hence
called the NMOS) if the gate voltage is above a threshold
voltage (VT)
Now current can flow through ldquon-typerdquo silicon from source
through channel to drain transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
PMOS TRANSISTOR
Similar but doping and voltages reversed
Body tied to high voltage (VDD)
Drain is at a lower voltage than the Source
Gate low transistor ON
Gate high transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
POWER SUPPLY VOLTAGE
GND = 0 V
In 1980rsquos VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 33 25 18 15 12 10
Effective power supply voltage can be lower due
to IR drop across the power grid
HELPING FIELDS FOR IC FABRICATION
Material Engineering
Chemistry
Device Physics
Advanced Technology
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
TEXT AND REFERENCE BOOKS
Text Books
[T1] SM Sze rdquo Modern Semiconductor Device Physicsrdquo John Wiley amp
Sons 2000
Reference Books
[R1]BG Streetman ldquoSolid State Electronics Devicesrdquo Prentice Hall
2002
[R2]ChenldquoVLSI Technologyrdquo Wiley March 2003
Tools Used
Silvaco
OBJECTIVE OF THE COURSE
Understand the impact of the physical and chemical processes of integrated circuit fabrication technology on the design of integrated circuits
Understand physics of the Crystal growth wafer fabrication and basic properties of silicon wafers
Learning contamination reduction and corresponding measurements methods including clean factory wafer cleaning and Gettering
Learning lithography techniques and concepts of wafer exposure system (projection contact and proximity) types of resists (g-line I-line and deep ultra-violate resist) Its measurement methods including mask features defects resist pattern and etched features)
Understand Concepts of thermal oxidation and SiSiO2 interface and its quality measurements (including physical optical and electrical) Modelling and simulation of thermal oxidation
Learn concepts of dopant solid solubility diffusion macroscopic point different solutions to diffusion equation Design and evaluation of diffused layers and its measurement methods
Learn concepts of ion implantation role of the crystals structures high-energy implants ultralow energy implants and ion beam heating methods
Learn concepts of thin film deposition including chemical Vapor Deposition (including APCVD LPCVD PECVD and HDPCVD) and Physical vapor deposition (including evaporation and sputtering)
Learning concepts of Wet etching and Plasma etching mechanism and systems
Learning back-end technology including contacts interconnects vias dielectrics silicided gates sourcedrain regions contact formations global interconnects IMD deposition and planarization Morphological electrical chemical and structure mechanical measurements
A Brief History
Invention of the Transistor
Vacuum tubes ruled in first half of 20th century Large expensive power-hungry unreliable
1947 first point contact transistor (3 terminal devices)
Shockley Bardeen and Brattain at Bell Labs
A Brief History contd
1958 First integrated circuit Flip-flop using two transistors
Built by Jack Kilby (Nobel Laureate) at Texas Instruments
Robert Noyce (Fairchild) is also considered as a co-inventor
smithsonianchipssiedu augarten
Kilbyrsquos IC
A Brief History contd
First Planer IC built in 1961
2003
Intel Pentium 4 processor (55 million transistors)
512 Mbit DRAM (gt 05 billion transistors)
53 compound annual growth rate over 45 years
No other technology has grown so fast so long
Driven by miniaturization of transistors
Smaller is cheaper faster lower in power
Revolutionary effects on society
1970rsquos processes usually had only nMOS transistors
Inexpensive but consume power while idle
1980s-present CMOS processes for low idle power
MOS Integrated Circuits
Intel 1101 256-bit SRAM Intel 4004 4-bit Proc
Moorersquos Law
1965 Gordon Moore plotted transistor on each chip
Fit straight line on semilog scale
Transistor counts have doubled every 26 months
Integration Levels
SSI 10 gates
MSI 1000 gates
LSI 10000 gates
VLSI gt 10k gates
httpwwwintelcomtechnologysiliconmooreslaw
Corollaries
Many other factors grow exponentially
Ex clock frequency processor performance
Year
1
10
100
1000
10000
1970 1975 1980 1985 1990 1995 2000 2005
4004
8008
8080
8086
80286
Intel386
Intel486
Pentium
Pentium ProIIIII
Pentium 4
Clo
ck Speed (M
Hz)
WHY VLSI DESIGN
Money technology civilization
VLSIVERY LARGE SCALE INTEGRATION
Integration Integrated Circuits
multiple devices on one substrate
How large is Very Large SSI (small scale integration)
7400 series 10-100 transistors
MSI (medium scale)
74000 series 100-1000
LSI 1000-10000 transistors
VLSI gt 10000 transistors
ULSI
Integration Improves the Design
bull Lower parasitics higher clocking speed
bull Lower power
bull Physically small
Integration Reduces Manufacturing Costs
bull (almost) no manual assembly
bull About $1-5billionfab
bull Typical Fab 1 city block a few hundred people
bull Packaging is largest cost
bull Testing is second largest cost
bull For low volume ICs Design Cost may swamp
all manufacturing cost
Need of VLSI
bull Specifications
bull IO Goals and Objectives Function Costs
bull Architectural Description
bull VLHD Verilog Behavioral Large Blocks
bull Logic Design
bull Gates plus Registers
bull Circuit Design
bull Transistors sized for power and speed
bull Discrete Logic Technology Mapping
bull Layout
bull Size Interconnect Parasitics
Levels of Design
n+ n+
S
G D
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
WHAT IS ldquoCMOS VLSIrdquo
MOS = Metal Oxide Semiconductor (This used to mean a Metal gate over Oxide insulation)
Now we use polycrystalline silicon which is deposited on the surface of the chip as a gate We call this ldquopolyrdquo or just ldquored stuffrdquo to distinguish it from the body of the chip the substrate which is a single crystal of silicon
We do use metal (aluminum) for interconnection wires on the surface of the chip
CMOSCOMPLEMENTARY MOS
Means we are using both N-channel and P-
channel type enhancement mode Field Effect
Transistors (FETs)
Field Effect- NO current from the controlling
electrode into the output
FET is a voltage controlled current device
BJT is a current controlled current device
NP Channel - doping of the substrate for
increased carriers (electrons or holes)
Complementary Metal Oxide
Semiconductor
PMOS
NMOS
VSS
VDD
X Xrsquo
FOUR VIEWS
Logic Transistor Layout Physical
VLSI DESIGN
The real issue inVLSI is about designing systems
on chips
The designs are complex and we need to use
structured design techniques and sophisticated
design tools to manage the complexity of the
design
We also accept the fact that any technology we
learn the details of will be out of date soon
We are trying to develop and use techniques that
will transcend the technology but still respect it
HELP FROM COMPUTER AIDED DESIGN TOOLS
Tools
Editors
Simulators
Libraries
Module Synthesis
PlaceRoute
Chip Assemblers
Silicon Compilers
Experts
Logic design
Electroniccircuit
design
Device physics
Artwork
Applications - system
design
Architectures
DESIGN STYLES
Full custom
Standard cell
Gate-array
Macro-cell
ldquoFPGArdquo
Combinations
FULL CUSTOM
Hand drawn geometry
All layers customized
Digital and analog
Simulation at transistor level (analog)
High density
High performance
Long design time
FULL CUSTOM
IN Out
Vdd
Gnd
STANDARD CELLS
Standard cells organized in rows (and or flip-flopsetc)
Cells made as full custom by vendor (not user)
All layers customized
Digital with possibility of special analog cells
Simulation at gate level (digital)
Medium density
Medium-high performance
Reasonable design time
STANDARD CELLS
Routing
Cell
IO cell
GATE-ARRAY
Predefined transistors connected via metal
Two types Channel based Channel less (sea of gates)
Only metallization layers customized
Fixed array sizes (normally 5-10 different)
Digital cells in library (and or flip-flopsetc)
Simulation at gate level (digital)
Medium density
Medium performance
Reasonable design time
GATE-ARRAY
Oxide isolation
Gate isolation
PMOS
NMOS
Vdd
Gnd
B A
Out
Vdd
Gnd
A
B
Out
Sea of gates Channel based
NAND gate using gate isolation
Can in principle be used by adjacent cell
Sea of gates
Gate-array
RAM
MACRO CELL
Predefined macro blocks (Processors RAMetc)
Macro blocks made as full custom by vendor
All layers customized
Digital and some analog (ADC)
Simulation at behavioral or gate level (digital)
High density
High performance
Short design time
Use standard on-chip busses
ldquoSystem on a chiprdquo
DSP processor
LCD
cont RAM
ROM ADC
FPGA = FIELD PROGRAMMABLE GATE ARRAY
Programmable logic blocks
Programmable connections between logic blocks
No layers customized (standard devices)
Digital only
Low - medium performance (lt50 - 100MHz)
Low - medium density (up to ~100k gates)
Programmable by SRAM EEROM Anti_fuse etc
Cheap design tools on PCrsquos
Low development cost
High device cost
HIGH PERFORMANCE DEVICES
Mixture of full custom standard cells and
macrorsquos
Full custom for special blocks Adder (data
path) etc
Macrorsquos for standard blocks RAM ROM etc
Standard cells for non critical digital blocks
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large currents
between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between
source and drain
Low power allows very high integration
First patent in the rsquo20s in USA and Germany
Not widely used until the rsquo60s or rsquo70s
MOS TRANSISTORS
Four terminal device gate source drain body
Gate ndash oxide ndash body stack looks like a capacitor
Gate and body are conductors (body is also called the substrate)
SiO2 (oxide) is a ldquogoodrdquo insulator (separates the gate from the body
Called metalndashoxidendashsemiconductor (MOS) capacitor even though gate
is mostly made of poly-crystalline silicon (polysilicon)
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
NMOS PMOS
NMOS OPERATION
Body is commonly tied to ground (0 V)
Drain is at a higher voltage than Source
When the gate is at a low voltage
P-type body is at low voltage
Source-body and drain-body ldquodiodesrdquo are OFF
No current flows transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S
NMOS OPERATION CONT
When the gate is at a high voltage Positive charge on gate of MOS capacitor
Negative charge is attracted to body under the gate
Inverts a channel under gate to ldquon-typerdquo (N-channel hence
called the NMOS) if the gate voltage is above a threshold
voltage (VT)
Now current can flow through ldquon-typerdquo silicon from source
through channel to drain transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
PMOS TRANSISTOR
Similar but doping and voltages reversed
Body tied to high voltage (VDD)
Drain is at a lower voltage than the Source
Gate low transistor ON
Gate high transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
POWER SUPPLY VOLTAGE
GND = 0 V
In 1980rsquos VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 33 25 18 15 12 10
Effective power supply voltage can be lower due
to IR drop across the power grid
HELPING FIELDS FOR IC FABRICATION
Material Engineering
Chemistry
Device Physics
Advanced Technology
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
OBJECTIVE OF THE COURSE
Understand the impact of the physical and chemical processes of integrated circuit fabrication technology on the design of integrated circuits
Understand physics of the Crystal growth wafer fabrication and basic properties of silicon wafers
Learning contamination reduction and corresponding measurements methods including clean factory wafer cleaning and Gettering
Learning lithography techniques and concepts of wafer exposure system (projection contact and proximity) types of resists (g-line I-line and deep ultra-violate resist) Its measurement methods including mask features defects resist pattern and etched features)
Understand Concepts of thermal oxidation and SiSiO2 interface and its quality measurements (including physical optical and electrical) Modelling and simulation of thermal oxidation
Learn concepts of dopant solid solubility diffusion macroscopic point different solutions to diffusion equation Design and evaluation of diffused layers and its measurement methods
Learn concepts of ion implantation role of the crystals structures high-energy implants ultralow energy implants and ion beam heating methods
Learn concepts of thin film deposition including chemical Vapor Deposition (including APCVD LPCVD PECVD and HDPCVD) and Physical vapor deposition (including evaporation and sputtering)
Learning concepts of Wet etching and Plasma etching mechanism and systems
Learning back-end technology including contacts interconnects vias dielectrics silicided gates sourcedrain regions contact formations global interconnects IMD deposition and planarization Morphological electrical chemical and structure mechanical measurements
A Brief History
Invention of the Transistor
Vacuum tubes ruled in first half of 20th century Large expensive power-hungry unreliable
1947 first point contact transistor (3 terminal devices)
Shockley Bardeen and Brattain at Bell Labs
A Brief History contd
1958 First integrated circuit Flip-flop using two transistors
Built by Jack Kilby (Nobel Laureate) at Texas Instruments
Robert Noyce (Fairchild) is also considered as a co-inventor
smithsonianchipssiedu augarten
Kilbyrsquos IC
A Brief History contd
First Planer IC built in 1961
2003
Intel Pentium 4 processor (55 million transistors)
512 Mbit DRAM (gt 05 billion transistors)
53 compound annual growth rate over 45 years
No other technology has grown so fast so long
Driven by miniaturization of transistors
Smaller is cheaper faster lower in power
Revolutionary effects on society
1970rsquos processes usually had only nMOS transistors
Inexpensive but consume power while idle
1980s-present CMOS processes for low idle power
MOS Integrated Circuits
Intel 1101 256-bit SRAM Intel 4004 4-bit Proc
Moorersquos Law
1965 Gordon Moore plotted transistor on each chip
Fit straight line on semilog scale
Transistor counts have doubled every 26 months
Integration Levels
SSI 10 gates
MSI 1000 gates
LSI 10000 gates
VLSI gt 10k gates
httpwwwintelcomtechnologysiliconmooreslaw
Corollaries
Many other factors grow exponentially
Ex clock frequency processor performance
Year
1
10
100
1000
10000
1970 1975 1980 1985 1990 1995 2000 2005
4004
8008
8080
8086
80286
Intel386
Intel486
Pentium
Pentium ProIIIII
Pentium 4
Clo
ck Speed (M
Hz)
WHY VLSI DESIGN
Money technology civilization
VLSIVERY LARGE SCALE INTEGRATION
Integration Integrated Circuits
multiple devices on one substrate
How large is Very Large SSI (small scale integration)
7400 series 10-100 transistors
MSI (medium scale)
74000 series 100-1000
LSI 1000-10000 transistors
VLSI gt 10000 transistors
ULSI
Integration Improves the Design
bull Lower parasitics higher clocking speed
bull Lower power
bull Physically small
Integration Reduces Manufacturing Costs
bull (almost) no manual assembly
bull About $1-5billionfab
bull Typical Fab 1 city block a few hundred people
bull Packaging is largest cost
bull Testing is second largest cost
bull For low volume ICs Design Cost may swamp
all manufacturing cost
Need of VLSI
bull Specifications
bull IO Goals and Objectives Function Costs
bull Architectural Description
bull VLHD Verilog Behavioral Large Blocks
bull Logic Design
bull Gates plus Registers
bull Circuit Design
bull Transistors sized for power and speed
bull Discrete Logic Technology Mapping
bull Layout
bull Size Interconnect Parasitics
Levels of Design
n+ n+
S
G D
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
WHAT IS ldquoCMOS VLSIrdquo
MOS = Metal Oxide Semiconductor (This used to mean a Metal gate over Oxide insulation)
Now we use polycrystalline silicon which is deposited on the surface of the chip as a gate We call this ldquopolyrdquo or just ldquored stuffrdquo to distinguish it from the body of the chip the substrate which is a single crystal of silicon
We do use metal (aluminum) for interconnection wires on the surface of the chip
CMOSCOMPLEMENTARY MOS
Means we are using both N-channel and P-
channel type enhancement mode Field Effect
Transistors (FETs)
Field Effect- NO current from the controlling
electrode into the output
FET is a voltage controlled current device
BJT is a current controlled current device
NP Channel - doping of the substrate for
increased carriers (electrons or holes)
Complementary Metal Oxide
Semiconductor
PMOS
NMOS
VSS
VDD
X Xrsquo
FOUR VIEWS
Logic Transistor Layout Physical
VLSI DESIGN
The real issue inVLSI is about designing systems
on chips
The designs are complex and we need to use
structured design techniques and sophisticated
design tools to manage the complexity of the
design
We also accept the fact that any technology we
learn the details of will be out of date soon
We are trying to develop and use techniques that
will transcend the technology but still respect it
HELP FROM COMPUTER AIDED DESIGN TOOLS
Tools
Editors
Simulators
Libraries
Module Synthesis
PlaceRoute
Chip Assemblers
Silicon Compilers
Experts
Logic design
Electroniccircuit
design
Device physics
Artwork
Applications - system
design
Architectures
DESIGN STYLES
Full custom
Standard cell
Gate-array
Macro-cell
ldquoFPGArdquo
Combinations
FULL CUSTOM
Hand drawn geometry
All layers customized
Digital and analog
Simulation at transistor level (analog)
High density
High performance
Long design time
FULL CUSTOM
IN Out
Vdd
Gnd
STANDARD CELLS
Standard cells organized in rows (and or flip-flopsetc)
Cells made as full custom by vendor (not user)
All layers customized
Digital with possibility of special analog cells
Simulation at gate level (digital)
Medium density
Medium-high performance
Reasonable design time
STANDARD CELLS
Routing
Cell
IO cell
GATE-ARRAY
Predefined transistors connected via metal
Two types Channel based Channel less (sea of gates)
Only metallization layers customized
Fixed array sizes (normally 5-10 different)
Digital cells in library (and or flip-flopsetc)
Simulation at gate level (digital)
Medium density
Medium performance
Reasonable design time
GATE-ARRAY
Oxide isolation
Gate isolation
PMOS
NMOS
Vdd
Gnd
B A
Out
Vdd
Gnd
A
B
Out
Sea of gates Channel based
NAND gate using gate isolation
Can in principle be used by adjacent cell
Sea of gates
Gate-array
RAM
MACRO CELL
Predefined macro blocks (Processors RAMetc)
Macro blocks made as full custom by vendor
All layers customized
Digital and some analog (ADC)
Simulation at behavioral or gate level (digital)
High density
High performance
Short design time
Use standard on-chip busses
ldquoSystem on a chiprdquo
DSP processor
LCD
cont RAM
ROM ADC
FPGA = FIELD PROGRAMMABLE GATE ARRAY
Programmable logic blocks
Programmable connections between logic blocks
No layers customized (standard devices)
Digital only
Low - medium performance (lt50 - 100MHz)
Low - medium density (up to ~100k gates)
Programmable by SRAM EEROM Anti_fuse etc
Cheap design tools on PCrsquos
Low development cost
High device cost
HIGH PERFORMANCE DEVICES
Mixture of full custom standard cells and
macrorsquos
Full custom for special blocks Adder (data
path) etc
Macrorsquos for standard blocks RAM ROM etc
Standard cells for non critical digital blocks
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large currents
between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between
source and drain
Low power allows very high integration
First patent in the rsquo20s in USA and Germany
Not widely used until the rsquo60s or rsquo70s
MOS TRANSISTORS
Four terminal device gate source drain body
Gate ndash oxide ndash body stack looks like a capacitor
Gate and body are conductors (body is also called the substrate)
SiO2 (oxide) is a ldquogoodrdquo insulator (separates the gate from the body
Called metalndashoxidendashsemiconductor (MOS) capacitor even though gate
is mostly made of poly-crystalline silicon (polysilicon)
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
NMOS PMOS
NMOS OPERATION
Body is commonly tied to ground (0 V)
Drain is at a higher voltage than Source
When the gate is at a low voltage
P-type body is at low voltage
Source-body and drain-body ldquodiodesrdquo are OFF
No current flows transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S
NMOS OPERATION CONT
When the gate is at a high voltage Positive charge on gate of MOS capacitor
Negative charge is attracted to body under the gate
Inverts a channel under gate to ldquon-typerdquo (N-channel hence
called the NMOS) if the gate voltage is above a threshold
voltage (VT)
Now current can flow through ldquon-typerdquo silicon from source
through channel to drain transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
PMOS TRANSISTOR
Similar but doping and voltages reversed
Body tied to high voltage (VDD)
Drain is at a lower voltage than the Source
Gate low transistor ON
Gate high transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
POWER SUPPLY VOLTAGE
GND = 0 V
In 1980rsquos VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 33 25 18 15 12 10
Effective power supply voltage can be lower due
to IR drop across the power grid
HELPING FIELDS FOR IC FABRICATION
Material Engineering
Chemistry
Device Physics
Advanced Technology
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
Learn concepts of dopant solid solubility diffusion macroscopic point different solutions to diffusion equation Design and evaluation of diffused layers and its measurement methods
Learn concepts of ion implantation role of the crystals structures high-energy implants ultralow energy implants and ion beam heating methods
Learn concepts of thin film deposition including chemical Vapor Deposition (including APCVD LPCVD PECVD and HDPCVD) and Physical vapor deposition (including evaporation and sputtering)
Learning concepts of Wet etching and Plasma etching mechanism and systems
Learning back-end technology including contacts interconnects vias dielectrics silicided gates sourcedrain regions contact formations global interconnects IMD deposition and planarization Morphological electrical chemical and structure mechanical measurements
A Brief History
Invention of the Transistor
Vacuum tubes ruled in first half of 20th century Large expensive power-hungry unreliable
1947 first point contact transistor (3 terminal devices)
Shockley Bardeen and Brattain at Bell Labs
A Brief History contd
1958 First integrated circuit Flip-flop using two transistors
Built by Jack Kilby (Nobel Laureate) at Texas Instruments
Robert Noyce (Fairchild) is also considered as a co-inventor
smithsonianchipssiedu augarten
Kilbyrsquos IC
A Brief History contd
First Planer IC built in 1961
2003
Intel Pentium 4 processor (55 million transistors)
512 Mbit DRAM (gt 05 billion transistors)
53 compound annual growth rate over 45 years
No other technology has grown so fast so long
Driven by miniaturization of transistors
Smaller is cheaper faster lower in power
Revolutionary effects on society
1970rsquos processes usually had only nMOS transistors
Inexpensive but consume power while idle
1980s-present CMOS processes for low idle power
MOS Integrated Circuits
Intel 1101 256-bit SRAM Intel 4004 4-bit Proc
Moorersquos Law
1965 Gordon Moore plotted transistor on each chip
Fit straight line on semilog scale
Transistor counts have doubled every 26 months
Integration Levels
SSI 10 gates
MSI 1000 gates
LSI 10000 gates
VLSI gt 10k gates
httpwwwintelcomtechnologysiliconmooreslaw
Corollaries
Many other factors grow exponentially
Ex clock frequency processor performance
Year
1
10
100
1000
10000
1970 1975 1980 1985 1990 1995 2000 2005
4004
8008
8080
8086
80286
Intel386
Intel486
Pentium
Pentium ProIIIII
Pentium 4
Clo
ck Speed (M
Hz)
WHY VLSI DESIGN
Money technology civilization
VLSIVERY LARGE SCALE INTEGRATION
Integration Integrated Circuits
multiple devices on one substrate
How large is Very Large SSI (small scale integration)
7400 series 10-100 transistors
MSI (medium scale)
74000 series 100-1000
LSI 1000-10000 transistors
VLSI gt 10000 transistors
ULSI
Integration Improves the Design
bull Lower parasitics higher clocking speed
bull Lower power
bull Physically small
Integration Reduces Manufacturing Costs
bull (almost) no manual assembly
bull About $1-5billionfab
bull Typical Fab 1 city block a few hundred people
bull Packaging is largest cost
bull Testing is second largest cost
bull For low volume ICs Design Cost may swamp
all manufacturing cost
Need of VLSI
bull Specifications
bull IO Goals and Objectives Function Costs
bull Architectural Description
bull VLHD Verilog Behavioral Large Blocks
bull Logic Design
bull Gates plus Registers
bull Circuit Design
bull Transistors sized for power and speed
bull Discrete Logic Technology Mapping
bull Layout
bull Size Interconnect Parasitics
Levels of Design
n+ n+
S
G D
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
WHAT IS ldquoCMOS VLSIrdquo
MOS = Metal Oxide Semiconductor (This used to mean a Metal gate over Oxide insulation)
Now we use polycrystalline silicon which is deposited on the surface of the chip as a gate We call this ldquopolyrdquo or just ldquored stuffrdquo to distinguish it from the body of the chip the substrate which is a single crystal of silicon
We do use metal (aluminum) for interconnection wires on the surface of the chip
CMOSCOMPLEMENTARY MOS
Means we are using both N-channel and P-
channel type enhancement mode Field Effect
Transistors (FETs)
Field Effect- NO current from the controlling
electrode into the output
FET is a voltage controlled current device
BJT is a current controlled current device
NP Channel - doping of the substrate for
increased carriers (electrons or holes)
Complementary Metal Oxide
Semiconductor
PMOS
NMOS
VSS
VDD
X Xrsquo
FOUR VIEWS
Logic Transistor Layout Physical
VLSI DESIGN
The real issue inVLSI is about designing systems
on chips
The designs are complex and we need to use
structured design techniques and sophisticated
design tools to manage the complexity of the
design
We also accept the fact that any technology we
learn the details of will be out of date soon
We are trying to develop and use techniques that
will transcend the technology but still respect it
HELP FROM COMPUTER AIDED DESIGN TOOLS
Tools
Editors
Simulators
Libraries
Module Synthesis
PlaceRoute
Chip Assemblers
Silicon Compilers
Experts
Logic design
Electroniccircuit
design
Device physics
Artwork
Applications - system
design
Architectures
DESIGN STYLES
Full custom
Standard cell
Gate-array
Macro-cell
ldquoFPGArdquo
Combinations
FULL CUSTOM
Hand drawn geometry
All layers customized
Digital and analog
Simulation at transistor level (analog)
High density
High performance
Long design time
FULL CUSTOM
IN Out
Vdd
Gnd
STANDARD CELLS
Standard cells organized in rows (and or flip-flopsetc)
Cells made as full custom by vendor (not user)
All layers customized
Digital with possibility of special analog cells
Simulation at gate level (digital)
Medium density
Medium-high performance
Reasonable design time
STANDARD CELLS
Routing
Cell
IO cell
GATE-ARRAY
Predefined transistors connected via metal
Two types Channel based Channel less (sea of gates)
Only metallization layers customized
Fixed array sizes (normally 5-10 different)
Digital cells in library (and or flip-flopsetc)
Simulation at gate level (digital)
Medium density
Medium performance
Reasonable design time
GATE-ARRAY
Oxide isolation
Gate isolation
PMOS
NMOS
Vdd
Gnd
B A
Out
Vdd
Gnd
A
B
Out
Sea of gates Channel based
NAND gate using gate isolation
Can in principle be used by adjacent cell
Sea of gates
Gate-array
RAM
MACRO CELL
Predefined macro blocks (Processors RAMetc)
Macro blocks made as full custom by vendor
All layers customized
Digital and some analog (ADC)
Simulation at behavioral or gate level (digital)
High density
High performance
Short design time
Use standard on-chip busses
ldquoSystem on a chiprdquo
DSP processor
LCD
cont RAM
ROM ADC
FPGA = FIELD PROGRAMMABLE GATE ARRAY
Programmable logic blocks
Programmable connections between logic blocks
No layers customized (standard devices)
Digital only
Low - medium performance (lt50 - 100MHz)
Low - medium density (up to ~100k gates)
Programmable by SRAM EEROM Anti_fuse etc
Cheap design tools on PCrsquos
Low development cost
High device cost
HIGH PERFORMANCE DEVICES
Mixture of full custom standard cells and
macrorsquos
Full custom for special blocks Adder (data
path) etc
Macrorsquos for standard blocks RAM ROM etc
Standard cells for non critical digital blocks
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large currents
between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between
source and drain
Low power allows very high integration
First patent in the rsquo20s in USA and Germany
Not widely used until the rsquo60s or rsquo70s
MOS TRANSISTORS
Four terminal device gate source drain body
Gate ndash oxide ndash body stack looks like a capacitor
Gate and body are conductors (body is also called the substrate)
SiO2 (oxide) is a ldquogoodrdquo insulator (separates the gate from the body
Called metalndashoxidendashsemiconductor (MOS) capacitor even though gate
is mostly made of poly-crystalline silicon (polysilicon)
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
NMOS PMOS
NMOS OPERATION
Body is commonly tied to ground (0 V)
Drain is at a higher voltage than Source
When the gate is at a low voltage
P-type body is at low voltage
Source-body and drain-body ldquodiodesrdquo are OFF
No current flows transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S
NMOS OPERATION CONT
When the gate is at a high voltage Positive charge on gate of MOS capacitor
Negative charge is attracted to body under the gate
Inverts a channel under gate to ldquon-typerdquo (N-channel hence
called the NMOS) if the gate voltage is above a threshold
voltage (VT)
Now current can flow through ldquon-typerdquo silicon from source
through channel to drain transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
PMOS TRANSISTOR
Similar but doping and voltages reversed
Body tied to high voltage (VDD)
Drain is at a lower voltage than the Source
Gate low transistor ON
Gate high transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
POWER SUPPLY VOLTAGE
GND = 0 V
In 1980rsquos VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 33 25 18 15 12 10
Effective power supply voltage can be lower due
to IR drop across the power grid
HELPING FIELDS FOR IC FABRICATION
Material Engineering
Chemistry
Device Physics
Advanced Technology
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
A Brief History
Invention of the Transistor
Vacuum tubes ruled in first half of 20th century Large expensive power-hungry unreliable
1947 first point contact transistor (3 terminal devices)
Shockley Bardeen and Brattain at Bell Labs
A Brief History contd
1958 First integrated circuit Flip-flop using two transistors
Built by Jack Kilby (Nobel Laureate) at Texas Instruments
Robert Noyce (Fairchild) is also considered as a co-inventor
smithsonianchipssiedu augarten
Kilbyrsquos IC
A Brief History contd
First Planer IC built in 1961
2003
Intel Pentium 4 processor (55 million transistors)
512 Mbit DRAM (gt 05 billion transistors)
53 compound annual growth rate over 45 years
No other technology has grown so fast so long
Driven by miniaturization of transistors
Smaller is cheaper faster lower in power
Revolutionary effects on society
1970rsquos processes usually had only nMOS transistors
Inexpensive but consume power while idle
1980s-present CMOS processes for low idle power
MOS Integrated Circuits
Intel 1101 256-bit SRAM Intel 4004 4-bit Proc
Moorersquos Law
1965 Gordon Moore plotted transistor on each chip
Fit straight line on semilog scale
Transistor counts have doubled every 26 months
Integration Levels
SSI 10 gates
MSI 1000 gates
LSI 10000 gates
VLSI gt 10k gates
httpwwwintelcomtechnologysiliconmooreslaw
Corollaries
Many other factors grow exponentially
Ex clock frequency processor performance
Year
1
10
100
1000
10000
1970 1975 1980 1985 1990 1995 2000 2005
4004
8008
8080
8086
80286
Intel386
Intel486
Pentium
Pentium ProIIIII
Pentium 4
Clo
ck Speed (M
Hz)
WHY VLSI DESIGN
Money technology civilization
VLSIVERY LARGE SCALE INTEGRATION
Integration Integrated Circuits
multiple devices on one substrate
How large is Very Large SSI (small scale integration)
7400 series 10-100 transistors
MSI (medium scale)
74000 series 100-1000
LSI 1000-10000 transistors
VLSI gt 10000 transistors
ULSI
Integration Improves the Design
bull Lower parasitics higher clocking speed
bull Lower power
bull Physically small
Integration Reduces Manufacturing Costs
bull (almost) no manual assembly
bull About $1-5billionfab
bull Typical Fab 1 city block a few hundred people
bull Packaging is largest cost
bull Testing is second largest cost
bull For low volume ICs Design Cost may swamp
all manufacturing cost
Need of VLSI
bull Specifications
bull IO Goals and Objectives Function Costs
bull Architectural Description
bull VLHD Verilog Behavioral Large Blocks
bull Logic Design
bull Gates plus Registers
bull Circuit Design
bull Transistors sized for power and speed
bull Discrete Logic Technology Mapping
bull Layout
bull Size Interconnect Parasitics
Levels of Design
n+ n+
S
G D
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
WHAT IS ldquoCMOS VLSIrdquo
MOS = Metal Oxide Semiconductor (This used to mean a Metal gate over Oxide insulation)
Now we use polycrystalline silicon which is deposited on the surface of the chip as a gate We call this ldquopolyrdquo or just ldquored stuffrdquo to distinguish it from the body of the chip the substrate which is a single crystal of silicon
We do use metal (aluminum) for interconnection wires on the surface of the chip
CMOSCOMPLEMENTARY MOS
Means we are using both N-channel and P-
channel type enhancement mode Field Effect
Transistors (FETs)
Field Effect- NO current from the controlling
electrode into the output
FET is a voltage controlled current device
BJT is a current controlled current device
NP Channel - doping of the substrate for
increased carriers (electrons or holes)
Complementary Metal Oxide
Semiconductor
PMOS
NMOS
VSS
VDD
X Xrsquo
FOUR VIEWS
Logic Transistor Layout Physical
VLSI DESIGN
The real issue inVLSI is about designing systems
on chips
The designs are complex and we need to use
structured design techniques and sophisticated
design tools to manage the complexity of the
design
We also accept the fact that any technology we
learn the details of will be out of date soon
We are trying to develop and use techniques that
will transcend the technology but still respect it
HELP FROM COMPUTER AIDED DESIGN TOOLS
Tools
Editors
Simulators
Libraries
Module Synthesis
PlaceRoute
Chip Assemblers
Silicon Compilers
Experts
Logic design
Electroniccircuit
design
Device physics
Artwork
Applications - system
design
Architectures
DESIGN STYLES
Full custom
Standard cell
Gate-array
Macro-cell
ldquoFPGArdquo
Combinations
FULL CUSTOM
Hand drawn geometry
All layers customized
Digital and analog
Simulation at transistor level (analog)
High density
High performance
Long design time
FULL CUSTOM
IN Out
Vdd
Gnd
STANDARD CELLS
Standard cells organized in rows (and or flip-flopsetc)
Cells made as full custom by vendor (not user)
All layers customized
Digital with possibility of special analog cells
Simulation at gate level (digital)
Medium density
Medium-high performance
Reasonable design time
STANDARD CELLS
Routing
Cell
IO cell
GATE-ARRAY
Predefined transistors connected via metal
Two types Channel based Channel less (sea of gates)
Only metallization layers customized
Fixed array sizes (normally 5-10 different)
Digital cells in library (and or flip-flopsetc)
Simulation at gate level (digital)
Medium density
Medium performance
Reasonable design time
GATE-ARRAY
Oxide isolation
Gate isolation
PMOS
NMOS
Vdd
Gnd
B A
Out
Vdd
Gnd
A
B
Out
Sea of gates Channel based
NAND gate using gate isolation
Can in principle be used by adjacent cell
Sea of gates
Gate-array
RAM
MACRO CELL
Predefined macro blocks (Processors RAMetc)
Macro blocks made as full custom by vendor
All layers customized
Digital and some analog (ADC)
Simulation at behavioral or gate level (digital)
High density
High performance
Short design time
Use standard on-chip busses
ldquoSystem on a chiprdquo
DSP processor
LCD
cont RAM
ROM ADC
FPGA = FIELD PROGRAMMABLE GATE ARRAY
Programmable logic blocks
Programmable connections between logic blocks
No layers customized (standard devices)
Digital only
Low - medium performance (lt50 - 100MHz)
Low - medium density (up to ~100k gates)
Programmable by SRAM EEROM Anti_fuse etc
Cheap design tools on PCrsquos
Low development cost
High device cost
HIGH PERFORMANCE DEVICES
Mixture of full custom standard cells and
macrorsquos
Full custom for special blocks Adder (data
path) etc
Macrorsquos for standard blocks RAM ROM etc
Standard cells for non critical digital blocks
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large currents
between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between
source and drain
Low power allows very high integration
First patent in the rsquo20s in USA and Germany
Not widely used until the rsquo60s or rsquo70s
MOS TRANSISTORS
Four terminal device gate source drain body
Gate ndash oxide ndash body stack looks like a capacitor
Gate and body are conductors (body is also called the substrate)
SiO2 (oxide) is a ldquogoodrdquo insulator (separates the gate from the body
Called metalndashoxidendashsemiconductor (MOS) capacitor even though gate
is mostly made of poly-crystalline silicon (polysilicon)
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
NMOS PMOS
NMOS OPERATION
Body is commonly tied to ground (0 V)
Drain is at a higher voltage than Source
When the gate is at a low voltage
P-type body is at low voltage
Source-body and drain-body ldquodiodesrdquo are OFF
No current flows transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S
NMOS OPERATION CONT
When the gate is at a high voltage Positive charge on gate of MOS capacitor
Negative charge is attracted to body under the gate
Inverts a channel under gate to ldquon-typerdquo (N-channel hence
called the NMOS) if the gate voltage is above a threshold
voltage (VT)
Now current can flow through ldquon-typerdquo silicon from source
through channel to drain transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
PMOS TRANSISTOR
Similar but doping and voltages reversed
Body tied to high voltage (VDD)
Drain is at a lower voltage than the Source
Gate low transistor ON
Gate high transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
POWER SUPPLY VOLTAGE
GND = 0 V
In 1980rsquos VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 33 25 18 15 12 10
Effective power supply voltage can be lower due
to IR drop across the power grid
HELPING FIELDS FOR IC FABRICATION
Material Engineering
Chemistry
Device Physics
Advanced Technology
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
A Brief History contd
1958 First integrated circuit Flip-flop using two transistors
Built by Jack Kilby (Nobel Laureate) at Texas Instruments
Robert Noyce (Fairchild) is also considered as a co-inventor
smithsonianchipssiedu augarten
Kilbyrsquos IC
A Brief History contd
First Planer IC built in 1961
2003
Intel Pentium 4 processor (55 million transistors)
512 Mbit DRAM (gt 05 billion transistors)
53 compound annual growth rate over 45 years
No other technology has grown so fast so long
Driven by miniaturization of transistors
Smaller is cheaper faster lower in power
Revolutionary effects on society
1970rsquos processes usually had only nMOS transistors
Inexpensive but consume power while idle
1980s-present CMOS processes for low idle power
MOS Integrated Circuits
Intel 1101 256-bit SRAM Intel 4004 4-bit Proc
Moorersquos Law
1965 Gordon Moore plotted transistor on each chip
Fit straight line on semilog scale
Transistor counts have doubled every 26 months
Integration Levels
SSI 10 gates
MSI 1000 gates
LSI 10000 gates
VLSI gt 10k gates
httpwwwintelcomtechnologysiliconmooreslaw
Corollaries
Many other factors grow exponentially
Ex clock frequency processor performance
Year
1
10
100
1000
10000
1970 1975 1980 1985 1990 1995 2000 2005
4004
8008
8080
8086
80286
Intel386
Intel486
Pentium
Pentium ProIIIII
Pentium 4
Clo
ck Speed (M
Hz)
WHY VLSI DESIGN
Money technology civilization
VLSIVERY LARGE SCALE INTEGRATION
Integration Integrated Circuits
multiple devices on one substrate
How large is Very Large SSI (small scale integration)
7400 series 10-100 transistors
MSI (medium scale)
74000 series 100-1000
LSI 1000-10000 transistors
VLSI gt 10000 transistors
ULSI
Integration Improves the Design
bull Lower parasitics higher clocking speed
bull Lower power
bull Physically small
Integration Reduces Manufacturing Costs
bull (almost) no manual assembly
bull About $1-5billionfab
bull Typical Fab 1 city block a few hundred people
bull Packaging is largest cost
bull Testing is second largest cost
bull For low volume ICs Design Cost may swamp
all manufacturing cost
Need of VLSI
bull Specifications
bull IO Goals and Objectives Function Costs
bull Architectural Description
bull VLHD Verilog Behavioral Large Blocks
bull Logic Design
bull Gates plus Registers
bull Circuit Design
bull Transistors sized for power and speed
bull Discrete Logic Technology Mapping
bull Layout
bull Size Interconnect Parasitics
Levels of Design
n+ n+
S
G D
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
WHAT IS ldquoCMOS VLSIrdquo
MOS = Metal Oxide Semiconductor (This used to mean a Metal gate over Oxide insulation)
Now we use polycrystalline silicon which is deposited on the surface of the chip as a gate We call this ldquopolyrdquo or just ldquored stuffrdquo to distinguish it from the body of the chip the substrate which is a single crystal of silicon
We do use metal (aluminum) for interconnection wires on the surface of the chip
CMOSCOMPLEMENTARY MOS
Means we are using both N-channel and P-
channel type enhancement mode Field Effect
Transistors (FETs)
Field Effect- NO current from the controlling
electrode into the output
FET is a voltage controlled current device
BJT is a current controlled current device
NP Channel - doping of the substrate for
increased carriers (electrons or holes)
Complementary Metal Oxide
Semiconductor
PMOS
NMOS
VSS
VDD
X Xrsquo
FOUR VIEWS
Logic Transistor Layout Physical
VLSI DESIGN
The real issue inVLSI is about designing systems
on chips
The designs are complex and we need to use
structured design techniques and sophisticated
design tools to manage the complexity of the
design
We also accept the fact that any technology we
learn the details of will be out of date soon
We are trying to develop and use techniques that
will transcend the technology but still respect it
HELP FROM COMPUTER AIDED DESIGN TOOLS
Tools
Editors
Simulators
Libraries
Module Synthesis
PlaceRoute
Chip Assemblers
Silicon Compilers
Experts
Logic design
Electroniccircuit
design
Device physics
Artwork
Applications - system
design
Architectures
DESIGN STYLES
Full custom
Standard cell
Gate-array
Macro-cell
ldquoFPGArdquo
Combinations
FULL CUSTOM
Hand drawn geometry
All layers customized
Digital and analog
Simulation at transistor level (analog)
High density
High performance
Long design time
FULL CUSTOM
IN Out
Vdd
Gnd
STANDARD CELLS
Standard cells organized in rows (and or flip-flopsetc)
Cells made as full custom by vendor (not user)
All layers customized
Digital with possibility of special analog cells
Simulation at gate level (digital)
Medium density
Medium-high performance
Reasonable design time
STANDARD CELLS
Routing
Cell
IO cell
GATE-ARRAY
Predefined transistors connected via metal
Two types Channel based Channel less (sea of gates)
Only metallization layers customized
Fixed array sizes (normally 5-10 different)
Digital cells in library (and or flip-flopsetc)
Simulation at gate level (digital)
Medium density
Medium performance
Reasonable design time
GATE-ARRAY
Oxide isolation
Gate isolation
PMOS
NMOS
Vdd
Gnd
B A
Out
Vdd
Gnd
A
B
Out
Sea of gates Channel based
NAND gate using gate isolation
Can in principle be used by adjacent cell
Sea of gates
Gate-array
RAM
MACRO CELL
Predefined macro blocks (Processors RAMetc)
Macro blocks made as full custom by vendor
All layers customized
Digital and some analog (ADC)
Simulation at behavioral or gate level (digital)
High density
High performance
Short design time
Use standard on-chip busses
ldquoSystem on a chiprdquo
DSP processor
LCD
cont RAM
ROM ADC
FPGA = FIELD PROGRAMMABLE GATE ARRAY
Programmable logic blocks
Programmable connections between logic blocks
No layers customized (standard devices)
Digital only
Low - medium performance (lt50 - 100MHz)
Low - medium density (up to ~100k gates)
Programmable by SRAM EEROM Anti_fuse etc
Cheap design tools on PCrsquos
Low development cost
High device cost
HIGH PERFORMANCE DEVICES
Mixture of full custom standard cells and
macrorsquos
Full custom for special blocks Adder (data
path) etc
Macrorsquos for standard blocks RAM ROM etc
Standard cells for non critical digital blocks
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large currents
between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between
source and drain
Low power allows very high integration
First patent in the rsquo20s in USA and Germany
Not widely used until the rsquo60s or rsquo70s
MOS TRANSISTORS
Four terminal device gate source drain body
Gate ndash oxide ndash body stack looks like a capacitor
Gate and body are conductors (body is also called the substrate)
SiO2 (oxide) is a ldquogoodrdquo insulator (separates the gate from the body
Called metalndashoxidendashsemiconductor (MOS) capacitor even though gate
is mostly made of poly-crystalline silicon (polysilicon)
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
NMOS PMOS
NMOS OPERATION
Body is commonly tied to ground (0 V)
Drain is at a higher voltage than Source
When the gate is at a low voltage
P-type body is at low voltage
Source-body and drain-body ldquodiodesrdquo are OFF
No current flows transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S
NMOS OPERATION CONT
When the gate is at a high voltage Positive charge on gate of MOS capacitor
Negative charge is attracted to body under the gate
Inverts a channel under gate to ldquon-typerdquo (N-channel hence
called the NMOS) if the gate voltage is above a threshold
voltage (VT)
Now current can flow through ldquon-typerdquo silicon from source
through channel to drain transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
PMOS TRANSISTOR
Similar but doping and voltages reversed
Body tied to high voltage (VDD)
Drain is at a lower voltage than the Source
Gate low transistor ON
Gate high transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
POWER SUPPLY VOLTAGE
GND = 0 V
In 1980rsquos VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 33 25 18 15 12 10
Effective power supply voltage can be lower due
to IR drop across the power grid
HELPING FIELDS FOR IC FABRICATION
Material Engineering
Chemistry
Device Physics
Advanced Technology
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
A Brief History contd
First Planer IC built in 1961
2003
Intel Pentium 4 processor (55 million transistors)
512 Mbit DRAM (gt 05 billion transistors)
53 compound annual growth rate over 45 years
No other technology has grown so fast so long
Driven by miniaturization of transistors
Smaller is cheaper faster lower in power
Revolutionary effects on society
1970rsquos processes usually had only nMOS transistors
Inexpensive but consume power while idle
1980s-present CMOS processes for low idle power
MOS Integrated Circuits
Intel 1101 256-bit SRAM Intel 4004 4-bit Proc
Moorersquos Law
1965 Gordon Moore plotted transistor on each chip
Fit straight line on semilog scale
Transistor counts have doubled every 26 months
Integration Levels
SSI 10 gates
MSI 1000 gates
LSI 10000 gates
VLSI gt 10k gates
httpwwwintelcomtechnologysiliconmooreslaw
Corollaries
Many other factors grow exponentially
Ex clock frequency processor performance
Year
1
10
100
1000
10000
1970 1975 1980 1985 1990 1995 2000 2005
4004
8008
8080
8086
80286
Intel386
Intel486
Pentium
Pentium ProIIIII
Pentium 4
Clo
ck Speed (M
Hz)
WHY VLSI DESIGN
Money technology civilization
VLSIVERY LARGE SCALE INTEGRATION
Integration Integrated Circuits
multiple devices on one substrate
How large is Very Large SSI (small scale integration)
7400 series 10-100 transistors
MSI (medium scale)
74000 series 100-1000
LSI 1000-10000 transistors
VLSI gt 10000 transistors
ULSI
Integration Improves the Design
bull Lower parasitics higher clocking speed
bull Lower power
bull Physically small
Integration Reduces Manufacturing Costs
bull (almost) no manual assembly
bull About $1-5billionfab
bull Typical Fab 1 city block a few hundred people
bull Packaging is largest cost
bull Testing is second largest cost
bull For low volume ICs Design Cost may swamp
all manufacturing cost
Need of VLSI
bull Specifications
bull IO Goals and Objectives Function Costs
bull Architectural Description
bull VLHD Verilog Behavioral Large Blocks
bull Logic Design
bull Gates plus Registers
bull Circuit Design
bull Transistors sized for power and speed
bull Discrete Logic Technology Mapping
bull Layout
bull Size Interconnect Parasitics
Levels of Design
n+ n+
S
G D
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
WHAT IS ldquoCMOS VLSIrdquo
MOS = Metal Oxide Semiconductor (This used to mean a Metal gate over Oxide insulation)
Now we use polycrystalline silicon which is deposited on the surface of the chip as a gate We call this ldquopolyrdquo or just ldquored stuffrdquo to distinguish it from the body of the chip the substrate which is a single crystal of silicon
We do use metal (aluminum) for interconnection wires on the surface of the chip
CMOSCOMPLEMENTARY MOS
Means we are using both N-channel and P-
channel type enhancement mode Field Effect
Transistors (FETs)
Field Effect- NO current from the controlling
electrode into the output
FET is a voltage controlled current device
BJT is a current controlled current device
NP Channel - doping of the substrate for
increased carriers (electrons or holes)
Complementary Metal Oxide
Semiconductor
PMOS
NMOS
VSS
VDD
X Xrsquo
FOUR VIEWS
Logic Transistor Layout Physical
VLSI DESIGN
The real issue inVLSI is about designing systems
on chips
The designs are complex and we need to use
structured design techniques and sophisticated
design tools to manage the complexity of the
design
We also accept the fact that any technology we
learn the details of will be out of date soon
We are trying to develop and use techniques that
will transcend the technology but still respect it
HELP FROM COMPUTER AIDED DESIGN TOOLS
Tools
Editors
Simulators
Libraries
Module Synthesis
PlaceRoute
Chip Assemblers
Silicon Compilers
Experts
Logic design
Electroniccircuit
design
Device physics
Artwork
Applications - system
design
Architectures
DESIGN STYLES
Full custom
Standard cell
Gate-array
Macro-cell
ldquoFPGArdquo
Combinations
FULL CUSTOM
Hand drawn geometry
All layers customized
Digital and analog
Simulation at transistor level (analog)
High density
High performance
Long design time
FULL CUSTOM
IN Out
Vdd
Gnd
STANDARD CELLS
Standard cells organized in rows (and or flip-flopsetc)
Cells made as full custom by vendor (not user)
All layers customized
Digital with possibility of special analog cells
Simulation at gate level (digital)
Medium density
Medium-high performance
Reasonable design time
STANDARD CELLS
Routing
Cell
IO cell
GATE-ARRAY
Predefined transistors connected via metal
Two types Channel based Channel less (sea of gates)
Only metallization layers customized
Fixed array sizes (normally 5-10 different)
Digital cells in library (and or flip-flopsetc)
Simulation at gate level (digital)
Medium density
Medium performance
Reasonable design time
GATE-ARRAY
Oxide isolation
Gate isolation
PMOS
NMOS
Vdd
Gnd
B A
Out
Vdd
Gnd
A
B
Out
Sea of gates Channel based
NAND gate using gate isolation
Can in principle be used by adjacent cell
Sea of gates
Gate-array
RAM
MACRO CELL
Predefined macro blocks (Processors RAMetc)
Macro blocks made as full custom by vendor
All layers customized
Digital and some analog (ADC)
Simulation at behavioral or gate level (digital)
High density
High performance
Short design time
Use standard on-chip busses
ldquoSystem on a chiprdquo
DSP processor
LCD
cont RAM
ROM ADC
FPGA = FIELD PROGRAMMABLE GATE ARRAY
Programmable logic blocks
Programmable connections between logic blocks
No layers customized (standard devices)
Digital only
Low - medium performance (lt50 - 100MHz)
Low - medium density (up to ~100k gates)
Programmable by SRAM EEROM Anti_fuse etc
Cheap design tools on PCrsquos
Low development cost
High device cost
HIGH PERFORMANCE DEVICES
Mixture of full custom standard cells and
macrorsquos
Full custom for special blocks Adder (data
path) etc
Macrorsquos for standard blocks RAM ROM etc
Standard cells for non critical digital blocks
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large currents
between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between
source and drain
Low power allows very high integration
First patent in the rsquo20s in USA and Germany
Not widely used until the rsquo60s or rsquo70s
MOS TRANSISTORS
Four terminal device gate source drain body
Gate ndash oxide ndash body stack looks like a capacitor
Gate and body are conductors (body is also called the substrate)
SiO2 (oxide) is a ldquogoodrdquo insulator (separates the gate from the body
Called metalndashoxidendashsemiconductor (MOS) capacitor even though gate
is mostly made of poly-crystalline silicon (polysilicon)
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
NMOS PMOS
NMOS OPERATION
Body is commonly tied to ground (0 V)
Drain is at a higher voltage than Source
When the gate is at a low voltage
P-type body is at low voltage
Source-body and drain-body ldquodiodesrdquo are OFF
No current flows transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S
NMOS OPERATION CONT
When the gate is at a high voltage Positive charge on gate of MOS capacitor
Negative charge is attracted to body under the gate
Inverts a channel under gate to ldquon-typerdquo (N-channel hence
called the NMOS) if the gate voltage is above a threshold
voltage (VT)
Now current can flow through ldquon-typerdquo silicon from source
through channel to drain transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
PMOS TRANSISTOR
Similar but doping and voltages reversed
Body tied to high voltage (VDD)
Drain is at a lower voltage than the Source
Gate low transistor ON
Gate high transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
POWER SUPPLY VOLTAGE
GND = 0 V
In 1980rsquos VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 33 25 18 15 12 10
Effective power supply voltage can be lower due
to IR drop across the power grid
HELPING FIELDS FOR IC FABRICATION
Material Engineering
Chemistry
Device Physics
Advanced Technology
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
1970rsquos processes usually had only nMOS transistors
Inexpensive but consume power while idle
1980s-present CMOS processes for low idle power
MOS Integrated Circuits
Intel 1101 256-bit SRAM Intel 4004 4-bit Proc
Moorersquos Law
1965 Gordon Moore plotted transistor on each chip
Fit straight line on semilog scale
Transistor counts have doubled every 26 months
Integration Levels
SSI 10 gates
MSI 1000 gates
LSI 10000 gates
VLSI gt 10k gates
httpwwwintelcomtechnologysiliconmooreslaw
Corollaries
Many other factors grow exponentially
Ex clock frequency processor performance
Year
1
10
100
1000
10000
1970 1975 1980 1985 1990 1995 2000 2005
4004
8008
8080
8086
80286
Intel386
Intel486
Pentium
Pentium ProIIIII
Pentium 4
Clo
ck Speed (M
Hz)
WHY VLSI DESIGN
Money technology civilization
VLSIVERY LARGE SCALE INTEGRATION
Integration Integrated Circuits
multiple devices on one substrate
How large is Very Large SSI (small scale integration)
7400 series 10-100 transistors
MSI (medium scale)
74000 series 100-1000
LSI 1000-10000 transistors
VLSI gt 10000 transistors
ULSI
Integration Improves the Design
bull Lower parasitics higher clocking speed
bull Lower power
bull Physically small
Integration Reduces Manufacturing Costs
bull (almost) no manual assembly
bull About $1-5billionfab
bull Typical Fab 1 city block a few hundred people
bull Packaging is largest cost
bull Testing is second largest cost
bull For low volume ICs Design Cost may swamp
all manufacturing cost
Need of VLSI
bull Specifications
bull IO Goals and Objectives Function Costs
bull Architectural Description
bull VLHD Verilog Behavioral Large Blocks
bull Logic Design
bull Gates plus Registers
bull Circuit Design
bull Transistors sized for power and speed
bull Discrete Logic Technology Mapping
bull Layout
bull Size Interconnect Parasitics
Levels of Design
n+ n+
S
G D
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
WHAT IS ldquoCMOS VLSIrdquo
MOS = Metal Oxide Semiconductor (This used to mean a Metal gate over Oxide insulation)
Now we use polycrystalline silicon which is deposited on the surface of the chip as a gate We call this ldquopolyrdquo or just ldquored stuffrdquo to distinguish it from the body of the chip the substrate which is a single crystal of silicon
We do use metal (aluminum) for interconnection wires on the surface of the chip
CMOSCOMPLEMENTARY MOS
Means we are using both N-channel and P-
channel type enhancement mode Field Effect
Transistors (FETs)
Field Effect- NO current from the controlling
electrode into the output
FET is a voltage controlled current device
BJT is a current controlled current device
NP Channel - doping of the substrate for
increased carriers (electrons or holes)
Complementary Metal Oxide
Semiconductor
PMOS
NMOS
VSS
VDD
X Xrsquo
FOUR VIEWS
Logic Transistor Layout Physical
VLSI DESIGN
The real issue inVLSI is about designing systems
on chips
The designs are complex and we need to use
structured design techniques and sophisticated
design tools to manage the complexity of the
design
We also accept the fact that any technology we
learn the details of will be out of date soon
We are trying to develop and use techniques that
will transcend the technology but still respect it
HELP FROM COMPUTER AIDED DESIGN TOOLS
Tools
Editors
Simulators
Libraries
Module Synthesis
PlaceRoute
Chip Assemblers
Silicon Compilers
Experts
Logic design
Electroniccircuit
design
Device physics
Artwork
Applications - system
design
Architectures
DESIGN STYLES
Full custom
Standard cell
Gate-array
Macro-cell
ldquoFPGArdquo
Combinations
FULL CUSTOM
Hand drawn geometry
All layers customized
Digital and analog
Simulation at transistor level (analog)
High density
High performance
Long design time
FULL CUSTOM
IN Out
Vdd
Gnd
STANDARD CELLS
Standard cells organized in rows (and or flip-flopsetc)
Cells made as full custom by vendor (not user)
All layers customized
Digital with possibility of special analog cells
Simulation at gate level (digital)
Medium density
Medium-high performance
Reasonable design time
STANDARD CELLS
Routing
Cell
IO cell
GATE-ARRAY
Predefined transistors connected via metal
Two types Channel based Channel less (sea of gates)
Only metallization layers customized
Fixed array sizes (normally 5-10 different)
Digital cells in library (and or flip-flopsetc)
Simulation at gate level (digital)
Medium density
Medium performance
Reasonable design time
GATE-ARRAY
Oxide isolation
Gate isolation
PMOS
NMOS
Vdd
Gnd
B A
Out
Vdd
Gnd
A
B
Out
Sea of gates Channel based
NAND gate using gate isolation
Can in principle be used by adjacent cell
Sea of gates
Gate-array
RAM
MACRO CELL
Predefined macro blocks (Processors RAMetc)
Macro blocks made as full custom by vendor
All layers customized
Digital and some analog (ADC)
Simulation at behavioral or gate level (digital)
High density
High performance
Short design time
Use standard on-chip busses
ldquoSystem on a chiprdquo
DSP processor
LCD
cont RAM
ROM ADC
FPGA = FIELD PROGRAMMABLE GATE ARRAY
Programmable logic blocks
Programmable connections between logic blocks
No layers customized (standard devices)
Digital only
Low - medium performance (lt50 - 100MHz)
Low - medium density (up to ~100k gates)
Programmable by SRAM EEROM Anti_fuse etc
Cheap design tools on PCrsquos
Low development cost
High device cost
HIGH PERFORMANCE DEVICES
Mixture of full custom standard cells and
macrorsquos
Full custom for special blocks Adder (data
path) etc
Macrorsquos for standard blocks RAM ROM etc
Standard cells for non critical digital blocks
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large currents
between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between
source and drain
Low power allows very high integration
First patent in the rsquo20s in USA and Germany
Not widely used until the rsquo60s or rsquo70s
MOS TRANSISTORS
Four terminal device gate source drain body
Gate ndash oxide ndash body stack looks like a capacitor
Gate and body are conductors (body is also called the substrate)
SiO2 (oxide) is a ldquogoodrdquo insulator (separates the gate from the body
Called metalndashoxidendashsemiconductor (MOS) capacitor even though gate
is mostly made of poly-crystalline silicon (polysilicon)
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
NMOS PMOS
NMOS OPERATION
Body is commonly tied to ground (0 V)
Drain is at a higher voltage than Source
When the gate is at a low voltage
P-type body is at low voltage
Source-body and drain-body ldquodiodesrdquo are OFF
No current flows transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S
NMOS OPERATION CONT
When the gate is at a high voltage Positive charge on gate of MOS capacitor
Negative charge is attracted to body under the gate
Inverts a channel under gate to ldquon-typerdquo (N-channel hence
called the NMOS) if the gate voltage is above a threshold
voltage (VT)
Now current can flow through ldquon-typerdquo silicon from source
through channel to drain transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
PMOS TRANSISTOR
Similar but doping and voltages reversed
Body tied to high voltage (VDD)
Drain is at a lower voltage than the Source
Gate low transistor ON
Gate high transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
POWER SUPPLY VOLTAGE
GND = 0 V
In 1980rsquos VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 33 25 18 15 12 10
Effective power supply voltage can be lower due
to IR drop across the power grid
HELPING FIELDS FOR IC FABRICATION
Material Engineering
Chemistry
Device Physics
Advanced Technology
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
Moorersquos Law
1965 Gordon Moore plotted transistor on each chip
Fit straight line on semilog scale
Transistor counts have doubled every 26 months
Integration Levels
SSI 10 gates
MSI 1000 gates
LSI 10000 gates
VLSI gt 10k gates
httpwwwintelcomtechnologysiliconmooreslaw
Corollaries
Many other factors grow exponentially
Ex clock frequency processor performance
Year
1
10
100
1000
10000
1970 1975 1980 1985 1990 1995 2000 2005
4004
8008
8080
8086
80286
Intel386
Intel486
Pentium
Pentium ProIIIII
Pentium 4
Clo
ck Speed (M
Hz)
WHY VLSI DESIGN
Money technology civilization
VLSIVERY LARGE SCALE INTEGRATION
Integration Integrated Circuits
multiple devices on one substrate
How large is Very Large SSI (small scale integration)
7400 series 10-100 transistors
MSI (medium scale)
74000 series 100-1000
LSI 1000-10000 transistors
VLSI gt 10000 transistors
ULSI
Integration Improves the Design
bull Lower parasitics higher clocking speed
bull Lower power
bull Physically small
Integration Reduces Manufacturing Costs
bull (almost) no manual assembly
bull About $1-5billionfab
bull Typical Fab 1 city block a few hundred people
bull Packaging is largest cost
bull Testing is second largest cost
bull For low volume ICs Design Cost may swamp
all manufacturing cost
Need of VLSI
bull Specifications
bull IO Goals and Objectives Function Costs
bull Architectural Description
bull VLHD Verilog Behavioral Large Blocks
bull Logic Design
bull Gates plus Registers
bull Circuit Design
bull Transistors sized for power and speed
bull Discrete Logic Technology Mapping
bull Layout
bull Size Interconnect Parasitics
Levels of Design
n+ n+
S
G D
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
WHAT IS ldquoCMOS VLSIrdquo
MOS = Metal Oxide Semiconductor (This used to mean a Metal gate over Oxide insulation)
Now we use polycrystalline silicon which is deposited on the surface of the chip as a gate We call this ldquopolyrdquo or just ldquored stuffrdquo to distinguish it from the body of the chip the substrate which is a single crystal of silicon
We do use metal (aluminum) for interconnection wires on the surface of the chip
CMOSCOMPLEMENTARY MOS
Means we are using both N-channel and P-
channel type enhancement mode Field Effect
Transistors (FETs)
Field Effect- NO current from the controlling
electrode into the output
FET is a voltage controlled current device
BJT is a current controlled current device
NP Channel - doping of the substrate for
increased carriers (electrons or holes)
Complementary Metal Oxide
Semiconductor
PMOS
NMOS
VSS
VDD
X Xrsquo
FOUR VIEWS
Logic Transistor Layout Physical
VLSI DESIGN
The real issue inVLSI is about designing systems
on chips
The designs are complex and we need to use
structured design techniques and sophisticated
design tools to manage the complexity of the
design
We also accept the fact that any technology we
learn the details of will be out of date soon
We are trying to develop and use techniques that
will transcend the technology but still respect it
HELP FROM COMPUTER AIDED DESIGN TOOLS
Tools
Editors
Simulators
Libraries
Module Synthesis
PlaceRoute
Chip Assemblers
Silicon Compilers
Experts
Logic design
Electroniccircuit
design
Device physics
Artwork
Applications - system
design
Architectures
DESIGN STYLES
Full custom
Standard cell
Gate-array
Macro-cell
ldquoFPGArdquo
Combinations
FULL CUSTOM
Hand drawn geometry
All layers customized
Digital and analog
Simulation at transistor level (analog)
High density
High performance
Long design time
FULL CUSTOM
IN Out
Vdd
Gnd
STANDARD CELLS
Standard cells organized in rows (and or flip-flopsetc)
Cells made as full custom by vendor (not user)
All layers customized
Digital with possibility of special analog cells
Simulation at gate level (digital)
Medium density
Medium-high performance
Reasonable design time
STANDARD CELLS
Routing
Cell
IO cell
GATE-ARRAY
Predefined transistors connected via metal
Two types Channel based Channel less (sea of gates)
Only metallization layers customized
Fixed array sizes (normally 5-10 different)
Digital cells in library (and or flip-flopsetc)
Simulation at gate level (digital)
Medium density
Medium performance
Reasonable design time
GATE-ARRAY
Oxide isolation
Gate isolation
PMOS
NMOS
Vdd
Gnd
B A
Out
Vdd
Gnd
A
B
Out
Sea of gates Channel based
NAND gate using gate isolation
Can in principle be used by adjacent cell
Sea of gates
Gate-array
RAM
MACRO CELL
Predefined macro blocks (Processors RAMetc)
Macro blocks made as full custom by vendor
All layers customized
Digital and some analog (ADC)
Simulation at behavioral or gate level (digital)
High density
High performance
Short design time
Use standard on-chip busses
ldquoSystem on a chiprdquo
DSP processor
LCD
cont RAM
ROM ADC
FPGA = FIELD PROGRAMMABLE GATE ARRAY
Programmable logic blocks
Programmable connections between logic blocks
No layers customized (standard devices)
Digital only
Low - medium performance (lt50 - 100MHz)
Low - medium density (up to ~100k gates)
Programmable by SRAM EEROM Anti_fuse etc
Cheap design tools on PCrsquos
Low development cost
High device cost
HIGH PERFORMANCE DEVICES
Mixture of full custom standard cells and
macrorsquos
Full custom for special blocks Adder (data
path) etc
Macrorsquos for standard blocks RAM ROM etc
Standard cells for non critical digital blocks
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large currents
between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between
source and drain
Low power allows very high integration
First patent in the rsquo20s in USA and Germany
Not widely used until the rsquo60s or rsquo70s
MOS TRANSISTORS
Four terminal device gate source drain body
Gate ndash oxide ndash body stack looks like a capacitor
Gate and body are conductors (body is also called the substrate)
SiO2 (oxide) is a ldquogoodrdquo insulator (separates the gate from the body
Called metalndashoxidendashsemiconductor (MOS) capacitor even though gate
is mostly made of poly-crystalline silicon (polysilicon)
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
NMOS PMOS
NMOS OPERATION
Body is commonly tied to ground (0 V)
Drain is at a higher voltage than Source
When the gate is at a low voltage
P-type body is at low voltage
Source-body and drain-body ldquodiodesrdquo are OFF
No current flows transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S
NMOS OPERATION CONT
When the gate is at a high voltage Positive charge on gate of MOS capacitor
Negative charge is attracted to body under the gate
Inverts a channel under gate to ldquon-typerdquo (N-channel hence
called the NMOS) if the gate voltage is above a threshold
voltage (VT)
Now current can flow through ldquon-typerdquo silicon from source
through channel to drain transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
PMOS TRANSISTOR
Similar but doping and voltages reversed
Body tied to high voltage (VDD)
Drain is at a lower voltage than the Source
Gate low transistor ON
Gate high transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
POWER SUPPLY VOLTAGE
GND = 0 V
In 1980rsquos VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 33 25 18 15 12 10
Effective power supply voltage can be lower due
to IR drop across the power grid
HELPING FIELDS FOR IC FABRICATION
Material Engineering
Chemistry
Device Physics
Advanced Technology
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
Corollaries
Many other factors grow exponentially
Ex clock frequency processor performance
Year
1
10
100
1000
10000
1970 1975 1980 1985 1990 1995 2000 2005
4004
8008
8080
8086
80286
Intel386
Intel486
Pentium
Pentium ProIIIII
Pentium 4
Clo
ck Speed (M
Hz)
WHY VLSI DESIGN
Money technology civilization
VLSIVERY LARGE SCALE INTEGRATION
Integration Integrated Circuits
multiple devices on one substrate
How large is Very Large SSI (small scale integration)
7400 series 10-100 transistors
MSI (medium scale)
74000 series 100-1000
LSI 1000-10000 transistors
VLSI gt 10000 transistors
ULSI
Integration Improves the Design
bull Lower parasitics higher clocking speed
bull Lower power
bull Physically small
Integration Reduces Manufacturing Costs
bull (almost) no manual assembly
bull About $1-5billionfab
bull Typical Fab 1 city block a few hundred people
bull Packaging is largest cost
bull Testing is second largest cost
bull For low volume ICs Design Cost may swamp
all manufacturing cost
Need of VLSI
bull Specifications
bull IO Goals and Objectives Function Costs
bull Architectural Description
bull VLHD Verilog Behavioral Large Blocks
bull Logic Design
bull Gates plus Registers
bull Circuit Design
bull Transistors sized for power and speed
bull Discrete Logic Technology Mapping
bull Layout
bull Size Interconnect Parasitics
Levels of Design
n+ n+
S
G D
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
WHAT IS ldquoCMOS VLSIrdquo
MOS = Metal Oxide Semiconductor (This used to mean a Metal gate over Oxide insulation)
Now we use polycrystalline silicon which is deposited on the surface of the chip as a gate We call this ldquopolyrdquo or just ldquored stuffrdquo to distinguish it from the body of the chip the substrate which is a single crystal of silicon
We do use metal (aluminum) for interconnection wires on the surface of the chip
CMOSCOMPLEMENTARY MOS
Means we are using both N-channel and P-
channel type enhancement mode Field Effect
Transistors (FETs)
Field Effect- NO current from the controlling
electrode into the output
FET is a voltage controlled current device
BJT is a current controlled current device
NP Channel - doping of the substrate for
increased carriers (electrons or holes)
Complementary Metal Oxide
Semiconductor
PMOS
NMOS
VSS
VDD
X Xrsquo
FOUR VIEWS
Logic Transistor Layout Physical
VLSI DESIGN
The real issue inVLSI is about designing systems
on chips
The designs are complex and we need to use
structured design techniques and sophisticated
design tools to manage the complexity of the
design
We also accept the fact that any technology we
learn the details of will be out of date soon
We are trying to develop and use techniques that
will transcend the technology but still respect it
HELP FROM COMPUTER AIDED DESIGN TOOLS
Tools
Editors
Simulators
Libraries
Module Synthesis
PlaceRoute
Chip Assemblers
Silicon Compilers
Experts
Logic design
Electroniccircuit
design
Device physics
Artwork
Applications - system
design
Architectures
DESIGN STYLES
Full custom
Standard cell
Gate-array
Macro-cell
ldquoFPGArdquo
Combinations
FULL CUSTOM
Hand drawn geometry
All layers customized
Digital and analog
Simulation at transistor level (analog)
High density
High performance
Long design time
FULL CUSTOM
IN Out
Vdd
Gnd
STANDARD CELLS
Standard cells organized in rows (and or flip-flopsetc)
Cells made as full custom by vendor (not user)
All layers customized
Digital with possibility of special analog cells
Simulation at gate level (digital)
Medium density
Medium-high performance
Reasonable design time
STANDARD CELLS
Routing
Cell
IO cell
GATE-ARRAY
Predefined transistors connected via metal
Two types Channel based Channel less (sea of gates)
Only metallization layers customized
Fixed array sizes (normally 5-10 different)
Digital cells in library (and or flip-flopsetc)
Simulation at gate level (digital)
Medium density
Medium performance
Reasonable design time
GATE-ARRAY
Oxide isolation
Gate isolation
PMOS
NMOS
Vdd
Gnd
B A
Out
Vdd
Gnd
A
B
Out
Sea of gates Channel based
NAND gate using gate isolation
Can in principle be used by adjacent cell
Sea of gates
Gate-array
RAM
MACRO CELL
Predefined macro blocks (Processors RAMetc)
Macro blocks made as full custom by vendor
All layers customized
Digital and some analog (ADC)
Simulation at behavioral or gate level (digital)
High density
High performance
Short design time
Use standard on-chip busses
ldquoSystem on a chiprdquo
DSP processor
LCD
cont RAM
ROM ADC
FPGA = FIELD PROGRAMMABLE GATE ARRAY
Programmable logic blocks
Programmable connections between logic blocks
No layers customized (standard devices)
Digital only
Low - medium performance (lt50 - 100MHz)
Low - medium density (up to ~100k gates)
Programmable by SRAM EEROM Anti_fuse etc
Cheap design tools on PCrsquos
Low development cost
High device cost
HIGH PERFORMANCE DEVICES
Mixture of full custom standard cells and
macrorsquos
Full custom for special blocks Adder (data
path) etc
Macrorsquos for standard blocks RAM ROM etc
Standard cells for non critical digital blocks
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large currents
between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between
source and drain
Low power allows very high integration
First patent in the rsquo20s in USA and Germany
Not widely used until the rsquo60s or rsquo70s
MOS TRANSISTORS
Four terminal device gate source drain body
Gate ndash oxide ndash body stack looks like a capacitor
Gate and body are conductors (body is also called the substrate)
SiO2 (oxide) is a ldquogoodrdquo insulator (separates the gate from the body
Called metalndashoxidendashsemiconductor (MOS) capacitor even though gate
is mostly made of poly-crystalline silicon (polysilicon)
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
NMOS PMOS
NMOS OPERATION
Body is commonly tied to ground (0 V)
Drain is at a higher voltage than Source
When the gate is at a low voltage
P-type body is at low voltage
Source-body and drain-body ldquodiodesrdquo are OFF
No current flows transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S
NMOS OPERATION CONT
When the gate is at a high voltage Positive charge on gate of MOS capacitor
Negative charge is attracted to body under the gate
Inverts a channel under gate to ldquon-typerdquo (N-channel hence
called the NMOS) if the gate voltage is above a threshold
voltage (VT)
Now current can flow through ldquon-typerdquo silicon from source
through channel to drain transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
PMOS TRANSISTOR
Similar but doping and voltages reversed
Body tied to high voltage (VDD)
Drain is at a lower voltage than the Source
Gate low transistor ON
Gate high transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
POWER SUPPLY VOLTAGE
GND = 0 V
In 1980rsquos VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 33 25 18 15 12 10
Effective power supply voltage can be lower due
to IR drop across the power grid
HELPING FIELDS FOR IC FABRICATION
Material Engineering
Chemistry
Device Physics
Advanced Technology
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
WHY VLSI DESIGN
Money technology civilization
VLSIVERY LARGE SCALE INTEGRATION
Integration Integrated Circuits
multiple devices on one substrate
How large is Very Large SSI (small scale integration)
7400 series 10-100 transistors
MSI (medium scale)
74000 series 100-1000
LSI 1000-10000 transistors
VLSI gt 10000 transistors
ULSI
Integration Improves the Design
bull Lower parasitics higher clocking speed
bull Lower power
bull Physically small
Integration Reduces Manufacturing Costs
bull (almost) no manual assembly
bull About $1-5billionfab
bull Typical Fab 1 city block a few hundred people
bull Packaging is largest cost
bull Testing is second largest cost
bull For low volume ICs Design Cost may swamp
all manufacturing cost
Need of VLSI
bull Specifications
bull IO Goals and Objectives Function Costs
bull Architectural Description
bull VLHD Verilog Behavioral Large Blocks
bull Logic Design
bull Gates plus Registers
bull Circuit Design
bull Transistors sized for power and speed
bull Discrete Logic Technology Mapping
bull Layout
bull Size Interconnect Parasitics
Levels of Design
n+ n+
S
G D
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
WHAT IS ldquoCMOS VLSIrdquo
MOS = Metal Oxide Semiconductor (This used to mean a Metal gate over Oxide insulation)
Now we use polycrystalline silicon which is deposited on the surface of the chip as a gate We call this ldquopolyrdquo or just ldquored stuffrdquo to distinguish it from the body of the chip the substrate which is a single crystal of silicon
We do use metal (aluminum) for interconnection wires on the surface of the chip
CMOSCOMPLEMENTARY MOS
Means we are using both N-channel and P-
channel type enhancement mode Field Effect
Transistors (FETs)
Field Effect- NO current from the controlling
electrode into the output
FET is a voltage controlled current device
BJT is a current controlled current device
NP Channel - doping of the substrate for
increased carriers (electrons or holes)
Complementary Metal Oxide
Semiconductor
PMOS
NMOS
VSS
VDD
X Xrsquo
FOUR VIEWS
Logic Transistor Layout Physical
VLSI DESIGN
The real issue inVLSI is about designing systems
on chips
The designs are complex and we need to use
structured design techniques and sophisticated
design tools to manage the complexity of the
design
We also accept the fact that any technology we
learn the details of will be out of date soon
We are trying to develop and use techniques that
will transcend the technology but still respect it
HELP FROM COMPUTER AIDED DESIGN TOOLS
Tools
Editors
Simulators
Libraries
Module Synthesis
PlaceRoute
Chip Assemblers
Silicon Compilers
Experts
Logic design
Electroniccircuit
design
Device physics
Artwork
Applications - system
design
Architectures
DESIGN STYLES
Full custom
Standard cell
Gate-array
Macro-cell
ldquoFPGArdquo
Combinations
FULL CUSTOM
Hand drawn geometry
All layers customized
Digital and analog
Simulation at transistor level (analog)
High density
High performance
Long design time
FULL CUSTOM
IN Out
Vdd
Gnd
STANDARD CELLS
Standard cells organized in rows (and or flip-flopsetc)
Cells made as full custom by vendor (not user)
All layers customized
Digital with possibility of special analog cells
Simulation at gate level (digital)
Medium density
Medium-high performance
Reasonable design time
STANDARD CELLS
Routing
Cell
IO cell
GATE-ARRAY
Predefined transistors connected via metal
Two types Channel based Channel less (sea of gates)
Only metallization layers customized
Fixed array sizes (normally 5-10 different)
Digital cells in library (and or flip-flopsetc)
Simulation at gate level (digital)
Medium density
Medium performance
Reasonable design time
GATE-ARRAY
Oxide isolation
Gate isolation
PMOS
NMOS
Vdd
Gnd
B A
Out
Vdd
Gnd
A
B
Out
Sea of gates Channel based
NAND gate using gate isolation
Can in principle be used by adjacent cell
Sea of gates
Gate-array
RAM
MACRO CELL
Predefined macro blocks (Processors RAMetc)
Macro blocks made as full custom by vendor
All layers customized
Digital and some analog (ADC)
Simulation at behavioral or gate level (digital)
High density
High performance
Short design time
Use standard on-chip busses
ldquoSystem on a chiprdquo
DSP processor
LCD
cont RAM
ROM ADC
FPGA = FIELD PROGRAMMABLE GATE ARRAY
Programmable logic blocks
Programmable connections between logic blocks
No layers customized (standard devices)
Digital only
Low - medium performance (lt50 - 100MHz)
Low - medium density (up to ~100k gates)
Programmable by SRAM EEROM Anti_fuse etc
Cheap design tools on PCrsquos
Low development cost
High device cost
HIGH PERFORMANCE DEVICES
Mixture of full custom standard cells and
macrorsquos
Full custom for special blocks Adder (data
path) etc
Macrorsquos for standard blocks RAM ROM etc
Standard cells for non critical digital blocks
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large currents
between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between
source and drain
Low power allows very high integration
First patent in the rsquo20s in USA and Germany
Not widely used until the rsquo60s or rsquo70s
MOS TRANSISTORS
Four terminal device gate source drain body
Gate ndash oxide ndash body stack looks like a capacitor
Gate and body are conductors (body is also called the substrate)
SiO2 (oxide) is a ldquogoodrdquo insulator (separates the gate from the body
Called metalndashoxidendashsemiconductor (MOS) capacitor even though gate
is mostly made of poly-crystalline silicon (polysilicon)
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
NMOS PMOS
NMOS OPERATION
Body is commonly tied to ground (0 V)
Drain is at a higher voltage than Source
When the gate is at a low voltage
P-type body is at low voltage
Source-body and drain-body ldquodiodesrdquo are OFF
No current flows transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S
NMOS OPERATION CONT
When the gate is at a high voltage Positive charge on gate of MOS capacitor
Negative charge is attracted to body under the gate
Inverts a channel under gate to ldquon-typerdquo (N-channel hence
called the NMOS) if the gate voltage is above a threshold
voltage (VT)
Now current can flow through ldquon-typerdquo silicon from source
through channel to drain transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
PMOS TRANSISTOR
Similar but doping and voltages reversed
Body tied to high voltage (VDD)
Drain is at a lower voltage than the Source
Gate low transistor ON
Gate high transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
POWER SUPPLY VOLTAGE
GND = 0 V
In 1980rsquos VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 33 25 18 15 12 10
Effective power supply voltage can be lower due
to IR drop across the power grid
HELPING FIELDS FOR IC FABRICATION
Material Engineering
Chemistry
Device Physics
Advanced Technology
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
VLSIVERY LARGE SCALE INTEGRATION
Integration Integrated Circuits
multiple devices on one substrate
How large is Very Large SSI (small scale integration)
7400 series 10-100 transistors
MSI (medium scale)
74000 series 100-1000
LSI 1000-10000 transistors
VLSI gt 10000 transistors
ULSI
Integration Improves the Design
bull Lower parasitics higher clocking speed
bull Lower power
bull Physically small
Integration Reduces Manufacturing Costs
bull (almost) no manual assembly
bull About $1-5billionfab
bull Typical Fab 1 city block a few hundred people
bull Packaging is largest cost
bull Testing is second largest cost
bull For low volume ICs Design Cost may swamp
all manufacturing cost
Need of VLSI
bull Specifications
bull IO Goals and Objectives Function Costs
bull Architectural Description
bull VLHD Verilog Behavioral Large Blocks
bull Logic Design
bull Gates plus Registers
bull Circuit Design
bull Transistors sized for power and speed
bull Discrete Logic Technology Mapping
bull Layout
bull Size Interconnect Parasitics
Levels of Design
n+ n+
S
G D
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
WHAT IS ldquoCMOS VLSIrdquo
MOS = Metal Oxide Semiconductor (This used to mean a Metal gate over Oxide insulation)
Now we use polycrystalline silicon which is deposited on the surface of the chip as a gate We call this ldquopolyrdquo or just ldquored stuffrdquo to distinguish it from the body of the chip the substrate which is a single crystal of silicon
We do use metal (aluminum) for interconnection wires on the surface of the chip
CMOSCOMPLEMENTARY MOS
Means we are using both N-channel and P-
channel type enhancement mode Field Effect
Transistors (FETs)
Field Effect- NO current from the controlling
electrode into the output
FET is a voltage controlled current device
BJT is a current controlled current device
NP Channel - doping of the substrate for
increased carriers (electrons or holes)
Complementary Metal Oxide
Semiconductor
PMOS
NMOS
VSS
VDD
X Xrsquo
FOUR VIEWS
Logic Transistor Layout Physical
VLSI DESIGN
The real issue inVLSI is about designing systems
on chips
The designs are complex and we need to use
structured design techniques and sophisticated
design tools to manage the complexity of the
design
We also accept the fact that any technology we
learn the details of will be out of date soon
We are trying to develop and use techniques that
will transcend the technology but still respect it
HELP FROM COMPUTER AIDED DESIGN TOOLS
Tools
Editors
Simulators
Libraries
Module Synthesis
PlaceRoute
Chip Assemblers
Silicon Compilers
Experts
Logic design
Electroniccircuit
design
Device physics
Artwork
Applications - system
design
Architectures
DESIGN STYLES
Full custom
Standard cell
Gate-array
Macro-cell
ldquoFPGArdquo
Combinations
FULL CUSTOM
Hand drawn geometry
All layers customized
Digital and analog
Simulation at transistor level (analog)
High density
High performance
Long design time
FULL CUSTOM
IN Out
Vdd
Gnd
STANDARD CELLS
Standard cells organized in rows (and or flip-flopsetc)
Cells made as full custom by vendor (not user)
All layers customized
Digital with possibility of special analog cells
Simulation at gate level (digital)
Medium density
Medium-high performance
Reasonable design time
STANDARD CELLS
Routing
Cell
IO cell
GATE-ARRAY
Predefined transistors connected via metal
Two types Channel based Channel less (sea of gates)
Only metallization layers customized
Fixed array sizes (normally 5-10 different)
Digital cells in library (and or flip-flopsetc)
Simulation at gate level (digital)
Medium density
Medium performance
Reasonable design time
GATE-ARRAY
Oxide isolation
Gate isolation
PMOS
NMOS
Vdd
Gnd
B A
Out
Vdd
Gnd
A
B
Out
Sea of gates Channel based
NAND gate using gate isolation
Can in principle be used by adjacent cell
Sea of gates
Gate-array
RAM
MACRO CELL
Predefined macro blocks (Processors RAMetc)
Macro blocks made as full custom by vendor
All layers customized
Digital and some analog (ADC)
Simulation at behavioral or gate level (digital)
High density
High performance
Short design time
Use standard on-chip busses
ldquoSystem on a chiprdquo
DSP processor
LCD
cont RAM
ROM ADC
FPGA = FIELD PROGRAMMABLE GATE ARRAY
Programmable logic blocks
Programmable connections between logic blocks
No layers customized (standard devices)
Digital only
Low - medium performance (lt50 - 100MHz)
Low - medium density (up to ~100k gates)
Programmable by SRAM EEROM Anti_fuse etc
Cheap design tools on PCrsquos
Low development cost
High device cost
HIGH PERFORMANCE DEVICES
Mixture of full custom standard cells and
macrorsquos
Full custom for special blocks Adder (data
path) etc
Macrorsquos for standard blocks RAM ROM etc
Standard cells for non critical digital blocks
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large currents
between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between
source and drain
Low power allows very high integration
First patent in the rsquo20s in USA and Germany
Not widely used until the rsquo60s or rsquo70s
MOS TRANSISTORS
Four terminal device gate source drain body
Gate ndash oxide ndash body stack looks like a capacitor
Gate and body are conductors (body is also called the substrate)
SiO2 (oxide) is a ldquogoodrdquo insulator (separates the gate from the body
Called metalndashoxidendashsemiconductor (MOS) capacitor even though gate
is mostly made of poly-crystalline silicon (polysilicon)
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
NMOS PMOS
NMOS OPERATION
Body is commonly tied to ground (0 V)
Drain is at a higher voltage than Source
When the gate is at a low voltage
P-type body is at low voltage
Source-body and drain-body ldquodiodesrdquo are OFF
No current flows transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S
NMOS OPERATION CONT
When the gate is at a high voltage Positive charge on gate of MOS capacitor
Negative charge is attracted to body under the gate
Inverts a channel under gate to ldquon-typerdquo (N-channel hence
called the NMOS) if the gate voltage is above a threshold
voltage (VT)
Now current can flow through ldquon-typerdquo silicon from source
through channel to drain transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
PMOS TRANSISTOR
Similar but doping and voltages reversed
Body tied to high voltage (VDD)
Drain is at a lower voltage than the Source
Gate low transistor ON
Gate high transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
POWER SUPPLY VOLTAGE
GND = 0 V
In 1980rsquos VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 33 25 18 15 12 10
Effective power supply voltage can be lower due
to IR drop across the power grid
HELPING FIELDS FOR IC FABRICATION
Material Engineering
Chemistry
Device Physics
Advanced Technology
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
Integration Improves the Design
bull Lower parasitics higher clocking speed
bull Lower power
bull Physically small
Integration Reduces Manufacturing Costs
bull (almost) no manual assembly
bull About $1-5billionfab
bull Typical Fab 1 city block a few hundred people
bull Packaging is largest cost
bull Testing is second largest cost
bull For low volume ICs Design Cost may swamp
all manufacturing cost
Need of VLSI
bull Specifications
bull IO Goals and Objectives Function Costs
bull Architectural Description
bull VLHD Verilog Behavioral Large Blocks
bull Logic Design
bull Gates plus Registers
bull Circuit Design
bull Transistors sized for power and speed
bull Discrete Logic Technology Mapping
bull Layout
bull Size Interconnect Parasitics
Levels of Design
n+ n+
S
G D
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
WHAT IS ldquoCMOS VLSIrdquo
MOS = Metal Oxide Semiconductor (This used to mean a Metal gate over Oxide insulation)
Now we use polycrystalline silicon which is deposited on the surface of the chip as a gate We call this ldquopolyrdquo or just ldquored stuffrdquo to distinguish it from the body of the chip the substrate which is a single crystal of silicon
We do use metal (aluminum) for interconnection wires on the surface of the chip
CMOSCOMPLEMENTARY MOS
Means we are using both N-channel and P-
channel type enhancement mode Field Effect
Transistors (FETs)
Field Effect- NO current from the controlling
electrode into the output
FET is a voltage controlled current device
BJT is a current controlled current device
NP Channel - doping of the substrate for
increased carriers (electrons or holes)
Complementary Metal Oxide
Semiconductor
PMOS
NMOS
VSS
VDD
X Xrsquo
FOUR VIEWS
Logic Transistor Layout Physical
VLSI DESIGN
The real issue inVLSI is about designing systems
on chips
The designs are complex and we need to use
structured design techniques and sophisticated
design tools to manage the complexity of the
design
We also accept the fact that any technology we
learn the details of will be out of date soon
We are trying to develop and use techniques that
will transcend the technology but still respect it
HELP FROM COMPUTER AIDED DESIGN TOOLS
Tools
Editors
Simulators
Libraries
Module Synthesis
PlaceRoute
Chip Assemblers
Silicon Compilers
Experts
Logic design
Electroniccircuit
design
Device physics
Artwork
Applications - system
design
Architectures
DESIGN STYLES
Full custom
Standard cell
Gate-array
Macro-cell
ldquoFPGArdquo
Combinations
FULL CUSTOM
Hand drawn geometry
All layers customized
Digital and analog
Simulation at transistor level (analog)
High density
High performance
Long design time
FULL CUSTOM
IN Out
Vdd
Gnd
STANDARD CELLS
Standard cells organized in rows (and or flip-flopsetc)
Cells made as full custom by vendor (not user)
All layers customized
Digital with possibility of special analog cells
Simulation at gate level (digital)
Medium density
Medium-high performance
Reasonable design time
STANDARD CELLS
Routing
Cell
IO cell
GATE-ARRAY
Predefined transistors connected via metal
Two types Channel based Channel less (sea of gates)
Only metallization layers customized
Fixed array sizes (normally 5-10 different)
Digital cells in library (and or flip-flopsetc)
Simulation at gate level (digital)
Medium density
Medium performance
Reasonable design time
GATE-ARRAY
Oxide isolation
Gate isolation
PMOS
NMOS
Vdd
Gnd
B A
Out
Vdd
Gnd
A
B
Out
Sea of gates Channel based
NAND gate using gate isolation
Can in principle be used by adjacent cell
Sea of gates
Gate-array
RAM
MACRO CELL
Predefined macro blocks (Processors RAMetc)
Macro blocks made as full custom by vendor
All layers customized
Digital and some analog (ADC)
Simulation at behavioral or gate level (digital)
High density
High performance
Short design time
Use standard on-chip busses
ldquoSystem on a chiprdquo
DSP processor
LCD
cont RAM
ROM ADC
FPGA = FIELD PROGRAMMABLE GATE ARRAY
Programmable logic blocks
Programmable connections between logic blocks
No layers customized (standard devices)
Digital only
Low - medium performance (lt50 - 100MHz)
Low - medium density (up to ~100k gates)
Programmable by SRAM EEROM Anti_fuse etc
Cheap design tools on PCrsquos
Low development cost
High device cost
HIGH PERFORMANCE DEVICES
Mixture of full custom standard cells and
macrorsquos
Full custom for special blocks Adder (data
path) etc
Macrorsquos for standard blocks RAM ROM etc
Standard cells for non critical digital blocks
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large currents
between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between
source and drain
Low power allows very high integration
First patent in the rsquo20s in USA and Germany
Not widely used until the rsquo60s or rsquo70s
MOS TRANSISTORS
Four terminal device gate source drain body
Gate ndash oxide ndash body stack looks like a capacitor
Gate and body are conductors (body is also called the substrate)
SiO2 (oxide) is a ldquogoodrdquo insulator (separates the gate from the body
Called metalndashoxidendashsemiconductor (MOS) capacitor even though gate
is mostly made of poly-crystalline silicon (polysilicon)
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
NMOS PMOS
NMOS OPERATION
Body is commonly tied to ground (0 V)
Drain is at a higher voltage than Source
When the gate is at a low voltage
P-type body is at low voltage
Source-body and drain-body ldquodiodesrdquo are OFF
No current flows transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S
NMOS OPERATION CONT
When the gate is at a high voltage Positive charge on gate of MOS capacitor
Negative charge is attracted to body under the gate
Inverts a channel under gate to ldquon-typerdquo (N-channel hence
called the NMOS) if the gate voltage is above a threshold
voltage (VT)
Now current can flow through ldquon-typerdquo silicon from source
through channel to drain transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
PMOS TRANSISTOR
Similar but doping and voltages reversed
Body tied to high voltage (VDD)
Drain is at a lower voltage than the Source
Gate low transistor ON
Gate high transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
POWER SUPPLY VOLTAGE
GND = 0 V
In 1980rsquos VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 33 25 18 15 12 10
Effective power supply voltage can be lower due
to IR drop across the power grid
HELPING FIELDS FOR IC FABRICATION
Material Engineering
Chemistry
Device Physics
Advanced Technology
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
bull Specifications
bull IO Goals and Objectives Function Costs
bull Architectural Description
bull VLHD Verilog Behavioral Large Blocks
bull Logic Design
bull Gates plus Registers
bull Circuit Design
bull Transistors sized for power and speed
bull Discrete Logic Technology Mapping
bull Layout
bull Size Interconnect Parasitics
Levels of Design
n+ n+
S
G D
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
WHAT IS ldquoCMOS VLSIrdquo
MOS = Metal Oxide Semiconductor (This used to mean a Metal gate over Oxide insulation)
Now we use polycrystalline silicon which is deposited on the surface of the chip as a gate We call this ldquopolyrdquo or just ldquored stuffrdquo to distinguish it from the body of the chip the substrate which is a single crystal of silicon
We do use metal (aluminum) for interconnection wires on the surface of the chip
CMOSCOMPLEMENTARY MOS
Means we are using both N-channel and P-
channel type enhancement mode Field Effect
Transistors (FETs)
Field Effect- NO current from the controlling
electrode into the output
FET is a voltage controlled current device
BJT is a current controlled current device
NP Channel - doping of the substrate for
increased carriers (electrons or holes)
Complementary Metal Oxide
Semiconductor
PMOS
NMOS
VSS
VDD
X Xrsquo
FOUR VIEWS
Logic Transistor Layout Physical
VLSI DESIGN
The real issue inVLSI is about designing systems
on chips
The designs are complex and we need to use
structured design techniques and sophisticated
design tools to manage the complexity of the
design
We also accept the fact that any technology we
learn the details of will be out of date soon
We are trying to develop and use techniques that
will transcend the technology but still respect it
HELP FROM COMPUTER AIDED DESIGN TOOLS
Tools
Editors
Simulators
Libraries
Module Synthesis
PlaceRoute
Chip Assemblers
Silicon Compilers
Experts
Logic design
Electroniccircuit
design
Device physics
Artwork
Applications - system
design
Architectures
DESIGN STYLES
Full custom
Standard cell
Gate-array
Macro-cell
ldquoFPGArdquo
Combinations
FULL CUSTOM
Hand drawn geometry
All layers customized
Digital and analog
Simulation at transistor level (analog)
High density
High performance
Long design time
FULL CUSTOM
IN Out
Vdd
Gnd
STANDARD CELLS
Standard cells organized in rows (and or flip-flopsetc)
Cells made as full custom by vendor (not user)
All layers customized
Digital with possibility of special analog cells
Simulation at gate level (digital)
Medium density
Medium-high performance
Reasonable design time
STANDARD CELLS
Routing
Cell
IO cell
GATE-ARRAY
Predefined transistors connected via metal
Two types Channel based Channel less (sea of gates)
Only metallization layers customized
Fixed array sizes (normally 5-10 different)
Digital cells in library (and or flip-flopsetc)
Simulation at gate level (digital)
Medium density
Medium performance
Reasonable design time
GATE-ARRAY
Oxide isolation
Gate isolation
PMOS
NMOS
Vdd
Gnd
B A
Out
Vdd
Gnd
A
B
Out
Sea of gates Channel based
NAND gate using gate isolation
Can in principle be used by adjacent cell
Sea of gates
Gate-array
RAM
MACRO CELL
Predefined macro blocks (Processors RAMetc)
Macro blocks made as full custom by vendor
All layers customized
Digital and some analog (ADC)
Simulation at behavioral or gate level (digital)
High density
High performance
Short design time
Use standard on-chip busses
ldquoSystem on a chiprdquo
DSP processor
LCD
cont RAM
ROM ADC
FPGA = FIELD PROGRAMMABLE GATE ARRAY
Programmable logic blocks
Programmable connections between logic blocks
No layers customized (standard devices)
Digital only
Low - medium performance (lt50 - 100MHz)
Low - medium density (up to ~100k gates)
Programmable by SRAM EEROM Anti_fuse etc
Cheap design tools on PCrsquos
Low development cost
High device cost
HIGH PERFORMANCE DEVICES
Mixture of full custom standard cells and
macrorsquos
Full custom for special blocks Adder (data
path) etc
Macrorsquos for standard blocks RAM ROM etc
Standard cells for non critical digital blocks
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large currents
between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between
source and drain
Low power allows very high integration
First patent in the rsquo20s in USA and Germany
Not widely used until the rsquo60s or rsquo70s
MOS TRANSISTORS
Four terminal device gate source drain body
Gate ndash oxide ndash body stack looks like a capacitor
Gate and body are conductors (body is also called the substrate)
SiO2 (oxide) is a ldquogoodrdquo insulator (separates the gate from the body
Called metalndashoxidendashsemiconductor (MOS) capacitor even though gate
is mostly made of poly-crystalline silicon (polysilicon)
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
NMOS PMOS
NMOS OPERATION
Body is commonly tied to ground (0 V)
Drain is at a higher voltage than Source
When the gate is at a low voltage
P-type body is at low voltage
Source-body and drain-body ldquodiodesrdquo are OFF
No current flows transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S
NMOS OPERATION CONT
When the gate is at a high voltage Positive charge on gate of MOS capacitor
Negative charge is attracted to body under the gate
Inverts a channel under gate to ldquon-typerdquo (N-channel hence
called the NMOS) if the gate voltage is above a threshold
voltage (VT)
Now current can flow through ldquon-typerdquo silicon from source
through channel to drain transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
PMOS TRANSISTOR
Similar but doping and voltages reversed
Body tied to high voltage (VDD)
Drain is at a lower voltage than the Source
Gate low transistor ON
Gate high transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
POWER SUPPLY VOLTAGE
GND = 0 V
In 1980rsquos VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 33 25 18 15 12 10
Effective power supply voltage can be lower due
to IR drop across the power grid
HELPING FIELDS FOR IC FABRICATION
Material Engineering
Chemistry
Device Physics
Advanced Technology
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
n+ n+
S
G D
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
WHAT IS ldquoCMOS VLSIrdquo
MOS = Metal Oxide Semiconductor (This used to mean a Metal gate over Oxide insulation)
Now we use polycrystalline silicon which is deposited on the surface of the chip as a gate We call this ldquopolyrdquo or just ldquored stuffrdquo to distinguish it from the body of the chip the substrate which is a single crystal of silicon
We do use metal (aluminum) for interconnection wires on the surface of the chip
CMOSCOMPLEMENTARY MOS
Means we are using both N-channel and P-
channel type enhancement mode Field Effect
Transistors (FETs)
Field Effect- NO current from the controlling
electrode into the output
FET is a voltage controlled current device
BJT is a current controlled current device
NP Channel - doping of the substrate for
increased carriers (electrons or holes)
Complementary Metal Oxide
Semiconductor
PMOS
NMOS
VSS
VDD
X Xrsquo
FOUR VIEWS
Logic Transistor Layout Physical
VLSI DESIGN
The real issue inVLSI is about designing systems
on chips
The designs are complex and we need to use
structured design techniques and sophisticated
design tools to manage the complexity of the
design
We also accept the fact that any technology we
learn the details of will be out of date soon
We are trying to develop and use techniques that
will transcend the technology but still respect it
HELP FROM COMPUTER AIDED DESIGN TOOLS
Tools
Editors
Simulators
Libraries
Module Synthesis
PlaceRoute
Chip Assemblers
Silicon Compilers
Experts
Logic design
Electroniccircuit
design
Device physics
Artwork
Applications - system
design
Architectures
DESIGN STYLES
Full custom
Standard cell
Gate-array
Macro-cell
ldquoFPGArdquo
Combinations
FULL CUSTOM
Hand drawn geometry
All layers customized
Digital and analog
Simulation at transistor level (analog)
High density
High performance
Long design time
FULL CUSTOM
IN Out
Vdd
Gnd
STANDARD CELLS
Standard cells organized in rows (and or flip-flopsetc)
Cells made as full custom by vendor (not user)
All layers customized
Digital with possibility of special analog cells
Simulation at gate level (digital)
Medium density
Medium-high performance
Reasonable design time
STANDARD CELLS
Routing
Cell
IO cell
GATE-ARRAY
Predefined transistors connected via metal
Two types Channel based Channel less (sea of gates)
Only metallization layers customized
Fixed array sizes (normally 5-10 different)
Digital cells in library (and or flip-flopsetc)
Simulation at gate level (digital)
Medium density
Medium performance
Reasonable design time
GATE-ARRAY
Oxide isolation
Gate isolation
PMOS
NMOS
Vdd
Gnd
B A
Out
Vdd
Gnd
A
B
Out
Sea of gates Channel based
NAND gate using gate isolation
Can in principle be used by adjacent cell
Sea of gates
Gate-array
RAM
MACRO CELL
Predefined macro blocks (Processors RAMetc)
Macro blocks made as full custom by vendor
All layers customized
Digital and some analog (ADC)
Simulation at behavioral or gate level (digital)
High density
High performance
Short design time
Use standard on-chip busses
ldquoSystem on a chiprdquo
DSP processor
LCD
cont RAM
ROM ADC
FPGA = FIELD PROGRAMMABLE GATE ARRAY
Programmable logic blocks
Programmable connections between logic blocks
No layers customized (standard devices)
Digital only
Low - medium performance (lt50 - 100MHz)
Low - medium density (up to ~100k gates)
Programmable by SRAM EEROM Anti_fuse etc
Cheap design tools on PCrsquos
Low development cost
High device cost
HIGH PERFORMANCE DEVICES
Mixture of full custom standard cells and
macrorsquos
Full custom for special blocks Adder (data
path) etc
Macrorsquos for standard blocks RAM ROM etc
Standard cells for non critical digital blocks
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large currents
between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between
source and drain
Low power allows very high integration
First patent in the rsquo20s in USA and Germany
Not widely used until the rsquo60s or rsquo70s
MOS TRANSISTORS
Four terminal device gate source drain body
Gate ndash oxide ndash body stack looks like a capacitor
Gate and body are conductors (body is also called the substrate)
SiO2 (oxide) is a ldquogoodrdquo insulator (separates the gate from the body
Called metalndashoxidendashsemiconductor (MOS) capacitor even though gate
is mostly made of poly-crystalline silicon (polysilicon)
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
NMOS PMOS
NMOS OPERATION
Body is commonly tied to ground (0 V)
Drain is at a higher voltage than Source
When the gate is at a low voltage
P-type body is at low voltage
Source-body and drain-body ldquodiodesrdquo are OFF
No current flows transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S
NMOS OPERATION CONT
When the gate is at a high voltage Positive charge on gate of MOS capacitor
Negative charge is attracted to body under the gate
Inverts a channel under gate to ldquon-typerdquo (N-channel hence
called the NMOS) if the gate voltage is above a threshold
voltage (VT)
Now current can flow through ldquon-typerdquo silicon from source
through channel to drain transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
PMOS TRANSISTOR
Similar but doping and voltages reversed
Body tied to high voltage (VDD)
Drain is at a lower voltage than the Source
Gate low transistor ON
Gate high transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
POWER SUPPLY VOLTAGE
GND = 0 V
In 1980rsquos VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 33 25 18 15 12 10
Effective power supply voltage can be lower due
to IR drop across the power grid
HELPING FIELDS FOR IC FABRICATION
Material Engineering
Chemistry
Device Physics
Advanced Technology
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
WHAT IS ldquoCMOS VLSIrdquo
MOS = Metal Oxide Semiconductor (This used to mean a Metal gate over Oxide insulation)
Now we use polycrystalline silicon which is deposited on the surface of the chip as a gate We call this ldquopolyrdquo or just ldquored stuffrdquo to distinguish it from the body of the chip the substrate which is a single crystal of silicon
We do use metal (aluminum) for interconnection wires on the surface of the chip
CMOSCOMPLEMENTARY MOS
Means we are using both N-channel and P-
channel type enhancement mode Field Effect
Transistors (FETs)
Field Effect- NO current from the controlling
electrode into the output
FET is a voltage controlled current device
BJT is a current controlled current device
NP Channel - doping of the substrate for
increased carriers (electrons or holes)
Complementary Metal Oxide
Semiconductor
PMOS
NMOS
VSS
VDD
X Xrsquo
FOUR VIEWS
Logic Transistor Layout Physical
VLSI DESIGN
The real issue inVLSI is about designing systems
on chips
The designs are complex and we need to use
structured design techniques and sophisticated
design tools to manage the complexity of the
design
We also accept the fact that any technology we
learn the details of will be out of date soon
We are trying to develop and use techniques that
will transcend the technology but still respect it
HELP FROM COMPUTER AIDED DESIGN TOOLS
Tools
Editors
Simulators
Libraries
Module Synthesis
PlaceRoute
Chip Assemblers
Silicon Compilers
Experts
Logic design
Electroniccircuit
design
Device physics
Artwork
Applications - system
design
Architectures
DESIGN STYLES
Full custom
Standard cell
Gate-array
Macro-cell
ldquoFPGArdquo
Combinations
FULL CUSTOM
Hand drawn geometry
All layers customized
Digital and analog
Simulation at transistor level (analog)
High density
High performance
Long design time
FULL CUSTOM
IN Out
Vdd
Gnd
STANDARD CELLS
Standard cells organized in rows (and or flip-flopsetc)
Cells made as full custom by vendor (not user)
All layers customized
Digital with possibility of special analog cells
Simulation at gate level (digital)
Medium density
Medium-high performance
Reasonable design time
STANDARD CELLS
Routing
Cell
IO cell
GATE-ARRAY
Predefined transistors connected via metal
Two types Channel based Channel less (sea of gates)
Only metallization layers customized
Fixed array sizes (normally 5-10 different)
Digital cells in library (and or flip-flopsetc)
Simulation at gate level (digital)
Medium density
Medium performance
Reasonable design time
GATE-ARRAY
Oxide isolation
Gate isolation
PMOS
NMOS
Vdd
Gnd
B A
Out
Vdd
Gnd
A
B
Out
Sea of gates Channel based
NAND gate using gate isolation
Can in principle be used by adjacent cell
Sea of gates
Gate-array
RAM
MACRO CELL
Predefined macro blocks (Processors RAMetc)
Macro blocks made as full custom by vendor
All layers customized
Digital and some analog (ADC)
Simulation at behavioral or gate level (digital)
High density
High performance
Short design time
Use standard on-chip busses
ldquoSystem on a chiprdquo
DSP processor
LCD
cont RAM
ROM ADC
FPGA = FIELD PROGRAMMABLE GATE ARRAY
Programmable logic blocks
Programmable connections between logic blocks
No layers customized (standard devices)
Digital only
Low - medium performance (lt50 - 100MHz)
Low - medium density (up to ~100k gates)
Programmable by SRAM EEROM Anti_fuse etc
Cheap design tools on PCrsquos
Low development cost
High device cost
HIGH PERFORMANCE DEVICES
Mixture of full custom standard cells and
macrorsquos
Full custom for special blocks Adder (data
path) etc
Macrorsquos for standard blocks RAM ROM etc
Standard cells for non critical digital blocks
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large currents
between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between
source and drain
Low power allows very high integration
First patent in the rsquo20s in USA and Germany
Not widely used until the rsquo60s or rsquo70s
MOS TRANSISTORS
Four terminal device gate source drain body
Gate ndash oxide ndash body stack looks like a capacitor
Gate and body are conductors (body is also called the substrate)
SiO2 (oxide) is a ldquogoodrdquo insulator (separates the gate from the body
Called metalndashoxidendashsemiconductor (MOS) capacitor even though gate
is mostly made of poly-crystalline silicon (polysilicon)
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
NMOS PMOS
NMOS OPERATION
Body is commonly tied to ground (0 V)
Drain is at a higher voltage than Source
When the gate is at a low voltage
P-type body is at low voltage
Source-body and drain-body ldquodiodesrdquo are OFF
No current flows transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S
NMOS OPERATION CONT
When the gate is at a high voltage Positive charge on gate of MOS capacitor
Negative charge is attracted to body under the gate
Inverts a channel under gate to ldquon-typerdquo (N-channel hence
called the NMOS) if the gate voltage is above a threshold
voltage (VT)
Now current can flow through ldquon-typerdquo silicon from source
through channel to drain transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
PMOS TRANSISTOR
Similar but doping and voltages reversed
Body tied to high voltage (VDD)
Drain is at a lower voltage than the Source
Gate low transistor ON
Gate high transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
POWER SUPPLY VOLTAGE
GND = 0 V
In 1980rsquos VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 33 25 18 15 12 10
Effective power supply voltage can be lower due
to IR drop across the power grid
HELPING FIELDS FOR IC FABRICATION
Material Engineering
Chemistry
Device Physics
Advanced Technology
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
CMOSCOMPLEMENTARY MOS
Means we are using both N-channel and P-
channel type enhancement mode Field Effect
Transistors (FETs)
Field Effect- NO current from the controlling
electrode into the output
FET is a voltage controlled current device
BJT is a current controlled current device
NP Channel - doping of the substrate for
increased carriers (electrons or holes)
Complementary Metal Oxide
Semiconductor
PMOS
NMOS
VSS
VDD
X Xrsquo
FOUR VIEWS
Logic Transistor Layout Physical
VLSI DESIGN
The real issue inVLSI is about designing systems
on chips
The designs are complex and we need to use
structured design techniques and sophisticated
design tools to manage the complexity of the
design
We also accept the fact that any technology we
learn the details of will be out of date soon
We are trying to develop and use techniques that
will transcend the technology but still respect it
HELP FROM COMPUTER AIDED DESIGN TOOLS
Tools
Editors
Simulators
Libraries
Module Synthesis
PlaceRoute
Chip Assemblers
Silicon Compilers
Experts
Logic design
Electroniccircuit
design
Device physics
Artwork
Applications - system
design
Architectures
DESIGN STYLES
Full custom
Standard cell
Gate-array
Macro-cell
ldquoFPGArdquo
Combinations
FULL CUSTOM
Hand drawn geometry
All layers customized
Digital and analog
Simulation at transistor level (analog)
High density
High performance
Long design time
FULL CUSTOM
IN Out
Vdd
Gnd
STANDARD CELLS
Standard cells organized in rows (and or flip-flopsetc)
Cells made as full custom by vendor (not user)
All layers customized
Digital with possibility of special analog cells
Simulation at gate level (digital)
Medium density
Medium-high performance
Reasonable design time
STANDARD CELLS
Routing
Cell
IO cell
GATE-ARRAY
Predefined transistors connected via metal
Two types Channel based Channel less (sea of gates)
Only metallization layers customized
Fixed array sizes (normally 5-10 different)
Digital cells in library (and or flip-flopsetc)
Simulation at gate level (digital)
Medium density
Medium performance
Reasonable design time
GATE-ARRAY
Oxide isolation
Gate isolation
PMOS
NMOS
Vdd
Gnd
B A
Out
Vdd
Gnd
A
B
Out
Sea of gates Channel based
NAND gate using gate isolation
Can in principle be used by adjacent cell
Sea of gates
Gate-array
RAM
MACRO CELL
Predefined macro blocks (Processors RAMetc)
Macro blocks made as full custom by vendor
All layers customized
Digital and some analog (ADC)
Simulation at behavioral or gate level (digital)
High density
High performance
Short design time
Use standard on-chip busses
ldquoSystem on a chiprdquo
DSP processor
LCD
cont RAM
ROM ADC
FPGA = FIELD PROGRAMMABLE GATE ARRAY
Programmable logic blocks
Programmable connections between logic blocks
No layers customized (standard devices)
Digital only
Low - medium performance (lt50 - 100MHz)
Low - medium density (up to ~100k gates)
Programmable by SRAM EEROM Anti_fuse etc
Cheap design tools on PCrsquos
Low development cost
High device cost
HIGH PERFORMANCE DEVICES
Mixture of full custom standard cells and
macrorsquos
Full custom for special blocks Adder (data
path) etc
Macrorsquos for standard blocks RAM ROM etc
Standard cells for non critical digital blocks
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large currents
between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between
source and drain
Low power allows very high integration
First patent in the rsquo20s in USA and Germany
Not widely used until the rsquo60s or rsquo70s
MOS TRANSISTORS
Four terminal device gate source drain body
Gate ndash oxide ndash body stack looks like a capacitor
Gate and body are conductors (body is also called the substrate)
SiO2 (oxide) is a ldquogoodrdquo insulator (separates the gate from the body
Called metalndashoxidendashsemiconductor (MOS) capacitor even though gate
is mostly made of poly-crystalline silicon (polysilicon)
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
NMOS PMOS
NMOS OPERATION
Body is commonly tied to ground (0 V)
Drain is at a higher voltage than Source
When the gate is at a low voltage
P-type body is at low voltage
Source-body and drain-body ldquodiodesrdquo are OFF
No current flows transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S
NMOS OPERATION CONT
When the gate is at a high voltage Positive charge on gate of MOS capacitor
Negative charge is attracted to body under the gate
Inverts a channel under gate to ldquon-typerdquo (N-channel hence
called the NMOS) if the gate voltage is above a threshold
voltage (VT)
Now current can flow through ldquon-typerdquo silicon from source
through channel to drain transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
PMOS TRANSISTOR
Similar but doping and voltages reversed
Body tied to high voltage (VDD)
Drain is at a lower voltage than the Source
Gate low transistor ON
Gate high transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
POWER SUPPLY VOLTAGE
GND = 0 V
In 1980rsquos VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 33 25 18 15 12 10
Effective power supply voltage can be lower due
to IR drop across the power grid
HELPING FIELDS FOR IC FABRICATION
Material Engineering
Chemistry
Device Physics
Advanced Technology
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
Complementary Metal Oxide
Semiconductor
PMOS
NMOS
VSS
VDD
X Xrsquo
FOUR VIEWS
Logic Transistor Layout Physical
VLSI DESIGN
The real issue inVLSI is about designing systems
on chips
The designs are complex and we need to use
structured design techniques and sophisticated
design tools to manage the complexity of the
design
We also accept the fact that any technology we
learn the details of will be out of date soon
We are trying to develop and use techniques that
will transcend the technology but still respect it
HELP FROM COMPUTER AIDED DESIGN TOOLS
Tools
Editors
Simulators
Libraries
Module Synthesis
PlaceRoute
Chip Assemblers
Silicon Compilers
Experts
Logic design
Electroniccircuit
design
Device physics
Artwork
Applications - system
design
Architectures
DESIGN STYLES
Full custom
Standard cell
Gate-array
Macro-cell
ldquoFPGArdquo
Combinations
FULL CUSTOM
Hand drawn geometry
All layers customized
Digital and analog
Simulation at transistor level (analog)
High density
High performance
Long design time
FULL CUSTOM
IN Out
Vdd
Gnd
STANDARD CELLS
Standard cells organized in rows (and or flip-flopsetc)
Cells made as full custom by vendor (not user)
All layers customized
Digital with possibility of special analog cells
Simulation at gate level (digital)
Medium density
Medium-high performance
Reasonable design time
STANDARD CELLS
Routing
Cell
IO cell
GATE-ARRAY
Predefined transistors connected via metal
Two types Channel based Channel less (sea of gates)
Only metallization layers customized
Fixed array sizes (normally 5-10 different)
Digital cells in library (and or flip-flopsetc)
Simulation at gate level (digital)
Medium density
Medium performance
Reasonable design time
GATE-ARRAY
Oxide isolation
Gate isolation
PMOS
NMOS
Vdd
Gnd
B A
Out
Vdd
Gnd
A
B
Out
Sea of gates Channel based
NAND gate using gate isolation
Can in principle be used by adjacent cell
Sea of gates
Gate-array
RAM
MACRO CELL
Predefined macro blocks (Processors RAMetc)
Macro blocks made as full custom by vendor
All layers customized
Digital and some analog (ADC)
Simulation at behavioral or gate level (digital)
High density
High performance
Short design time
Use standard on-chip busses
ldquoSystem on a chiprdquo
DSP processor
LCD
cont RAM
ROM ADC
FPGA = FIELD PROGRAMMABLE GATE ARRAY
Programmable logic blocks
Programmable connections between logic blocks
No layers customized (standard devices)
Digital only
Low - medium performance (lt50 - 100MHz)
Low - medium density (up to ~100k gates)
Programmable by SRAM EEROM Anti_fuse etc
Cheap design tools on PCrsquos
Low development cost
High device cost
HIGH PERFORMANCE DEVICES
Mixture of full custom standard cells and
macrorsquos
Full custom for special blocks Adder (data
path) etc
Macrorsquos for standard blocks RAM ROM etc
Standard cells for non critical digital blocks
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large currents
between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between
source and drain
Low power allows very high integration
First patent in the rsquo20s in USA and Germany
Not widely used until the rsquo60s or rsquo70s
MOS TRANSISTORS
Four terminal device gate source drain body
Gate ndash oxide ndash body stack looks like a capacitor
Gate and body are conductors (body is also called the substrate)
SiO2 (oxide) is a ldquogoodrdquo insulator (separates the gate from the body
Called metalndashoxidendashsemiconductor (MOS) capacitor even though gate
is mostly made of poly-crystalline silicon (polysilicon)
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
NMOS PMOS
NMOS OPERATION
Body is commonly tied to ground (0 V)
Drain is at a higher voltage than Source
When the gate is at a low voltage
P-type body is at low voltage
Source-body and drain-body ldquodiodesrdquo are OFF
No current flows transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S
NMOS OPERATION CONT
When the gate is at a high voltage Positive charge on gate of MOS capacitor
Negative charge is attracted to body under the gate
Inverts a channel under gate to ldquon-typerdquo (N-channel hence
called the NMOS) if the gate voltage is above a threshold
voltage (VT)
Now current can flow through ldquon-typerdquo silicon from source
through channel to drain transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
PMOS TRANSISTOR
Similar but doping and voltages reversed
Body tied to high voltage (VDD)
Drain is at a lower voltage than the Source
Gate low transistor ON
Gate high transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
POWER SUPPLY VOLTAGE
GND = 0 V
In 1980rsquos VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 33 25 18 15 12 10
Effective power supply voltage can be lower due
to IR drop across the power grid
HELPING FIELDS FOR IC FABRICATION
Material Engineering
Chemistry
Device Physics
Advanced Technology
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
FOUR VIEWS
Logic Transistor Layout Physical
VLSI DESIGN
The real issue inVLSI is about designing systems
on chips
The designs are complex and we need to use
structured design techniques and sophisticated
design tools to manage the complexity of the
design
We also accept the fact that any technology we
learn the details of will be out of date soon
We are trying to develop and use techniques that
will transcend the technology but still respect it
HELP FROM COMPUTER AIDED DESIGN TOOLS
Tools
Editors
Simulators
Libraries
Module Synthesis
PlaceRoute
Chip Assemblers
Silicon Compilers
Experts
Logic design
Electroniccircuit
design
Device physics
Artwork
Applications - system
design
Architectures
DESIGN STYLES
Full custom
Standard cell
Gate-array
Macro-cell
ldquoFPGArdquo
Combinations
FULL CUSTOM
Hand drawn geometry
All layers customized
Digital and analog
Simulation at transistor level (analog)
High density
High performance
Long design time
FULL CUSTOM
IN Out
Vdd
Gnd
STANDARD CELLS
Standard cells organized in rows (and or flip-flopsetc)
Cells made as full custom by vendor (not user)
All layers customized
Digital with possibility of special analog cells
Simulation at gate level (digital)
Medium density
Medium-high performance
Reasonable design time
STANDARD CELLS
Routing
Cell
IO cell
GATE-ARRAY
Predefined transistors connected via metal
Two types Channel based Channel less (sea of gates)
Only metallization layers customized
Fixed array sizes (normally 5-10 different)
Digital cells in library (and or flip-flopsetc)
Simulation at gate level (digital)
Medium density
Medium performance
Reasonable design time
GATE-ARRAY
Oxide isolation
Gate isolation
PMOS
NMOS
Vdd
Gnd
B A
Out
Vdd
Gnd
A
B
Out
Sea of gates Channel based
NAND gate using gate isolation
Can in principle be used by adjacent cell
Sea of gates
Gate-array
RAM
MACRO CELL
Predefined macro blocks (Processors RAMetc)
Macro blocks made as full custom by vendor
All layers customized
Digital and some analog (ADC)
Simulation at behavioral or gate level (digital)
High density
High performance
Short design time
Use standard on-chip busses
ldquoSystem on a chiprdquo
DSP processor
LCD
cont RAM
ROM ADC
FPGA = FIELD PROGRAMMABLE GATE ARRAY
Programmable logic blocks
Programmable connections between logic blocks
No layers customized (standard devices)
Digital only
Low - medium performance (lt50 - 100MHz)
Low - medium density (up to ~100k gates)
Programmable by SRAM EEROM Anti_fuse etc
Cheap design tools on PCrsquos
Low development cost
High device cost
HIGH PERFORMANCE DEVICES
Mixture of full custom standard cells and
macrorsquos
Full custom for special blocks Adder (data
path) etc
Macrorsquos for standard blocks RAM ROM etc
Standard cells for non critical digital blocks
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large currents
between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between
source and drain
Low power allows very high integration
First patent in the rsquo20s in USA and Germany
Not widely used until the rsquo60s or rsquo70s
MOS TRANSISTORS
Four terminal device gate source drain body
Gate ndash oxide ndash body stack looks like a capacitor
Gate and body are conductors (body is also called the substrate)
SiO2 (oxide) is a ldquogoodrdquo insulator (separates the gate from the body
Called metalndashoxidendashsemiconductor (MOS) capacitor even though gate
is mostly made of poly-crystalline silicon (polysilicon)
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
NMOS PMOS
NMOS OPERATION
Body is commonly tied to ground (0 V)
Drain is at a higher voltage than Source
When the gate is at a low voltage
P-type body is at low voltage
Source-body and drain-body ldquodiodesrdquo are OFF
No current flows transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S
NMOS OPERATION CONT
When the gate is at a high voltage Positive charge on gate of MOS capacitor
Negative charge is attracted to body under the gate
Inverts a channel under gate to ldquon-typerdquo (N-channel hence
called the NMOS) if the gate voltage is above a threshold
voltage (VT)
Now current can flow through ldquon-typerdquo silicon from source
through channel to drain transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
PMOS TRANSISTOR
Similar but doping and voltages reversed
Body tied to high voltage (VDD)
Drain is at a lower voltage than the Source
Gate low transistor ON
Gate high transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
POWER SUPPLY VOLTAGE
GND = 0 V
In 1980rsquos VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 33 25 18 15 12 10
Effective power supply voltage can be lower due
to IR drop across the power grid
HELPING FIELDS FOR IC FABRICATION
Material Engineering
Chemistry
Device Physics
Advanced Technology
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
VLSI DESIGN
The real issue inVLSI is about designing systems
on chips
The designs are complex and we need to use
structured design techniques and sophisticated
design tools to manage the complexity of the
design
We also accept the fact that any technology we
learn the details of will be out of date soon
We are trying to develop and use techniques that
will transcend the technology but still respect it
HELP FROM COMPUTER AIDED DESIGN TOOLS
Tools
Editors
Simulators
Libraries
Module Synthesis
PlaceRoute
Chip Assemblers
Silicon Compilers
Experts
Logic design
Electroniccircuit
design
Device physics
Artwork
Applications - system
design
Architectures
DESIGN STYLES
Full custom
Standard cell
Gate-array
Macro-cell
ldquoFPGArdquo
Combinations
FULL CUSTOM
Hand drawn geometry
All layers customized
Digital and analog
Simulation at transistor level (analog)
High density
High performance
Long design time
FULL CUSTOM
IN Out
Vdd
Gnd
STANDARD CELLS
Standard cells organized in rows (and or flip-flopsetc)
Cells made as full custom by vendor (not user)
All layers customized
Digital with possibility of special analog cells
Simulation at gate level (digital)
Medium density
Medium-high performance
Reasonable design time
STANDARD CELLS
Routing
Cell
IO cell
GATE-ARRAY
Predefined transistors connected via metal
Two types Channel based Channel less (sea of gates)
Only metallization layers customized
Fixed array sizes (normally 5-10 different)
Digital cells in library (and or flip-flopsetc)
Simulation at gate level (digital)
Medium density
Medium performance
Reasonable design time
GATE-ARRAY
Oxide isolation
Gate isolation
PMOS
NMOS
Vdd
Gnd
B A
Out
Vdd
Gnd
A
B
Out
Sea of gates Channel based
NAND gate using gate isolation
Can in principle be used by adjacent cell
Sea of gates
Gate-array
RAM
MACRO CELL
Predefined macro blocks (Processors RAMetc)
Macro blocks made as full custom by vendor
All layers customized
Digital and some analog (ADC)
Simulation at behavioral or gate level (digital)
High density
High performance
Short design time
Use standard on-chip busses
ldquoSystem on a chiprdquo
DSP processor
LCD
cont RAM
ROM ADC
FPGA = FIELD PROGRAMMABLE GATE ARRAY
Programmable logic blocks
Programmable connections between logic blocks
No layers customized (standard devices)
Digital only
Low - medium performance (lt50 - 100MHz)
Low - medium density (up to ~100k gates)
Programmable by SRAM EEROM Anti_fuse etc
Cheap design tools on PCrsquos
Low development cost
High device cost
HIGH PERFORMANCE DEVICES
Mixture of full custom standard cells and
macrorsquos
Full custom for special blocks Adder (data
path) etc
Macrorsquos for standard blocks RAM ROM etc
Standard cells for non critical digital blocks
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large currents
between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between
source and drain
Low power allows very high integration
First patent in the rsquo20s in USA and Germany
Not widely used until the rsquo60s or rsquo70s
MOS TRANSISTORS
Four terminal device gate source drain body
Gate ndash oxide ndash body stack looks like a capacitor
Gate and body are conductors (body is also called the substrate)
SiO2 (oxide) is a ldquogoodrdquo insulator (separates the gate from the body
Called metalndashoxidendashsemiconductor (MOS) capacitor even though gate
is mostly made of poly-crystalline silicon (polysilicon)
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
NMOS PMOS
NMOS OPERATION
Body is commonly tied to ground (0 V)
Drain is at a higher voltage than Source
When the gate is at a low voltage
P-type body is at low voltage
Source-body and drain-body ldquodiodesrdquo are OFF
No current flows transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S
NMOS OPERATION CONT
When the gate is at a high voltage Positive charge on gate of MOS capacitor
Negative charge is attracted to body under the gate
Inverts a channel under gate to ldquon-typerdquo (N-channel hence
called the NMOS) if the gate voltage is above a threshold
voltage (VT)
Now current can flow through ldquon-typerdquo silicon from source
through channel to drain transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
PMOS TRANSISTOR
Similar but doping and voltages reversed
Body tied to high voltage (VDD)
Drain is at a lower voltage than the Source
Gate low transistor ON
Gate high transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
POWER SUPPLY VOLTAGE
GND = 0 V
In 1980rsquos VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 33 25 18 15 12 10
Effective power supply voltage can be lower due
to IR drop across the power grid
HELPING FIELDS FOR IC FABRICATION
Material Engineering
Chemistry
Device Physics
Advanced Technology
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
HELP FROM COMPUTER AIDED DESIGN TOOLS
Tools
Editors
Simulators
Libraries
Module Synthesis
PlaceRoute
Chip Assemblers
Silicon Compilers
Experts
Logic design
Electroniccircuit
design
Device physics
Artwork
Applications - system
design
Architectures
DESIGN STYLES
Full custom
Standard cell
Gate-array
Macro-cell
ldquoFPGArdquo
Combinations
FULL CUSTOM
Hand drawn geometry
All layers customized
Digital and analog
Simulation at transistor level (analog)
High density
High performance
Long design time
FULL CUSTOM
IN Out
Vdd
Gnd
STANDARD CELLS
Standard cells organized in rows (and or flip-flopsetc)
Cells made as full custom by vendor (not user)
All layers customized
Digital with possibility of special analog cells
Simulation at gate level (digital)
Medium density
Medium-high performance
Reasonable design time
STANDARD CELLS
Routing
Cell
IO cell
GATE-ARRAY
Predefined transistors connected via metal
Two types Channel based Channel less (sea of gates)
Only metallization layers customized
Fixed array sizes (normally 5-10 different)
Digital cells in library (and or flip-flopsetc)
Simulation at gate level (digital)
Medium density
Medium performance
Reasonable design time
GATE-ARRAY
Oxide isolation
Gate isolation
PMOS
NMOS
Vdd
Gnd
B A
Out
Vdd
Gnd
A
B
Out
Sea of gates Channel based
NAND gate using gate isolation
Can in principle be used by adjacent cell
Sea of gates
Gate-array
RAM
MACRO CELL
Predefined macro blocks (Processors RAMetc)
Macro blocks made as full custom by vendor
All layers customized
Digital and some analog (ADC)
Simulation at behavioral or gate level (digital)
High density
High performance
Short design time
Use standard on-chip busses
ldquoSystem on a chiprdquo
DSP processor
LCD
cont RAM
ROM ADC
FPGA = FIELD PROGRAMMABLE GATE ARRAY
Programmable logic blocks
Programmable connections between logic blocks
No layers customized (standard devices)
Digital only
Low - medium performance (lt50 - 100MHz)
Low - medium density (up to ~100k gates)
Programmable by SRAM EEROM Anti_fuse etc
Cheap design tools on PCrsquos
Low development cost
High device cost
HIGH PERFORMANCE DEVICES
Mixture of full custom standard cells and
macrorsquos
Full custom for special blocks Adder (data
path) etc
Macrorsquos for standard blocks RAM ROM etc
Standard cells for non critical digital blocks
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large currents
between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between
source and drain
Low power allows very high integration
First patent in the rsquo20s in USA and Germany
Not widely used until the rsquo60s or rsquo70s
MOS TRANSISTORS
Four terminal device gate source drain body
Gate ndash oxide ndash body stack looks like a capacitor
Gate and body are conductors (body is also called the substrate)
SiO2 (oxide) is a ldquogoodrdquo insulator (separates the gate from the body
Called metalndashoxidendashsemiconductor (MOS) capacitor even though gate
is mostly made of poly-crystalline silicon (polysilicon)
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
NMOS PMOS
NMOS OPERATION
Body is commonly tied to ground (0 V)
Drain is at a higher voltage than Source
When the gate is at a low voltage
P-type body is at low voltage
Source-body and drain-body ldquodiodesrdquo are OFF
No current flows transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S
NMOS OPERATION CONT
When the gate is at a high voltage Positive charge on gate of MOS capacitor
Negative charge is attracted to body under the gate
Inverts a channel under gate to ldquon-typerdquo (N-channel hence
called the NMOS) if the gate voltage is above a threshold
voltage (VT)
Now current can flow through ldquon-typerdquo silicon from source
through channel to drain transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
PMOS TRANSISTOR
Similar but doping and voltages reversed
Body tied to high voltage (VDD)
Drain is at a lower voltage than the Source
Gate low transistor ON
Gate high transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
POWER SUPPLY VOLTAGE
GND = 0 V
In 1980rsquos VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 33 25 18 15 12 10
Effective power supply voltage can be lower due
to IR drop across the power grid
HELPING FIELDS FOR IC FABRICATION
Material Engineering
Chemistry
Device Physics
Advanced Technology
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
DESIGN STYLES
Full custom
Standard cell
Gate-array
Macro-cell
ldquoFPGArdquo
Combinations
FULL CUSTOM
Hand drawn geometry
All layers customized
Digital and analog
Simulation at transistor level (analog)
High density
High performance
Long design time
FULL CUSTOM
IN Out
Vdd
Gnd
STANDARD CELLS
Standard cells organized in rows (and or flip-flopsetc)
Cells made as full custom by vendor (not user)
All layers customized
Digital with possibility of special analog cells
Simulation at gate level (digital)
Medium density
Medium-high performance
Reasonable design time
STANDARD CELLS
Routing
Cell
IO cell
GATE-ARRAY
Predefined transistors connected via metal
Two types Channel based Channel less (sea of gates)
Only metallization layers customized
Fixed array sizes (normally 5-10 different)
Digital cells in library (and or flip-flopsetc)
Simulation at gate level (digital)
Medium density
Medium performance
Reasonable design time
GATE-ARRAY
Oxide isolation
Gate isolation
PMOS
NMOS
Vdd
Gnd
B A
Out
Vdd
Gnd
A
B
Out
Sea of gates Channel based
NAND gate using gate isolation
Can in principle be used by adjacent cell
Sea of gates
Gate-array
RAM
MACRO CELL
Predefined macro blocks (Processors RAMetc)
Macro blocks made as full custom by vendor
All layers customized
Digital and some analog (ADC)
Simulation at behavioral or gate level (digital)
High density
High performance
Short design time
Use standard on-chip busses
ldquoSystem on a chiprdquo
DSP processor
LCD
cont RAM
ROM ADC
FPGA = FIELD PROGRAMMABLE GATE ARRAY
Programmable logic blocks
Programmable connections between logic blocks
No layers customized (standard devices)
Digital only
Low - medium performance (lt50 - 100MHz)
Low - medium density (up to ~100k gates)
Programmable by SRAM EEROM Anti_fuse etc
Cheap design tools on PCrsquos
Low development cost
High device cost
HIGH PERFORMANCE DEVICES
Mixture of full custom standard cells and
macrorsquos
Full custom for special blocks Adder (data
path) etc
Macrorsquos for standard blocks RAM ROM etc
Standard cells for non critical digital blocks
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large currents
between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between
source and drain
Low power allows very high integration
First patent in the rsquo20s in USA and Germany
Not widely used until the rsquo60s or rsquo70s
MOS TRANSISTORS
Four terminal device gate source drain body
Gate ndash oxide ndash body stack looks like a capacitor
Gate and body are conductors (body is also called the substrate)
SiO2 (oxide) is a ldquogoodrdquo insulator (separates the gate from the body
Called metalndashoxidendashsemiconductor (MOS) capacitor even though gate
is mostly made of poly-crystalline silicon (polysilicon)
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
NMOS PMOS
NMOS OPERATION
Body is commonly tied to ground (0 V)
Drain is at a higher voltage than Source
When the gate is at a low voltage
P-type body is at low voltage
Source-body and drain-body ldquodiodesrdquo are OFF
No current flows transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S
NMOS OPERATION CONT
When the gate is at a high voltage Positive charge on gate of MOS capacitor
Negative charge is attracted to body under the gate
Inverts a channel under gate to ldquon-typerdquo (N-channel hence
called the NMOS) if the gate voltage is above a threshold
voltage (VT)
Now current can flow through ldquon-typerdquo silicon from source
through channel to drain transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
PMOS TRANSISTOR
Similar but doping and voltages reversed
Body tied to high voltage (VDD)
Drain is at a lower voltage than the Source
Gate low transistor ON
Gate high transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
POWER SUPPLY VOLTAGE
GND = 0 V
In 1980rsquos VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 33 25 18 15 12 10
Effective power supply voltage can be lower due
to IR drop across the power grid
HELPING FIELDS FOR IC FABRICATION
Material Engineering
Chemistry
Device Physics
Advanced Technology
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
FULL CUSTOM
Hand drawn geometry
All layers customized
Digital and analog
Simulation at transistor level (analog)
High density
High performance
Long design time
FULL CUSTOM
IN Out
Vdd
Gnd
STANDARD CELLS
Standard cells organized in rows (and or flip-flopsetc)
Cells made as full custom by vendor (not user)
All layers customized
Digital with possibility of special analog cells
Simulation at gate level (digital)
Medium density
Medium-high performance
Reasonable design time
STANDARD CELLS
Routing
Cell
IO cell
GATE-ARRAY
Predefined transistors connected via metal
Two types Channel based Channel less (sea of gates)
Only metallization layers customized
Fixed array sizes (normally 5-10 different)
Digital cells in library (and or flip-flopsetc)
Simulation at gate level (digital)
Medium density
Medium performance
Reasonable design time
GATE-ARRAY
Oxide isolation
Gate isolation
PMOS
NMOS
Vdd
Gnd
B A
Out
Vdd
Gnd
A
B
Out
Sea of gates Channel based
NAND gate using gate isolation
Can in principle be used by adjacent cell
Sea of gates
Gate-array
RAM
MACRO CELL
Predefined macro blocks (Processors RAMetc)
Macro blocks made as full custom by vendor
All layers customized
Digital and some analog (ADC)
Simulation at behavioral or gate level (digital)
High density
High performance
Short design time
Use standard on-chip busses
ldquoSystem on a chiprdquo
DSP processor
LCD
cont RAM
ROM ADC
FPGA = FIELD PROGRAMMABLE GATE ARRAY
Programmable logic blocks
Programmable connections between logic blocks
No layers customized (standard devices)
Digital only
Low - medium performance (lt50 - 100MHz)
Low - medium density (up to ~100k gates)
Programmable by SRAM EEROM Anti_fuse etc
Cheap design tools on PCrsquos
Low development cost
High device cost
HIGH PERFORMANCE DEVICES
Mixture of full custom standard cells and
macrorsquos
Full custom for special blocks Adder (data
path) etc
Macrorsquos for standard blocks RAM ROM etc
Standard cells for non critical digital blocks
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large currents
between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between
source and drain
Low power allows very high integration
First patent in the rsquo20s in USA and Germany
Not widely used until the rsquo60s or rsquo70s
MOS TRANSISTORS
Four terminal device gate source drain body
Gate ndash oxide ndash body stack looks like a capacitor
Gate and body are conductors (body is also called the substrate)
SiO2 (oxide) is a ldquogoodrdquo insulator (separates the gate from the body
Called metalndashoxidendashsemiconductor (MOS) capacitor even though gate
is mostly made of poly-crystalline silicon (polysilicon)
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
NMOS PMOS
NMOS OPERATION
Body is commonly tied to ground (0 V)
Drain is at a higher voltage than Source
When the gate is at a low voltage
P-type body is at low voltage
Source-body and drain-body ldquodiodesrdquo are OFF
No current flows transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S
NMOS OPERATION CONT
When the gate is at a high voltage Positive charge on gate of MOS capacitor
Negative charge is attracted to body under the gate
Inverts a channel under gate to ldquon-typerdquo (N-channel hence
called the NMOS) if the gate voltage is above a threshold
voltage (VT)
Now current can flow through ldquon-typerdquo silicon from source
through channel to drain transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
PMOS TRANSISTOR
Similar but doping and voltages reversed
Body tied to high voltage (VDD)
Drain is at a lower voltage than the Source
Gate low transistor ON
Gate high transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
POWER SUPPLY VOLTAGE
GND = 0 V
In 1980rsquos VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 33 25 18 15 12 10
Effective power supply voltage can be lower due
to IR drop across the power grid
HELPING FIELDS FOR IC FABRICATION
Material Engineering
Chemistry
Device Physics
Advanced Technology
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
FULL CUSTOM
IN Out
Vdd
Gnd
STANDARD CELLS
Standard cells organized in rows (and or flip-flopsetc)
Cells made as full custom by vendor (not user)
All layers customized
Digital with possibility of special analog cells
Simulation at gate level (digital)
Medium density
Medium-high performance
Reasonable design time
STANDARD CELLS
Routing
Cell
IO cell
GATE-ARRAY
Predefined transistors connected via metal
Two types Channel based Channel less (sea of gates)
Only metallization layers customized
Fixed array sizes (normally 5-10 different)
Digital cells in library (and or flip-flopsetc)
Simulation at gate level (digital)
Medium density
Medium performance
Reasonable design time
GATE-ARRAY
Oxide isolation
Gate isolation
PMOS
NMOS
Vdd
Gnd
B A
Out
Vdd
Gnd
A
B
Out
Sea of gates Channel based
NAND gate using gate isolation
Can in principle be used by adjacent cell
Sea of gates
Gate-array
RAM
MACRO CELL
Predefined macro blocks (Processors RAMetc)
Macro blocks made as full custom by vendor
All layers customized
Digital and some analog (ADC)
Simulation at behavioral or gate level (digital)
High density
High performance
Short design time
Use standard on-chip busses
ldquoSystem on a chiprdquo
DSP processor
LCD
cont RAM
ROM ADC
FPGA = FIELD PROGRAMMABLE GATE ARRAY
Programmable logic blocks
Programmable connections between logic blocks
No layers customized (standard devices)
Digital only
Low - medium performance (lt50 - 100MHz)
Low - medium density (up to ~100k gates)
Programmable by SRAM EEROM Anti_fuse etc
Cheap design tools on PCrsquos
Low development cost
High device cost
HIGH PERFORMANCE DEVICES
Mixture of full custom standard cells and
macrorsquos
Full custom for special blocks Adder (data
path) etc
Macrorsquos for standard blocks RAM ROM etc
Standard cells for non critical digital blocks
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large currents
between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between
source and drain
Low power allows very high integration
First patent in the rsquo20s in USA and Germany
Not widely used until the rsquo60s or rsquo70s
MOS TRANSISTORS
Four terminal device gate source drain body
Gate ndash oxide ndash body stack looks like a capacitor
Gate and body are conductors (body is also called the substrate)
SiO2 (oxide) is a ldquogoodrdquo insulator (separates the gate from the body
Called metalndashoxidendashsemiconductor (MOS) capacitor even though gate
is mostly made of poly-crystalline silicon (polysilicon)
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
NMOS PMOS
NMOS OPERATION
Body is commonly tied to ground (0 V)
Drain is at a higher voltage than Source
When the gate is at a low voltage
P-type body is at low voltage
Source-body and drain-body ldquodiodesrdquo are OFF
No current flows transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S
NMOS OPERATION CONT
When the gate is at a high voltage Positive charge on gate of MOS capacitor
Negative charge is attracted to body under the gate
Inverts a channel under gate to ldquon-typerdquo (N-channel hence
called the NMOS) if the gate voltage is above a threshold
voltage (VT)
Now current can flow through ldquon-typerdquo silicon from source
through channel to drain transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
PMOS TRANSISTOR
Similar but doping and voltages reversed
Body tied to high voltage (VDD)
Drain is at a lower voltage than the Source
Gate low transistor ON
Gate high transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
POWER SUPPLY VOLTAGE
GND = 0 V
In 1980rsquos VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 33 25 18 15 12 10
Effective power supply voltage can be lower due
to IR drop across the power grid
HELPING FIELDS FOR IC FABRICATION
Material Engineering
Chemistry
Device Physics
Advanced Technology
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
STANDARD CELLS
Standard cells organized in rows (and or flip-flopsetc)
Cells made as full custom by vendor (not user)
All layers customized
Digital with possibility of special analog cells
Simulation at gate level (digital)
Medium density
Medium-high performance
Reasonable design time
STANDARD CELLS
Routing
Cell
IO cell
GATE-ARRAY
Predefined transistors connected via metal
Two types Channel based Channel less (sea of gates)
Only metallization layers customized
Fixed array sizes (normally 5-10 different)
Digital cells in library (and or flip-flopsetc)
Simulation at gate level (digital)
Medium density
Medium performance
Reasonable design time
GATE-ARRAY
Oxide isolation
Gate isolation
PMOS
NMOS
Vdd
Gnd
B A
Out
Vdd
Gnd
A
B
Out
Sea of gates Channel based
NAND gate using gate isolation
Can in principle be used by adjacent cell
Sea of gates
Gate-array
RAM
MACRO CELL
Predefined macro blocks (Processors RAMetc)
Macro blocks made as full custom by vendor
All layers customized
Digital and some analog (ADC)
Simulation at behavioral or gate level (digital)
High density
High performance
Short design time
Use standard on-chip busses
ldquoSystem on a chiprdquo
DSP processor
LCD
cont RAM
ROM ADC
FPGA = FIELD PROGRAMMABLE GATE ARRAY
Programmable logic blocks
Programmable connections between logic blocks
No layers customized (standard devices)
Digital only
Low - medium performance (lt50 - 100MHz)
Low - medium density (up to ~100k gates)
Programmable by SRAM EEROM Anti_fuse etc
Cheap design tools on PCrsquos
Low development cost
High device cost
HIGH PERFORMANCE DEVICES
Mixture of full custom standard cells and
macrorsquos
Full custom for special blocks Adder (data
path) etc
Macrorsquos for standard blocks RAM ROM etc
Standard cells for non critical digital blocks
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large currents
between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between
source and drain
Low power allows very high integration
First patent in the rsquo20s in USA and Germany
Not widely used until the rsquo60s or rsquo70s
MOS TRANSISTORS
Four terminal device gate source drain body
Gate ndash oxide ndash body stack looks like a capacitor
Gate and body are conductors (body is also called the substrate)
SiO2 (oxide) is a ldquogoodrdquo insulator (separates the gate from the body
Called metalndashoxidendashsemiconductor (MOS) capacitor even though gate
is mostly made of poly-crystalline silicon (polysilicon)
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
NMOS PMOS
NMOS OPERATION
Body is commonly tied to ground (0 V)
Drain is at a higher voltage than Source
When the gate is at a low voltage
P-type body is at low voltage
Source-body and drain-body ldquodiodesrdquo are OFF
No current flows transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S
NMOS OPERATION CONT
When the gate is at a high voltage Positive charge on gate of MOS capacitor
Negative charge is attracted to body under the gate
Inverts a channel under gate to ldquon-typerdquo (N-channel hence
called the NMOS) if the gate voltage is above a threshold
voltage (VT)
Now current can flow through ldquon-typerdquo silicon from source
through channel to drain transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
PMOS TRANSISTOR
Similar but doping and voltages reversed
Body tied to high voltage (VDD)
Drain is at a lower voltage than the Source
Gate low transistor ON
Gate high transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
POWER SUPPLY VOLTAGE
GND = 0 V
In 1980rsquos VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 33 25 18 15 12 10
Effective power supply voltage can be lower due
to IR drop across the power grid
HELPING FIELDS FOR IC FABRICATION
Material Engineering
Chemistry
Device Physics
Advanced Technology
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
STANDARD CELLS
Routing
Cell
IO cell
GATE-ARRAY
Predefined transistors connected via metal
Two types Channel based Channel less (sea of gates)
Only metallization layers customized
Fixed array sizes (normally 5-10 different)
Digital cells in library (and or flip-flopsetc)
Simulation at gate level (digital)
Medium density
Medium performance
Reasonable design time
GATE-ARRAY
Oxide isolation
Gate isolation
PMOS
NMOS
Vdd
Gnd
B A
Out
Vdd
Gnd
A
B
Out
Sea of gates Channel based
NAND gate using gate isolation
Can in principle be used by adjacent cell
Sea of gates
Gate-array
RAM
MACRO CELL
Predefined macro blocks (Processors RAMetc)
Macro blocks made as full custom by vendor
All layers customized
Digital and some analog (ADC)
Simulation at behavioral or gate level (digital)
High density
High performance
Short design time
Use standard on-chip busses
ldquoSystem on a chiprdquo
DSP processor
LCD
cont RAM
ROM ADC
FPGA = FIELD PROGRAMMABLE GATE ARRAY
Programmable logic blocks
Programmable connections between logic blocks
No layers customized (standard devices)
Digital only
Low - medium performance (lt50 - 100MHz)
Low - medium density (up to ~100k gates)
Programmable by SRAM EEROM Anti_fuse etc
Cheap design tools on PCrsquos
Low development cost
High device cost
HIGH PERFORMANCE DEVICES
Mixture of full custom standard cells and
macrorsquos
Full custom for special blocks Adder (data
path) etc
Macrorsquos for standard blocks RAM ROM etc
Standard cells for non critical digital blocks
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large currents
between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between
source and drain
Low power allows very high integration
First patent in the rsquo20s in USA and Germany
Not widely used until the rsquo60s or rsquo70s
MOS TRANSISTORS
Four terminal device gate source drain body
Gate ndash oxide ndash body stack looks like a capacitor
Gate and body are conductors (body is also called the substrate)
SiO2 (oxide) is a ldquogoodrdquo insulator (separates the gate from the body
Called metalndashoxidendashsemiconductor (MOS) capacitor even though gate
is mostly made of poly-crystalline silicon (polysilicon)
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
NMOS PMOS
NMOS OPERATION
Body is commonly tied to ground (0 V)
Drain is at a higher voltage than Source
When the gate is at a low voltage
P-type body is at low voltage
Source-body and drain-body ldquodiodesrdquo are OFF
No current flows transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S
NMOS OPERATION CONT
When the gate is at a high voltage Positive charge on gate of MOS capacitor
Negative charge is attracted to body under the gate
Inverts a channel under gate to ldquon-typerdquo (N-channel hence
called the NMOS) if the gate voltage is above a threshold
voltage (VT)
Now current can flow through ldquon-typerdquo silicon from source
through channel to drain transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
PMOS TRANSISTOR
Similar but doping and voltages reversed
Body tied to high voltage (VDD)
Drain is at a lower voltage than the Source
Gate low transistor ON
Gate high transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
POWER SUPPLY VOLTAGE
GND = 0 V
In 1980rsquos VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 33 25 18 15 12 10
Effective power supply voltage can be lower due
to IR drop across the power grid
HELPING FIELDS FOR IC FABRICATION
Material Engineering
Chemistry
Device Physics
Advanced Technology
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
GATE-ARRAY
Predefined transistors connected via metal
Two types Channel based Channel less (sea of gates)
Only metallization layers customized
Fixed array sizes (normally 5-10 different)
Digital cells in library (and or flip-flopsetc)
Simulation at gate level (digital)
Medium density
Medium performance
Reasonable design time
GATE-ARRAY
Oxide isolation
Gate isolation
PMOS
NMOS
Vdd
Gnd
B A
Out
Vdd
Gnd
A
B
Out
Sea of gates Channel based
NAND gate using gate isolation
Can in principle be used by adjacent cell
Sea of gates
Gate-array
RAM
MACRO CELL
Predefined macro blocks (Processors RAMetc)
Macro blocks made as full custom by vendor
All layers customized
Digital and some analog (ADC)
Simulation at behavioral or gate level (digital)
High density
High performance
Short design time
Use standard on-chip busses
ldquoSystem on a chiprdquo
DSP processor
LCD
cont RAM
ROM ADC
FPGA = FIELD PROGRAMMABLE GATE ARRAY
Programmable logic blocks
Programmable connections between logic blocks
No layers customized (standard devices)
Digital only
Low - medium performance (lt50 - 100MHz)
Low - medium density (up to ~100k gates)
Programmable by SRAM EEROM Anti_fuse etc
Cheap design tools on PCrsquos
Low development cost
High device cost
HIGH PERFORMANCE DEVICES
Mixture of full custom standard cells and
macrorsquos
Full custom for special blocks Adder (data
path) etc
Macrorsquos for standard blocks RAM ROM etc
Standard cells for non critical digital blocks
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large currents
between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between
source and drain
Low power allows very high integration
First patent in the rsquo20s in USA and Germany
Not widely used until the rsquo60s or rsquo70s
MOS TRANSISTORS
Four terminal device gate source drain body
Gate ndash oxide ndash body stack looks like a capacitor
Gate and body are conductors (body is also called the substrate)
SiO2 (oxide) is a ldquogoodrdquo insulator (separates the gate from the body
Called metalndashoxidendashsemiconductor (MOS) capacitor even though gate
is mostly made of poly-crystalline silicon (polysilicon)
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
NMOS PMOS
NMOS OPERATION
Body is commonly tied to ground (0 V)
Drain is at a higher voltage than Source
When the gate is at a low voltage
P-type body is at low voltage
Source-body and drain-body ldquodiodesrdquo are OFF
No current flows transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S
NMOS OPERATION CONT
When the gate is at a high voltage Positive charge on gate of MOS capacitor
Negative charge is attracted to body under the gate
Inverts a channel under gate to ldquon-typerdquo (N-channel hence
called the NMOS) if the gate voltage is above a threshold
voltage (VT)
Now current can flow through ldquon-typerdquo silicon from source
through channel to drain transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
PMOS TRANSISTOR
Similar but doping and voltages reversed
Body tied to high voltage (VDD)
Drain is at a lower voltage than the Source
Gate low transistor ON
Gate high transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
POWER SUPPLY VOLTAGE
GND = 0 V
In 1980rsquos VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 33 25 18 15 12 10
Effective power supply voltage can be lower due
to IR drop across the power grid
HELPING FIELDS FOR IC FABRICATION
Material Engineering
Chemistry
Device Physics
Advanced Technology
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
GATE-ARRAY
Oxide isolation
Gate isolation
PMOS
NMOS
Vdd
Gnd
B A
Out
Vdd
Gnd
A
B
Out
Sea of gates Channel based
NAND gate using gate isolation
Can in principle be used by adjacent cell
Sea of gates
Gate-array
RAM
MACRO CELL
Predefined macro blocks (Processors RAMetc)
Macro blocks made as full custom by vendor
All layers customized
Digital and some analog (ADC)
Simulation at behavioral or gate level (digital)
High density
High performance
Short design time
Use standard on-chip busses
ldquoSystem on a chiprdquo
DSP processor
LCD
cont RAM
ROM ADC
FPGA = FIELD PROGRAMMABLE GATE ARRAY
Programmable logic blocks
Programmable connections between logic blocks
No layers customized (standard devices)
Digital only
Low - medium performance (lt50 - 100MHz)
Low - medium density (up to ~100k gates)
Programmable by SRAM EEROM Anti_fuse etc
Cheap design tools on PCrsquos
Low development cost
High device cost
HIGH PERFORMANCE DEVICES
Mixture of full custom standard cells and
macrorsquos
Full custom for special blocks Adder (data
path) etc
Macrorsquos for standard blocks RAM ROM etc
Standard cells for non critical digital blocks
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large currents
between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between
source and drain
Low power allows very high integration
First patent in the rsquo20s in USA and Germany
Not widely used until the rsquo60s or rsquo70s
MOS TRANSISTORS
Four terminal device gate source drain body
Gate ndash oxide ndash body stack looks like a capacitor
Gate and body are conductors (body is also called the substrate)
SiO2 (oxide) is a ldquogoodrdquo insulator (separates the gate from the body
Called metalndashoxidendashsemiconductor (MOS) capacitor even though gate
is mostly made of poly-crystalline silicon (polysilicon)
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
NMOS PMOS
NMOS OPERATION
Body is commonly tied to ground (0 V)
Drain is at a higher voltage than Source
When the gate is at a low voltage
P-type body is at low voltage
Source-body and drain-body ldquodiodesrdquo are OFF
No current flows transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S
NMOS OPERATION CONT
When the gate is at a high voltage Positive charge on gate of MOS capacitor
Negative charge is attracted to body under the gate
Inverts a channel under gate to ldquon-typerdquo (N-channel hence
called the NMOS) if the gate voltage is above a threshold
voltage (VT)
Now current can flow through ldquon-typerdquo silicon from source
through channel to drain transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
PMOS TRANSISTOR
Similar but doping and voltages reversed
Body tied to high voltage (VDD)
Drain is at a lower voltage than the Source
Gate low transistor ON
Gate high transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
POWER SUPPLY VOLTAGE
GND = 0 V
In 1980rsquos VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 33 25 18 15 12 10
Effective power supply voltage can be lower due
to IR drop across the power grid
HELPING FIELDS FOR IC FABRICATION
Material Engineering
Chemistry
Device Physics
Advanced Technology
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
Sea of gates
Gate-array
RAM
MACRO CELL
Predefined macro blocks (Processors RAMetc)
Macro blocks made as full custom by vendor
All layers customized
Digital and some analog (ADC)
Simulation at behavioral or gate level (digital)
High density
High performance
Short design time
Use standard on-chip busses
ldquoSystem on a chiprdquo
DSP processor
LCD
cont RAM
ROM ADC
FPGA = FIELD PROGRAMMABLE GATE ARRAY
Programmable logic blocks
Programmable connections between logic blocks
No layers customized (standard devices)
Digital only
Low - medium performance (lt50 - 100MHz)
Low - medium density (up to ~100k gates)
Programmable by SRAM EEROM Anti_fuse etc
Cheap design tools on PCrsquos
Low development cost
High device cost
HIGH PERFORMANCE DEVICES
Mixture of full custom standard cells and
macrorsquos
Full custom for special blocks Adder (data
path) etc
Macrorsquos for standard blocks RAM ROM etc
Standard cells for non critical digital blocks
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large currents
between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between
source and drain
Low power allows very high integration
First patent in the rsquo20s in USA and Germany
Not widely used until the rsquo60s or rsquo70s
MOS TRANSISTORS
Four terminal device gate source drain body
Gate ndash oxide ndash body stack looks like a capacitor
Gate and body are conductors (body is also called the substrate)
SiO2 (oxide) is a ldquogoodrdquo insulator (separates the gate from the body
Called metalndashoxidendashsemiconductor (MOS) capacitor even though gate
is mostly made of poly-crystalline silicon (polysilicon)
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
NMOS PMOS
NMOS OPERATION
Body is commonly tied to ground (0 V)
Drain is at a higher voltage than Source
When the gate is at a low voltage
P-type body is at low voltage
Source-body and drain-body ldquodiodesrdquo are OFF
No current flows transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S
NMOS OPERATION CONT
When the gate is at a high voltage Positive charge on gate of MOS capacitor
Negative charge is attracted to body under the gate
Inverts a channel under gate to ldquon-typerdquo (N-channel hence
called the NMOS) if the gate voltage is above a threshold
voltage (VT)
Now current can flow through ldquon-typerdquo silicon from source
through channel to drain transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
PMOS TRANSISTOR
Similar but doping and voltages reversed
Body tied to high voltage (VDD)
Drain is at a lower voltage than the Source
Gate low transistor ON
Gate high transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
POWER SUPPLY VOLTAGE
GND = 0 V
In 1980rsquos VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 33 25 18 15 12 10
Effective power supply voltage can be lower due
to IR drop across the power grid
HELPING FIELDS FOR IC FABRICATION
Material Engineering
Chemistry
Device Physics
Advanced Technology
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
MACRO CELL
Predefined macro blocks (Processors RAMetc)
Macro blocks made as full custom by vendor
All layers customized
Digital and some analog (ADC)
Simulation at behavioral or gate level (digital)
High density
High performance
Short design time
Use standard on-chip busses
ldquoSystem on a chiprdquo
DSP processor
LCD
cont RAM
ROM ADC
FPGA = FIELD PROGRAMMABLE GATE ARRAY
Programmable logic blocks
Programmable connections between logic blocks
No layers customized (standard devices)
Digital only
Low - medium performance (lt50 - 100MHz)
Low - medium density (up to ~100k gates)
Programmable by SRAM EEROM Anti_fuse etc
Cheap design tools on PCrsquos
Low development cost
High device cost
HIGH PERFORMANCE DEVICES
Mixture of full custom standard cells and
macrorsquos
Full custom for special blocks Adder (data
path) etc
Macrorsquos for standard blocks RAM ROM etc
Standard cells for non critical digital blocks
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large currents
between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between
source and drain
Low power allows very high integration
First patent in the rsquo20s in USA and Germany
Not widely used until the rsquo60s or rsquo70s
MOS TRANSISTORS
Four terminal device gate source drain body
Gate ndash oxide ndash body stack looks like a capacitor
Gate and body are conductors (body is also called the substrate)
SiO2 (oxide) is a ldquogoodrdquo insulator (separates the gate from the body
Called metalndashoxidendashsemiconductor (MOS) capacitor even though gate
is mostly made of poly-crystalline silicon (polysilicon)
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
NMOS PMOS
NMOS OPERATION
Body is commonly tied to ground (0 V)
Drain is at a higher voltage than Source
When the gate is at a low voltage
P-type body is at low voltage
Source-body and drain-body ldquodiodesrdquo are OFF
No current flows transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S
NMOS OPERATION CONT
When the gate is at a high voltage Positive charge on gate of MOS capacitor
Negative charge is attracted to body under the gate
Inverts a channel under gate to ldquon-typerdquo (N-channel hence
called the NMOS) if the gate voltage is above a threshold
voltage (VT)
Now current can flow through ldquon-typerdquo silicon from source
through channel to drain transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
PMOS TRANSISTOR
Similar but doping and voltages reversed
Body tied to high voltage (VDD)
Drain is at a lower voltage than the Source
Gate low transistor ON
Gate high transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
POWER SUPPLY VOLTAGE
GND = 0 V
In 1980rsquos VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 33 25 18 15 12 10
Effective power supply voltage can be lower due
to IR drop across the power grid
HELPING FIELDS FOR IC FABRICATION
Material Engineering
Chemistry
Device Physics
Advanced Technology
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
FPGA = FIELD PROGRAMMABLE GATE ARRAY
Programmable logic blocks
Programmable connections between logic blocks
No layers customized (standard devices)
Digital only
Low - medium performance (lt50 - 100MHz)
Low - medium density (up to ~100k gates)
Programmable by SRAM EEROM Anti_fuse etc
Cheap design tools on PCrsquos
Low development cost
High device cost
HIGH PERFORMANCE DEVICES
Mixture of full custom standard cells and
macrorsquos
Full custom for special blocks Adder (data
path) etc
Macrorsquos for standard blocks RAM ROM etc
Standard cells for non critical digital blocks
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large currents
between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between
source and drain
Low power allows very high integration
First patent in the rsquo20s in USA and Germany
Not widely used until the rsquo60s or rsquo70s
MOS TRANSISTORS
Four terminal device gate source drain body
Gate ndash oxide ndash body stack looks like a capacitor
Gate and body are conductors (body is also called the substrate)
SiO2 (oxide) is a ldquogoodrdquo insulator (separates the gate from the body
Called metalndashoxidendashsemiconductor (MOS) capacitor even though gate
is mostly made of poly-crystalline silicon (polysilicon)
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
NMOS PMOS
NMOS OPERATION
Body is commonly tied to ground (0 V)
Drain is at a higher voltage than Source
When the gate is at a low voltage
P-type body is at low voltage
Source-body and drain-body ldquodiodesrdquo are OFF
No current flows transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S
NMOS OPERATION CONT
When the gate is at a high voltage Positive charge on gate of MOS capacitor
Negative charge is attracted to body under the gate
Inverts a channel under gate to ldquon-typerdquo (N-channel hence
called the NMOS) if the gate voltage is above a threshold
voltage (VT)
Now current can flow through ldquon-typerdquo silicon from source
through channel to drain transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
PMOS TRANSISTOR
Similar but doping and voltages reversed
Body tied to high voltage (VDD)
Drain is at a lower voltage than the Source
Gate low transistor ON
Gate high transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
POWER SUPPLY VOLTAGE
GND = 0 V
In 1980rsquos VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 33 25 18 15 12 10
Effective power supply voltage can be lower due
to IR drop across the power grid
HELPING FIELDS FOR IC FABRICATION
Material Engineering
Chemistry
Device Physics
Advanced Technology
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
HIGH PERFORMANCE DEVICES
Mixture of full custom standard cells and
macrorsquos
Full custom for special blocks Adder (data
path) etc
Macrorsquos for standard blocks RAM ROM etc
Standard cells for non critical digital blocks
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large currents
between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between
source and drain
Low power allows very high integration
First patent in the rsquo20s in USA and Germany
Not widely used until the rsquo60s or rsquo70s
MOS TRANSISTORS
Four terminal device gate source drain body
Gate ndash oxide ndash body stack looks like a capacitor
Gate and body are conductors (body is also called the substrate)
SiO2 (oxide) is a ldquogoodrdquo insulator (separates the gate from the body
Called metalndashoxidendashsemiconductor (MOS) capacitor even though gate
is mostly made of poly-crystalline silicon (polysilicon)
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
NMOS PMOS
NMOS OPERATION
Body is commonly tied to ground (0 V)
Drain is at a higher voltage than Source
When the gate is at a low voltage
P-type body is at low voltage
Source-body and drain-body ldquodiodesrdquo are OFF
No current flows transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S
NMOS OPERATION CONT
When the gate is at a high voltage Positive charge on gate of MOS capacitor
Negative charge is attracted to body under the gate
Inverts a channel under gate to ldquon-typerdquo (N-channel hence
called the NMOS) if the gate voltage is above a threshold
voltage (VT)
Now current can flow through ldquon-typerdquo silicon from source
through channel to drain transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
PMOS TRANSISTOR
Similar but doping and voltages reversed
Body tied to high voltage (VDD)
Drain is at a lower voltage than the Source
Gate low transistor ON
Gate high transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
POWER SUPPLY VOLTAGE
GND = 0 V
In 1980rsquos VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 33 25 18 15 12 10
Effective power supply voltage can be lower due
to IR drop across the power grid
HELPING FIELDS FOR IC FABRICATION
Material Engineering
Chemistry
Device Physics
Advanced Technology
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large currents
between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between
source and drain
Low power allows very high integration
First patent in the rsquo20s in USA and Germany
Not widely used until the rsquo60s or rsquo70s
MOS TRANSISTORS
Four terminal device gate source drain body
Gate ndash oxide ndash body stack looks like a capacitor
Gate and body are conductors (body is also called the substrate)
SiO2 (oxide) is a ldquogoodrdquo insulator (separates the gate from the body
Called metalndashoxidendashsemiconductor (MOS) capacitor even though gate
is mostly made of poly-crystalline silicon (polysilicon)
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
NMOS PMOS
NMOS OPERATION
Body is commonly tied to ground (0 V)
Drain is at a higher voltage than Source
When the gate is at a low voltage
P-type body is at low voltage
Source-body and drain-body ldquodiodesrdquo are OFF
No current flows transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S
NMOS OPERATION CONT
When the gate is at a high voltage Positive charge on gate of MOS capacitor
Negative charge is attracted to body under the gate
Inverts a channel under gate to ldquon-typerdquo (N-channel hence
called the NMOS) if the gate voltage is above a threshold
voltage (VT)
Now current can flow through ldquon-typerdquo silicon from source
through channel to drain transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
PMOS TRANSISTOR
Similar but doping and voltages reversed
Body tied to high voltage (VDD)
Drain is at a lower voltage than the Source
Gate low transistor ON
Gate high transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
POWER SUPPLY VOLTAGE
GND = 0 V
In 1980rsquos VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 33 25 18 15 12 10
Effective power supply voltage can be lower due
to IR drop across the power grid
HELPING FIELDS FOR IC FABRICATION
Material Engineering
Chemistry
Device Physics
Advanced Technology
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
MOS TRANSISTORS
Four terminal device gate source drain body
Gate ndash oxide ndash body stack looks like a capacitor
Gate and body are conductors (body is also called the substrate)
SiO2 (oxide) is a ldquogoodrdquo insulator (separates the gate from the body
Called metalndashoxidendashsemiconductor (MOS) capacitor even though gate
is mostly made of poly-crystalline silicon (polysilicon)
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
NMOS PMOS
NMOS OPERATION
Body is commonly tied to ground (0 V)
Drain is at a higher voltage than Source
When the gate is at a low voltage
P-type body is at low voltage
Source-body and drain-body ldquodiodesrdquo are OFF
No current flows transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S
NMOS OPERATION CONT
When the gate is at a high voltage Positive charge on gate of MOS capacitor
Negative charge is attracted to body under the gate
Inverts a channel under gate to ldquon-typerdquo (N-channel hence
called the NMOS) if the gate voltage is above a threshold
voltage (VT)
Now current can flow through ldquon-typerdquo silicon from source
through channel to drain transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
PMOS TRANSISTOR
Similar but doping and voltages reversed
Body tied to high voltage (VDD)
Drain is at a lower voltage than the Source
Gate low transistor ON
Gate high transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
POWER SUPPLY VOLTAGE
GND = 0 V
In 1980rsquos VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 33 25 18 15 12 10
Effective power supply voltage can be lower due
to IR drop across the power grid
HELPING FIELDS FOR IC FABRICATION
Material Engineering
Chemistry
Device Physics
Advanced Technology
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
NMOS OPERATION
Body is commonly tied to ground (0 V)
Drain is at a higher voltage than Source
When the gate is at a low voltage
P-type body is at low voltage
Source-body and drain-body ldquodiodesrdquo are OFF
No current flows transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S
NMOS OPERATION CONT
When the gate is at a high voltage Positive charge on gate of MOS capacitor
Negative charge is attracted to body under the gate
Inverts a channel under gate to ldquon-typerdquo (N-channel hence
called the NMOS) if the gate voltage is above a threshold
voltage (VT)
Now current can flow through ldquon-typerdquo silicon from source
through channel to drain transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
PMOS TRANSISTOR
Similar but doping and voltages reversed
Body tied to high voltage (VDD)
Drain is at a lower voltage than the Source
Gate low transistor ON
Gate high transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
POWER SUPPLY VOLTAGE
GND = 0 V
In 1980rsquos VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 33 25 18 15 12 10
Effective power supply voltage can be lower due
to IR drop across the power grid
HELPING FIELDS FOR IC FABRICATION
Material Engineering
Chemistry
Device Physics
Advanced Technology
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
NMOS OPERATION CONT
When the gate is at a high voltage Positive charge on gate of MOS capacitor
Negative charge is attracted to body under the gate
Inverts a channel under gate to ldquon-typerdquo (N-channel hence
called the NMOS) if the gate voltage is above a threshold
voltage (VT)
Now current can flow through ldquon-typerdquo silicon from source
through channel to drain transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
PMOS TRANSISTOR
Similar but doping and voltages reversed
Body tied to high voltage (VDD)
Drain is at a lower voltage than the Source
Gate low transistor ON
Gate high transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
POWER SUPPLY VOLTAGE
GND = 0 V
In 1980rsquos VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 33 25 18 15 12 10
Effective power supply voltage can be lower due
to IR drop across the power grid
HELPING FIELDS FOR IC FABRICATION
Material Engineering
Chemistry
Device Physics
Advanced Technology
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
PMOS TRANSISTOR
Similar but doping and voltages reversed
Body tied to high voltage (VDD)
Drain is at a lower voltage than the Source
Gate low transistor ON
Gate high transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
POWER SUPPLY VOLTAGE
GND = 0 V
In 1980rsquos VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 33 25 18 15 12 10
Effective power supply voltage can be lower due
to IR drop across the power grid
HELPING FIELDS FOR IC FABRICATION
Material Engineering
Chemistry
Device Physics
Advanced Technology
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
POWER SUPPLY VOLTAGE
GND = 0 V
In 1980rsquos VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 33 25 18 15 12 10
Effective power supply voltage can be lower due
to IR drop across the power grid
HELPING FIELDS FOR IC FABRICATION
Material Engineering
Chemistry
Device Physics
Advanced Technology
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
HELPING FIELDS FOR IC FABRICATION
Material Engineering
Chemistry
Device Physics
Advanced Technology
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
MATERIALS USED IN VLSI FABRICATION
Main Categories of Materials
Materials can be classified into three main groups
regarding their electrical conduction properties
1 Insulators
2 Conductors
3 Semiconductors
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
CONDUCTORS
Conductors are used in IC design for electrical
connectivity The following are good conducting
elements
1 Silver
2 Gold
3 Copper
4 Aluminum
5 Platinum
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
INSULATORS
Insulatorsare usedtoisolate conductingandor semi-conductingmaterialsfromeachother
MOS devicesand Capacitorsrelyon an
insulatorfortheirphysicaloperation
The choiceof the insulators(and the conductors)
in IC design dependsheavilyon howthe materials
interactwitheachother especiallywiththe
semiconductors
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
SEMICONDUCTORS
The basic semiconductor material usedin devicefabricationisSilicon
1048708 The success of thismaterial isdue to
1048708 Phisicalcharacteristics
1048708 Abundance in nature and very low cost
1048708 Relatively easy process
1048708 Reliable high volume fabrication
1048708 Othersemiconductors(eg GaAs) are usedforspecial applications
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