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Copyright 1997/8/9, KJH, 545_9, 5/8/2001 1 TestBench Prof. K. J. Hintz Department of Electrical and Computer Engineering George Mason University
Copyright 1997/8/9, KJH, 545_9, 5/8/20011
TestBench
Prof. K. J. Hintz
Department of Electricaland
Computer EngineeringGeorge Mason University
Copyright 1997/8/9, KJH, 545_9, 5/8/20012
Testbench Example
■ Configuration■ Clock■ Test Bench■ Behavioral to Structural■ After J. Pick, VHDL Techniques,
Experiments, and Caveats,McGraw-Hill,1996.
Copyright 1997/8/9, KJH, 545_9, 5/8/20013
Counter Test Bench Entity
entity Counter_Wrapper_TB is
end Counter_Wrapper_TB ;
No port clause since encapsulating counter totest it.
Copyright 1997/8/9, KJH, 545_9, 5/8/20014
First Counter Architecture
architecture Count_1 ofCounter_Wrapper_TB is
signal Clock : bit := ‘0’ ;
begin
Copyright 1997/8/9, KJH, 545_9, 5/8/20015
Local Clock
Clock_P_1 : process
begin
Clock <= not Clock after 50 ns;
wait on Clock ;
end process Clock_P_1 ;
Copyright 1997/8/9, KJH, 545_9, 5/8/20016
Counter Process
Inc_Cntr: process
variable Count_Now : integer := 0 ;
begin
--wait for trailing edge
wait until Clock = ‘0’ ;
Copyright 1997/8/9, KJH, 545_9, 5/8/20017
Increment Counter
--increment mod 8
if Count_Now = 7 then
Count_now := 0 ;
else
Count_now := Count_Now + 1 ;
end if ;
end process Inc_Cntr ;
end Count_1 ;
Copyright 1997/8/9, KJH, 545_9, 5/8/20018
2nd Counter Architecture
architecture Count_2 ofCounter_Wrapper_TB is
signal Clock : bit := ‘0’ ;
begin
-- no change
Copyright 1997/8/9, KJH, 545_9, 5/8/20019
Local Clock with StaticSensitivity List
Clock_P_2 : process ( Clock )
begin
Clock <= not Clock after 50 ns;
-- removed ... wait on Clock ;
end process Clock_P_2 ;
Copyright 1997/8/9, KJH, 545_9, 5/8/200110
Counter Process
Inc_Cntr: process
variable Count_Now : integer := 0 ;
begin
--wait for trailing edge
wait until Clock = ‘0’ ;
-- no change
Copyright 1997/8/9, KJH, 545_9, 5/8/200111
Increment Counter
--increment mod 8
if Count_Now = 7 then Count_now := 0 ;
else
Count_now := Count_Now + 1 ;
end if ;
-- no change
end process Inc_Cntr ;
end Count_2 ;
-- no change
Copyright 1997/8/9, KJH, 545_9, 5/8/200112
3rd Counter
■ Same As Others Except for Clock Generator
■ Concurrent Clock Instead of Process
■ Wrapper Slides Not Repeated Here
Copyright 1997/8/9, KJH, 545_9, 5/8/200113
Concurrent Local Clock
Clock_P_3 :
-- removed process ( Clock )
-- removed begin
Clock <= not Clock after 50 ns;
-- removed ... wait on Clock ;
-- removed end process Clock_P_2;
Copyright 1997/8/9, KJH, 545_9, 5/8/200114
Specific Configuration ofCounter
configuration Conf_KJH_1 of
Counter_Wrapper_TB is
--no ambiguity here
--only one entity per library
for Count_1
--ambiguity so need to
--specify architecture
Copyright 1997/8/9, KJH, 545_9, 5/8/200115
End Configuration
end for ;
end Conf_KJH_1 ;
--architecture is now bound
--to entity
Copyright 1997/8/9, KJH, 545_9, 5/8/200116
Encapsulation
Counter_Wrapper_TB
Conf_KJH_1
Count_1
Copyright 1997/8/9, KJH, 545_9, 5/8/200117
2nd Specific Configuration ofCounter
configuration Conf_KJH_2 of
Counter_Wrapper_TB is
--no ambiguity here
--only one entity per library
for Count_2
--ambiguity so need to
--specify architecture
Copyright 1997/8/9, KJH, 545_9, 5/8/200118
End Configuration
end for ;
end Conf_KJH_2 ;
--different architecture is
--now bound to same entity
--mutually exclusive bindings
Copyright 1997/8/9, KJH, 545_9, 5/8/200119
Encapsulation
Counter_Wrapper_TB
Conf_KJH_2
Count_2
Copyright 1997/8/9, KJH, 545_9, 5/8/200120
Encapsulation
Conf_KJH_?
Counter_Wrapper_TB
Count_?
Count_1
Count_2
Count_3
Architectures
Copyright 1997/8/9, KJH, 545_9, 5/8/200121
Structural Decomposition ofCounter_Wrapper_TB
Counter_Wrapper_TB
Count_3
Counter
Counter_Wrapper_TB
Clock
Verify
Copyright 1997/8/9, KJH, 545_9, 5/8/200122
SD Counter Clock Component
architecture Count_SD ofCounter_Wrapper_TB is
component Clock
generic (PW : time ) ;
port ( Clock : out bit );
end component Clock ;
Copyright 1997/8/9, KJH, 545_9, 5/8/200123
SD Counter Component
component Counter_Mod_8
port (
Clock : in bit ;
DataOut : out bit_vector (2 downto 0 ) );
end component Counter_Mod_8 ;
Copyright 1997/8/9, KJH, 545_9, 5/8/200124
SD Verify Component
component Verify
port (
DataIn : in bit_vector (2 downto 0 ) );
end component Verify ;
Copyright 1997/8/9, KJH, 545_9, 5/8/200125
SD Signals
signal Clock_Tic : bit := ‘0’ ;
signal Count_Data : bit_vector
(2 downto 0 ) := ( others => ‘0’ );
--initializes all values to ‘0’
Copyright 1997/8/9, KJH, 545_9, 5/8/200126
Clock Instantiation
begin
Synch : Clock
generic map ( PW => 50 ns )
--no ; required cause port next
port map ( Clock_Tic ) ;
Copyright 1997/8/9, KJH, 545_9, 5/8/200127
Counter Instantiation
Counter_Instance : Counter_Mod_8
port map ( Clock_Tic , Count_Data ) ;
Copyright 1997/8/9, KJH, 545_9, 5/8/200128
Verify Instantiation
Verify_Instance : Verify
port map ( DataIn => Count_Data ) ;
end Count_SD ;
Copyright 1997/8/9, KJH, 545_9, 5/8/200129
Block Diagram of SD
Clock out
Clock inDataOut (2)
DataOut (1)
DataOut (0)
Count_SD
Counter_Mod_8DataIn (2)
DataIn (1)
DataIn (0)
Verify
Copyright 1997/8/9, KJH, 545_9, 5/8/200130
Approach
■ Turn Counter_Mod_8 into an entity and putin a library after it has been verified
■ Count_SD is a good start to a testbenchwhere the counter drives a signal generatorwhich creates the sequential signals toexcite the device under test
■ Verify is a component which needs to beexpanded with assert/report statements toverify performance
Copyright 1997/8/9, KJH, 545_9, 5/8/200131
End of Lecture
■ Configuration■ Test Bench■ Structural
Decomposition
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