1st IEEE Energy Efficiency Tutorial - IEEE Future Networks · handset & small cell (24-52 GHz)...

Silicon Technology solutions to address power and performance requirements for sub 6GHz & mmWave 5G

Radio Interface

Anirban BandyopadhyayDirector, Strategic Applications, GLOBALFOUNDRIES, Inc., USA

[email protected]

1st IEEE Energy Efficiency Tutorial:

Wednesday, September 19, 2018

ALL INFORMATION SHALL BE CONSIDERED SPEAKER PROPERTY UNLESS OTHERWISE SUPERSEDED BY ANOTHER DOCUMENT.

• Introduction

• Cellular IOT – architecture & Technology Requirements

• FDSOI Based IOT RFSOC

• mmWave 5G – Phased Array & Beamforming Architecture

• Phased Array Systems based on PDSOI, FDSOI & SiGe

• Summary

2

Outline


• Introduction





• Summary

3


This presentation will highlight how different Silicon technologies enable power efficient operation for the above two use cases

4

5G Usage Scenarios

Enhanced Mobile

Broadband

Massive Machine type

Communication

Ultra reliable & low latency

Communication

Cellular IOT (Sub 6GHz) – Static power consumption is key (there’re exceptions)

mmWave 5G (24-40GHz) - both Dynamic

and static power consumptions are important

We’ll focus on two usage cases for energy efficiency

IOT

Sub 6GHz & mmWave


Timeline for 5G deployment

5

Rel. 15 Rel. 16 Rel. 17

2017 2018 2019 2020 2021 2022

Sub 6GHz & 24-52 GHz

3GPP

Phase1 Commercial Launches

5G

NR

Mainly sub 6GHz 5G & mmWave Fixed wireless

+mmWave eMBB

mmWave based enhanced mobile broadband in UE will be wide-spread during phase 2 of 5G launch

Phase2 Commercial Launches

Non-standalone (NSA)

standalone (SA)

V2X, IOT and others


• Introduction





• Summary

6

ALL INFORMATION SHALL BE CONSIDERED SPEAKER PROPERTY UNLESS OTHERWISE SUPERSEDED BY ANOTHER DOCUMENT.7

Sub 6GHz Cellular UE : Performance – Power Trade off

5G eMBBCAT 18CAT 4 ---CAT 1 ---NB-IOT

Increasing data rateDecreasing power / cost

CAT MPeak DataRate

<100kbps <1 Mbps <10 Mbps

Bandwidth 200 KHz 1.4 MHz up to 20MHz

Tx Power 20, 23 dBm 14dBm

20, 23 dBm 23 dBm

Duplex Mode

Half FDD

Half / FullFDD/TDD

Full FDD/TDD

Mobility Cell reselection

Limited-to-Full

Full

< 150 Mbps

Up to 20MHz

23dBm

FullFDD/TDD

Full

~ 1Gbps > 1 Gbps

100MHz > 100 MHz

23dBm / 26dBm (HPUE)

TBD

Full FDD/TDD

Full FDD/TDD

Full Full

The low CAT’s are targeted for low data rate at low cost & high power efficiency Higher CAT’s including 5G eMBB need to deliver high performance with high power

efficiency


Cellular IOT Radio ArchitectureGeneric architecture valid for CAT-M, NB-IOT & 5G IOT

LTE Baseband & RAM Direct Conversion RF

Integrated PMIC

PA

PA Switching Power Supply

PA

Logic & Memory dominated part

NB-IoT Base-band is simpler and smaller; CAT-M1 is 1.5 mm2 additional

RF parts

Analog & Mixed signal parts

Front end Module (FEM)

Chip Partitioning • Multi-chip solution possible with separate chips for FEM, Transceiver, Baseband & PMIC etc.

• Possible to implement the entire Radio except filters on SOC using appropriate technologies

• The main sources of static power consumption are Baseband & Memory and partly PMIC & Transceiver.


• Introduction





• Summary

9


Bulk , PDSOI & FDSOI FET Devices-2.0V to +2.0VBody-Biasing

10

Leak

age

Pow

er

• Depending on thickness above Buried Oxide, Silicon under the Gate can be partially or fully depleted of carriers

• Both PDSOI & FDSOI enable stacking of FET for high voltage(Power) tolerance

Bulk NFET Partially Depleted Silicon-On-Insulator (PDSOI) NFET

Fully Depleted Silicon-On-Insulator (FDSOI) NFET


Fully-Depleted Silicon On Insulator (FD-SOI) –Technology for low power RF SOC

• Software-controlled body-bias, post-silicon trimming• Integrated power mgmt (3.3 & 6.5v LDMOS)• Good RF performance to integrate FEM & Transceiver with Logic chips

-2.0V to +2.0VBody-Biasing

Ultra-thin Buried Oxide Insulator

Fully DepletedChannel for Low Leakage

Back Gate Bias to max Perf. or low leakage

11

Leak

age

Pow

er


FDSOI Ultra Low Power (ULP) Operation

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Ene

rgy

(no

rm)

Vdd (V)

switching energyLeaakge energytotal energy

SLVT, FBB=0.8V TT, 25C

Median:0.64V

Median:0.40V

28nm Poly/SiON 22nm FDSOI

Logic Vmin

0.4v

0.3v

0.6v

0.5v

0.7v

0.8v

22nm FDSOI can have an optimum operating Vdd =0.4V with leakage power ~1pA/um :• As Vdd decreases, both dynamic power and speed goes down• Leakage power also goes down as Vdd drops• Energy goes up below ~0.4V since delay increases result in crow-bar current increase


Technology Benchmarking for Low Power Mode

Total power for 22nm FDSOI @Vdd=0.4v is the lowest around 500-800 MHz

13

1200

800

120 240

Total Power (MW)

Freq

. (M

Hz)

13% More Power

180 210150

520

22nm FDSOI @0.4v 47% Less Power &50% Less Area

50% Faster, 18% Less Power,52% Less Area

ARM® A7 Results


Cellular IOT RFSOC using FDSOI – CAT-M/NB-IOT/5G IOT

• High Ft, even at lowest current density ( highest Gm/I), lowest power consumption for RF

• Stacked SOI FETs (3V breakdown @ 350GHz Fmax) for PA, switch (FEM) integration with TRX for IoT

• Low voltage operation (0.4V) for ultra low power IoT with back gate tuning

• Ultra-low leakage thin ox (~2pA/um), thick ox (~10pA/um) and SRAM (~1pA/cell) devices

• High density ( >5M gates/mm2) high performance digital logic

• Very small area, low power ADC and DAC, 3/5/6.5V LDMOS for PMIC integration

Baseband & RAM

Direct Conversion RF

Integrated PMIC

PA

PA

Cellular IoT SoC with Integrated FEM

14

Filters off-chip

0

100

200

300

400

1.0E-07 1.0E-05 1.0E-03

Ft (

GH

z)

Jd (Current Density)

High Ft even at low current density


PA efficiency increases with Input power level, but PA linearity and signal PAPR determine back off from saturation

For Cellular IOT, some applications will have RF communication more frequently than others, PA efficiency is important for those applications

IOT Dynamic power efficiency– Efficient PA

Input Power

Ou

tpu

t Po

wer

PA E

ffic

ien

cy

0.05

0.15

0.25

0.35

0.55

0.45

Class AB

Class A

Saturation

Saturation

PAPR (peak-to-average power ratio)


Efficient PA on 130nm PDSOI using EDNMOS at 2.4GHz

Vgg

Vcascode

RFin

RFout

EDNMOS FET

Thin/Thick gate FET

LindParameter EDNMOS (typ)

Typ operating Vgs [V] 2.5/3.3

Typ operating Vds [V] 5.0

Idsat @Vg=3.3V 540

BVdss [V] 15

fT/fmax [GHz] 39/70

Rds_on [mΩ/mm2] 1.6

Ioff [pA/μm] 7.0

PAEMAX

PAE1dB

PAEMAX: 59% @POUT = 22.2dBm

PAE1dB: 54% @P1dB = 21 dBm

PAE (Power Added Efficiency) = (Pout – Pin)/Pdc

Source: GLOBALFOUNDRIES


FDSOI enables integration of high power PA (> 1w) Digital PA

• Stacked FET implementation of current mode class-D power amplifier for cellular IOT

VDD_PA

RLOAD

1:N

vbg

vbgc1

vbgc2

vgc1

vgc2

vbg

vbgc1

vbgc2

vgc1

vgc2

Minimize transistor Ron to maximize PA efficiency

VoutpVoutn

IN_p IN_n

1.8V cascode transistorsto sustain voltage stress

Core devices aspower transistors

IpCtune

In



• Introduction





• Summary

18


mmWave Applications – Phased Array Antenna System

Low Earth Orbit (LEO) satellites for broadband

communications

Ka Band (26-40 GHz)

Fixed wireless, 5G handset & small cell

(24-52 GHz)

Millimeterwave backhaul

E Band (71-76 & 81-86 GHz)

ADAS auto radar

24 & 77-81 GHzIntegrated short, mid

and long range

802.11ad

57-63 GHz

Less TX power of power amplifier for larger array addressable by silicon technologies

Short distance, highly focused antenna beam


Different mmWave Beamforming Architectures

20

Digital Beamforming

Analog Beamforming

SPDT

SPDT

LNA

PAPower Combiner/splitter

Up/Dnconv

LNA

PA

/2

/2

ADC/DAC Modem + Host Processor

/2

/2ADC/DAC

Combiner / Splitter

DigitalPh

shifterDigital

Ph shifter

Modem + Host Processor

Hybrid Beamforming

SPDT

Power Combiner/splitter

Up/Dnconv

/2

/2

ADC/DAC

SPDT

Power Combiner/splitter

Up/Dnconv

/2

/2

ADC/DAC

Splitter/ Combiner

Digital Ph

shifter

Digital Ph

shifter

Modem + Host Processor

• Smallest #components• Low power dissipation• Complexity in phase shifting

• Large #components• module scaling to larger #array elements• multi beam implementation

• For large array where pure analog & digital beamforming are inefficient and complex

RF phase shifting

EIRP, receiver sensitivity, available form factor, power budget determine array size and architecture

SPDT

ADC/DACUp/Dnconv

ADC/DACUp/Dnconv

LNA

LNA

PA

PA

SPDT

SPDT

LNA

LNA

LNA

LNA

PA

PA

PA

PA

SPDT

SPDT

SPDT

SPDT

ALL INFORMATION SHALL BE CONSIDERED SPEAKER PROPERTY UNLESS OTHERWISE SUPERSEDED BY ANOTHER DOCUMENT. 21

Generic Architecture for mmWave 5G UE Example of digital Beamforming shown, can be analog Beamforming as well

TransceiverFEM subsystemAntenna

SubsystemBaseband and

Application Processing

The biggest contributors to power consumptions among RF components are PA, PLL’s & Data converters

App Processor

Modem / Digital Phase

splitter / power

combiner

RF & IF up/down

conversion

LNA

PA

SPDT

PA

SPDTRF & IF

up/down conversion

ADC/DAC

ADC/DAC

PA: High Psat, efficiency LNA: Low NF, high Gain Switch: low IL, high

Isolation & linearity Ph shifter/passives: low loss

Mixer: High conv gain, linearity

PLL: low ph noise ADC/DAC: low

power, high sampling rate

Low dynamic & leakage power, high speed and area scaling

Requirements

LNA


• Introduction





• Summary

22


Silicon Technologies for mmWave 5G Radio InterfaceTechnology Key Features Device Cross-Section

RF CMOS (65nm -28nm)

• High-volume logic process technology base with multiple foundries

• Comprehensive IP offerings for System-on-Chip (SOC)• Traction in mmWave markets: WiGig 802.11ad (60GHz), 77GHz

auto radar

PD-SOI (45nm)

PD-SOI = Partially Depleted Silicon on Insulator• High-speed w/ lower junction capacitance, isolation & stacking• 180nm RF SOI extensively used in cellular & Wi-Fi FEM• Early adoption in 5G & Sat Comm for 45nm PDSOI with highest

Ft/Fmax & optimum BEOL stack

FD-SOI (28nm -22nm)

FD-SOI = Fully Depleted Silicon-on-Insulator• Delivers FinFET-like performance and power-efficiency at

28/22nm cost• Transistor body-biasing for flexible trade-off between

performance and power• Enables applications across mobile, IoT and mmWave markets

SiGe (130nm -90nm)

SiGe = Silicon Germanium• Based on higher performance & power tolerant HBT ( vs FET)• Technology optimized for micro and mmWave applications:

backhaul, E-band links, Sat Comm, automotive radar, A&D

GS D

We’ll highlight capabilities of some of these technologies, namely, 45nm PDSOI, 22nm FDSOI & 130/90nm SiGe to address energy efficient mmWave 5G


How to address RF power efficiency on a Silicon Technology platform for mmWave

24

- High PA Pout with high Gain leads to less #antenna element and

significant power reduction for digital / Hybrid Beamforming

High-performance technology (High Self Gain, Ft/Fmax – at least 3-5X operating frequency)

–Higher PA power efficiency, low loss matching network, less Pout to

compensate for interconnect/ passive loss

Low loss Backend-of-line (high resistivity substrate, increased BEOL metal stack height)

Low power PLL & data converters

–Lower power budget particularly for digital/hybrid beamforming with

large #antenna array


mmWave Interconnect Loss – how to address power efficiency?

25

From another BF chip

/2

/2

Need to be IF/Baseband signal, not mmWave, to reduce interconnect loss

Interconnect length can be >> cm long

From another BF chip

Chip-to-chip Interconnect loss at mmWave is very high For large 2D or linear array, the mmWave signal should be converted to IF or baseband

in the nearest proximity of BF chip to avoid huge loss due to long interconnect between Beamforming and Transceiver/ Modem chip

Beamforming (BF) Chip

IF Transceiver and/or Baseband chip


mmWave Beamforming FEM using Partially Depleted SOI Technology

3 High resistivity substrate:

- Improves back-end-of-line (BEOL) losses due to parasitics - Linearity in Switches

2 Raised thick Cu levels:

- High Q inductors and transformers- Low loss transmission lines- High Q & high density MIMs or APMOMs- Dual thick Cu levels provide design flexibility

1 Transistor Stacking

- Capability of stacking FET’s enable Switches & PA’s to withstand high voltage swing - Avoids power combining to generate mmWave power efficiently

Increased ‘d’ to substrate reduces parasitics / coupling

11LM 8LM

AL

Cu

Cu

AL

Cu

Cu

Cu

45nm PDSOI Backend-of-the-line optimization

45nm PDSOI BEOL IL comparison with different substrates

0.8dB



45nm PD SOI NFET & PFET FT/FMAX

• Ldes = 40 nm (nom), width = 1 µm x 20

• Double sided gate contact De-embedded to M1

• 1x pitch peak FT = 250 GHz, peak FMAX = 350 GHz


• Ldes = 40 nm (nom), width = 1 µm x 20

• Double sided gate contact De-embedded to M1



High Ft/Fmax provides flexibility for both PA & LNA design on 45nm PDSOI within 24-40GHz and beyond.



45nm PDSOI based Power Amplifier with high PAE (Power added efficiency)

Single ended PA 16dBm Psat Peak PAE>40%

Single ended PA with 20dBm Psat Peak PAE ~30%

Differential Doherty PA Psat > 23dBm Peak PAE > 40%

With efficient linear PA and low BEOL loss, 45nm PDSOI can address energy efficient 5G beamforming FEM

Courtesy of Prof. H. Wang, Georgia Institute of Technology, Atlanta



FDSOI Technology for mmWave applications

29

FDSOI FET

• High Ft/Fmax & self Gain , Peak Gm*Ft/Ids at

low current (2.65 THz/V @ 100uA/um)

• Low 1/f noise : 200fV2mm2/Hz @ 100Hz for

L=20nm

• High breakdown voltage and very high HCI

voltage limit mainly at low-Vgs

• Low power Tx line driver using back-gate bias

FDSOI – capable of integrating FEM, Transceiver including ADC/DAC and SERDES


FOM Comparison - bulk CMOS & FDSOI

FDSOI has at least 20% lower current for same RF performance

compared to 28nm

For mmWave LNA, mixer circuits, FDSOI has 30% higher

performance and 16% lower current than 28nm

For mmWave PA circuits, FDSOI far outperforms any other CMOS

node

Above results are for 1X CPP layout, higher Fmax *Gm/I for 2X CPP



22nm FDSOI SLVT NFET Self-Gain1xCPP Layout

With 2xCPP Layout Style Self, Gain is 20+ for L=17nm

Vds=0.8V Vds=0.4V

L=17nm L=28nm

High Self-Gain at mmWave bands offers flexibility in both PA & LNA design to meet both high linear Gain and high Pout provided Fmax is high (at least 3-5X the operating freq.)



22nm FDSOI 28GHz Differential PA with high PAE

28-40GHz 5G TRX with Integrated FEM

32

High efficiency PA enables 22nm FDSOI to be an excellent candidate for mmWave 5G UE devices

3-Stack PA Schematic

High Psat DesignMeasured

High PAE DesignMeasured

SG-SG-SG SG-SG

S21 peak freq (GHz)

27.8 29

IDDQ (mA) 15.9 15.8

Gain (dB) 12.4 12.7

Psat/P3dB(dBm) 18.2 16.4

PAE_Psat-6dB (%) 18.3 20.8

PAE_peak (%) 30.2 41.0

Ruggedness Passed

18dBm 15dBm



• Optimizing vertical (intrinsic) & lateral (extrinsic) profiles allows one to improve Ft – BV margin

33

SiGe (P) Base

Regions to optimize for breakdown

8HP

9HP

SiGe HBT’s avoids the need for multi-stacking approach used for FETs in CMOS improves PAE for PA

• SiGe HBT Breakdown (BVcbo) Saturating at 4V for Ft >500 GHz


High Performance SiGe Technology for mmWave 5G

Heterojunction Bipolar Transistor (HBT)


130nm & 90nm SiGe Technologies -HBT’s offer High Ft/Fmax at low power

• SiGe (8XP) offers Fmax of 350 GHz; SiGe (9HP) offers Fmax of 370 GHz

• CMOS logic supporting thin and thick oxide for 1.2 V / 1.5 V, 1.8 V / 2.5 V / 3.3 V

• Thick top level metals for improved transmission line loss

34

Fmax

Ft


High Fmax and breakdown voltage of SiGe makes it an ideal technology for high Psat, PAE, linearity of PA with high reliability.


High Performance SiGe HBT based forWideband Doherty PA at 39GHz

35

CW measurements – Power back-off at 39 GHz Achieved 17 dBm PSAT, 15.4 dBm P1dB, 28.2% peak collector efficiency

1.92× efficiency enhancement over class-B at 6dB Power Back Off

Courtesy of Prof. H. Wang, Georgia Institute of Technology, Atlanta


Analog Beamforming Architecture used for Power Budget Estimation

36

Number of elements (N) can be typically 4-8 for UE, we assumed N=4 and 8 for the analyses

Phase Shifter (PS) and VGA has a number of bits 6-8-bit for Phase/Gain Control & Calibration

LNA

f

PS+VGA

PA

LNA

f

PS+VGA

PA

Co

mb

iner

/Sp

litte

r

LO1(Low-Side Injection)

2xLO2

AMP

AMP

I/Q BB RX

I/Q BB TX

PLLLO1

PLL2xLO2

5G FE

RFTransceiver

.

.

.N


Digital Beamforming Architecture used for Power Budget Estimation

37

Transmitter + DAC

Receiver + ADC

PLL

Digital BFLogic

LO Lines

Transmitter + DAC

Receiver + ADC

Transmitter + DAC

Receiver + ADC

Transmitter + DAC

Receiver + ADC

• Both transmit and receiver use direct conversion• N=4 and 8 are used for Digital Beamforming as well for power analysis


22nm FDSOI vs 28HKM Bulk CMOS Power Budget Analysis

38

Technology 28HKM 22FDSOI 22FDSOI 22FDSOI 22FDSOI

ArchitectureABF, High IF,

N=8

ABF, High IF,

N=8

DBF, DC,

N=8

ABF, High IF,

N=4

DBF, DC,

N=4

PA Pout

(dBm)7 7 7 13 13

Pdc (mW)

(Tx/RX

0.3/0.7)

506 415 360 315 289

All 22nm FDSOI power consumption results based on measured results of silicon blocks

22nm FDSOI Analog Beamforming solution has ~20% less power budget than 28HKM bulk CMOS, much higher delta for digital BF

Analysis for 16QAM UL/DL, 100MHz RF BW


mmWave 5G UE chip partitioning options

TransceiverFEM subsystemAntenna

SubsystemBaseband and

Application Processing

App Processor

Modem / Digital Phase

splitter / power

combiner

RF & IF up/down

conversion

LNA

PA

SPDT

LNA

PA

SPDT

RF & IF up/down

conversion

ADC/DAC

ADC/DAC

14/10/7nmFinFET

22nm FDSOI

45nm PDSOI up to IF

28/22nm bulkCMOS w/ SiGe/III-V PA & RFSOI Switch if needed

28/22nm bulk45nm PDSOI up to IF

14/10/7nmFinFET

14/10/7nmFinFET

14/10/7nmFinFET

14/10/7nmFinFET

Possible Silicon Technology options for chip partitioning

Multiple Silicon technology options depending on EIRP, #antenna array and Power efficiency


Chip Partitioning options for mmWave 5G Infrastructure

BB

L1/L2/L3

Data

Conv

Subsystem

Transceiver

SubsystemFEM Subsystem

Antenna

Subsystem DFE

Digital UnitRadio Unit

130/90nm SiGe or 45nm PDSOI 14/10/7nm FinFET 14/10/7nm FinFET

22nm FDSOI

Hybrid Beam Forming

RF & IF up/downconversion

LNA

PA

SPDT

Power combiners/splitters and phase shifters

LNA

PA

LNA

PA

LNA

PA

RF & IF up/downconversion

Power combiners/splitters and phase shifters

DAC/ADC

DAC/ADC

DFE L1/L2/L3 Baseband ProcessingDAC/ADC

DAC/ADC

DAC/ADC

DAC/ADC

SPDT

SPDT

SPDT

14/10/7nm FinFET

28-22nm CMOS w/ SiGe/III-V PA & RFSOI Switch, if needed 14/10/7nm FinFET 14/10/7nm FinFET

Possible chip partitioning options

Tx power/ PA & overall power budget will decide the technology options and chip partitioning


Summary

• Two usage scenarios of 5G - cellular IOT (sub 6GHz) and mmWave eMBB have been covered

• Different Silicon technologies like Partially & Fully depleted SOI and SiGe that can address power efficient 5G operation are highlighted

• It’s shown that back gate biased FDSOI can address low standby power for 5G IOT

• 45nm PDSOI, 22nm FDSOI & 130/90nm SiGe can address power efficient mmWave beamforming system

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1st IEEE Energy Efficiency Tutorial - IEEE Future Networks · handset & small cell (24-52 GHz)...

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