24 July 2002 Work In Progress – Not for Publication

2001 ITRS Test Chapter

• New Additions– Reliability Methods– Material Handling– Device Interface Technology

• Updates– High Frequency Serial Communications– High Performance ASIC– High Performance Microprocessor– Low-end Microcontroller– Mixed Signal and Wireless– DFT Tester– Embedded and Commodity DRAM and Flash

24 July 2002 Work In Progress – Not for Publication

2001 Key Challenges

• High Speed Device Interfaces• Highly Integrated Designs & SOCs• Reliability Screens• Manufacturing Test Cost Reduction• Test Software Standards• Modeling and Simulation

24 July 2002 Work In Progress – Not for Publication

YEAR OF PRODUCTION 2001 2002 2003 2004 2005 2006 2007

MPU / ASIC ½ PITCH (nm) 150 130 107 90 80 70 65

High-integration-level backplane and computer I/O

Serial data rate (Gbits/s) Production 2.5 3.125 3.125 10 10 40 40

Introduction 3.125 — 10 — 40 — —

Maximum port count at Production frequencies 20 100 200 100 200 100 200

at Introduction frequencies — — 20 — 20 — —

i

Demand for Bandwidth

• Penetration of high speed interfaces into new designs is increasing dramatically

• Learning rate for ATE solutions lags leading edge device technology

• Test and DFT methods must be developed to enable development and production test of these products

24 July 2002 Work In Progress – Not for Publication

High Integration Devices & SOC

• Customer requirements for form factor and power consumption are driving a significant increase in design integration levels– Test complexity will increase dramatically with the

combination of different classes of circuits on single die or within a single package

– Disciplined, structured DFT is a requirement to reduce test complexity

• New test methods and equipment architectures must be developed– Enable a merge of logic and analog test capability with

the throughput of high density memory test equipment

24 July 2002 Work In Progress – Not for Publication

Reliability Screens Run Out of Gas

• Critical need for development of new techniques for acceleration of latent defects– Burn-in methods limited by thermal runaway– Lowered use voltages limits voltage stress opportunity– Difficulty of determining Iddq signal versus “normal”

leakage current noise

• New materials– Rate of introduction increasing: Cu, low k, high k, SiGe– Increasing mechanical sensitivities

• Rapid growth of Fabless business model– Organizational and corporate boundaries - lack of clear

ownership of reliability in distributed business models

24 July 2002 Work In Progress – Not for Publication

Scaling Component Test Cost

• Recent steps have enabled test cost to begin to scale across technology nodes– Equipment reuse across nodes– Increasing test throughput

• Challenge remains in most segments, especially high speed and high integration products

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1980 1985 1990 1995 2000 2005 2010 2015

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SIA Silicon manufacturing

SIA Test equipment depreciation

24 July 2002 Work In Progress – Not for Publication

Dismantling the Red Brick Walls

• Design For Test enabling has begun to remove many of the roadblocks that appeared in the 1997 and 1999 roadmaps– Test is becoming integrated with the design process– Improvements demonstrated in capability and cost

• Continued research is needed into new and existing digital logic fault models toward identification of true process defects

• Development of Analog DFT methods must advance– Formalization of analog techniques and development of

fault models

24 July 2002 Work In Progress – Not for Publication

Test Software Standards Focus

• Standards for test equipment interface & communication are needed to decrease equipment factory integration time– Improve equipment interoperability to reduce factory

systems integration time – e.g, built into 300mm equipment specifications

• Standards for ATE software and test program generation are needed to decrease test development effort and improve time to market– Lower the barrier for selecting the optimal equipment

• Increased focus for standards development and adoption of existing standards

24 July 2002 Work In Progress – Not for Publication

How can we improve manageability of the divergence between

validation and manufacturing

equipment?

What happens when high speed serial interfaces become buses?

Can ATE instruments catch

up and keep up with high speed

serial performance

trends?

Will market dynamics justify development of next generation functional test capabilities?

Can DFT and BIST mitigate the mixed

signal tester capability treadmill?

What other opportunities exist?

How can we make test of complex

SOC designs more cost effective?

Will increasing test data volume lead to increased focus on

Logic BIST architectures? What

are the other solutions?

Can DFT mitigate analog

test cost as does in the digital

domain?What is the cost and capability

optimal SOC test approach?

24 July 2002 Work In Progress – Not for Publication

Test Implications of IP Design

• Test Strategy and Integration– DFT for IP Core Based Design

– Higher Level DFT

• Standardization

IP Core Based Design

LogicMCUMemoryControlDSPAnalog

BISR/BIRAPath Delay

BOSTTest Strategy Analog Isolation

Scan+ATPGIP Core Isolation BIST

24 July 2002 Work In Progress – Not for Publication

Automated DFT Insertion

• Automation of test control integration and test scheduling– Insert test wrapper and test control circuits

SoC

DFT

IP Core

Test Data

Chip-LevelTest Data

Test Wrapper

DFT

TestController

Test WrapperInsertion

Test DataConversion

Configuration of Chip-Level Test Controllerand Test Access Mechanism

24 July 2002 Work In Progress – Not for Publication

Memory 2001 2002 2003 2004 2005 2006 2007 2010 2013 2016

Parallel Testing

Index Time

Throughput

Temp. Control

Temp. Accuracy

Foot Print

32 to 64 64 to 128

3 to 5 2 to 5 2 to 4

6 to 8 8 to 10 8 to 12

-55 to 100

+/- 3 +/- 2 +/- 2 +/- 1.5

1 to 1.3 1.3 to 1.5

per head

Sec.

thousands / hour

degree

degree

ratio *2

*1

Note

Logic 2001 2002 2003 2004 2005 2006 2007 2010 2013 2016

4 8

0.3 to 0.4 to 0.25

4 to 6 8 to 12 12 to 20

Room Temp. to 125

+/- 3 +/- 2 +/- 2 +/- 1

1 1.2 *2

*1

Note

16

9 to14

1.4

Parallel Testing

Index Time

Throughput

Temp. Control

Temp. Accuracy

Foot Print

per head

Sec.

thousands / hour

degree

degree

ratio

*1 Though 128 become number of parallel testing after 2005 years, it is difficult to keep the temperature accuracy that 64 are the same as the number of parallel testing with memory handler.Therefore, it becomes yellow. Though 8 become number of parallel testing after 2004 years, it is difficult to keep the temperature accuracy that 4 are the same as the number of parallel testing with logic handler. Therefore, it becomes yellow.*2 It is expressed by the index number when 32 of parallel testing in 2001 is made 1. (Therefore, it becomes 1.3 by 64 of parallel testing in 2001.).

Preliminary Roadmap for Handlers

24 July 2002 Work In Progress – Not for Publication

Device flow

Tray flow

Tray

Loader UnLoader

JEDEC

Temp. control

Achieving the same temperature accuracy in handlers with 128 deviceshandled in parallel, as handlers with 64 will be very difficult and challenging.

Parallel testing

Memory 64 to 128 (2005)

Foot print

Considering the size of the handler needed to access the test floor, the test floor layout, and other transportation restrictions,

the handler width should not exceed 1.8 m.

Logic 4 to 8 (2004) to 16 (2010)

Make the handling faster.Make the conveyance distance shorter.More accurate positioning will make

the handling time shorter.

Test head

The test head size is becoming larger year by year.

Socket

DeviceHandler is required to handle

diversifying various kinds of packages.

Index time

Test frequency

Keep an electrical stable contact

Preliminary Roadmap for Handlers

24 July 2002 Work In Progress – Not for Publication

Electrical stable contact is one of key technologieson semiconductor device testing.

Important contact technologies:

　　 Probing contact for wafer testing 　　 Discussed in 2001　　 Socket contact for package testing　　 Proposal for 2002 discussion

Preliminary Roadmap for Sockets

24 July 2002 Work In Progress – Not for Publication

Molded board type 2001 2002 2003 2004 2005 2006 2007 2010 2013 2016Inductance

Contact strokeContact pressure

Contact resistanceGuarantee marginal value

3 to 8 2 to 80.3 to 0.5

20 to 4030

nH

mm

g

mOhm

durability

20 to 40

10000

Spring probe type2 to 8 1 to 8

0.3 to 0.520 to 40

15010000

New generation type1 to 8

0.1 to 0.3

3013 to 28

10000

0.313 to 40 13 to 28

10010000 10000

InductanceContact stroke

Contact pressureContact resistance

nH

mm

g

mOhm

durability

InductanceContact stroke

Contact pressureContact resistance

nH

mm

g

mOhm

durability

Note The performance has ripened and there is no big change. Contact pressure is difficult at lead free correspondence.

Note The limit over the diameter reduction of a terminal is in sight.

Note If opposite cost is taken into consideration, at a present stage, it is not practical.

2001 2002 2003 2004 2005 2006 2007 2010 2013 2016

2001 2002 2003 2004 2005 2006 2007 2010 2013 2016

Guarantee marginal value

Guarantee marginal value

* Guarantee marginal value : The number of times of a use limit which an offer company guarantees.

Preliminary Roadmap for Sockets

24 July 2002 Work In Progress – Not for Publication

A trend of Socket

Leaf spring type

Spring probe system

Surface mount type of stamping

Surface mount of stamping contact pin with rubber component Particle inter-connect

Barrel less type of spring probe pin

One side actuating type of spring probe pin

Leaf spring type

Film type Rubber type Micro-spring

Peripheral

Area Array

Need to develop novel contactor such as zero-force architecture forultra high pin counts (narrow pitch) and high speed device testing.

?

?

Preliminary Roadmap for Sockets

24 July 2002 Work In Progress – Not for Publication

Difficulty of test development for design & Virtual tester tech.

Virtual tester technology

Correct products?

Correct test program? Correct testequipment?

Difficulttriangular・・・・・

･ wrong wiring ･ miss relay control point ･ Ground noise ･ wrong parts･ probe card (inductance)･ reflection(missmatched Z)

・・・・・

･ imperfect circuit understanding･ not fix test spec.･ complex conditions of timing etc ････

Virtual test operation

De fac’to program description Test Board verification tech.

･ Tester resource problems(timing,pattern length, etc.)･ Tester limitation(clump)･Wait time・ Different tester

Modeling and Simulation

24 July 2002 Work In Progress – Not for Publication

Socket / Probe Test board

Tester

Formation of many pins

Formation of a special package

A large number are taken.

Workability, Speed

Conversion

Machine figure presentation, target electrical property presentation

Equivalent length wiring, target transmission impedance

Electric circuit parameter extraction

(Electro magnetic analysis)

Optimize wiring , Adjust processing

(Board analysis)

　　　　　　　　Concentration constant

(Comparator capacity, driver impedance)

It is overly high-speed testing.

High frequency Transition line consideration

Distributed Model, Tester Mode

(Tester transmission way analysis technology)

Test - Board

DUT- Tester transmission

DRCPx

SocketSmall board

Test board

Conversion board

Tester mother boardTester pin electronics

Socket/ Probe

Tester

Subject: socket / probe, a test board, and a tester

Even if each shows information, the whole test board verification is difficult.

Device

Output voltage, current regulation

(Voh,Vol,Ioh,Iol

Device improvement in the speed, customer situation consideration

　　(RAMBUS, cellular phone)

output SPICE and IBS model

(Customer board design consideration)

New business

The necessity for a model

Test board verification technology

High-speed tester (125MHz) test mode waveform analysis

Fig 2 T6672 Tester Ringing Countermeasure Method

L/ Ｒ　Ｃｉｒｃｕｉｔ Diode Clamp Circuit I-LOAD Circuit

ＣＰ

1V

6V

ＣＰ

24mA -24mA

3V

tr=2.0ns/tf=2.4ns tr=1.3ns/tf=1.8ns tr=2.3ns/tf=12.8ns

ＲSRL∽

25Ω

350mH

Block ring

Modeling and Simulation