ITRS Design ITWG 2009 1

Design and System Drivers - 2009

Worldwide Design ITWG

Key actions / messages:

1. Software, system level design productivity critical to roadmap2. Initiated reliability / resilience roadmap3. System-level design technology is key to power efficiency4. Design cost will be contained through innovation

ITRS Design ITWG 2009 2

Overview (2004-9)1. Increasingly quantitative roadmap2. Increasingly complete driver set

2004

2005

2006

2007

ExploreDesign metrics

Design Technology metrics

Revised Design metrics

Revised Design Technology Metrics

ConsumerPortableDriver

Consumer Stationary, PortableDrivers

Consumer Stationary,Portable,Networking Drivers

More Than Moore analysis + iNEMI

Driver study

System DriversChapter

DesignChapter

2008

Revised Design MetricsDFM extension

Updated Consumer Stationary,Portable,and Networking Drivers

More Than Moore extension+ iNEMI+ SW !!

2009

AdditionalDesign MetricsDFM ExtensionSystem level extension

Updated Consumer Stationary,Portable architecture,and Networking Drivers

More Than Moore extension+ iNEMI synch+ SW !!

ITRS Design ITWG 2009 3

ITRS Cost Chart 2009 (Millions of Dollars)

$21 $16 $21 $21 $31 $24 $33 $15 $22 $16 $20 $19 $26 $33 $45 $29 $40 $25 $33 $27 $37 $17 $22$2 $8 $12 $18 $9 $13$20

$24$39

$30 $41 $56$79

$34$47

$31$42

$27$35 $34

$47

$21 $29

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Total HW Engineering Costs + EDA Tool Costs Total SW Engineering Costs + ESDA Tool Costs

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ITRS Design ITWG 2009 4

System Level Design & SOFTWARE Hardware design productivity is growing appropriately

– Requirements correspond roughly with solutions– Innovations pacing properly (transistors / designer / year)

Large gap in software productivity possibly opening up– If hardware accelerators are heavily leveraged, problem mitigated– Otherwise, possibly 100X gap can affect memory size, other

Adding new parameters to requirements/solutions tables– Hardware design productivity - requirement– Software design productivity - requirement– Software design productivity (assuming only software implementation)– System design productivity innovations – solutions (Fig. 1 in chapter)

(alternative Scenario)

ITRS Design ITWG 2009 5

Impact of Design on PowerEmphasis on System Level [SW/HW]

ITRS Design ITWG 2009 6

Design and System Drivers - 2010

Worldwide Design ITWG

Key actions / messages:

1. Continue expanding importance of SW and system level2. Quantify design technology impact on variability, “sigma”

control in process3. Update “design cost control through innovation” chart4. Develop design technology roadmap for 3D / TSV5. Develop new set of Design requirements/solutions from MtM6. Complete reliability roadmap for 2011

ITRS Design ITWG 2009 7

Impact of Design on “Sigma” (Variability)

Manufacturing

Device

Circuit

Logic / function

System / SW

Use variability model

Goal Quantify “how many sigmas” can design “reduce”

Approach Inventory of design techniques / toolsMatch inventory to parameters or correlations in modelUse variability model to capture “delta” in sigmas

Inputs (manufacturing)

Check overall variation

ITRS Design ITWG 2009 8

More Than Moore (Design) More than Moore brings new set of requirements/solutions

– Will create additional inventory of parameters

Existing requirements Existing solutions

Additional requirements Additional solutions

E.g.– System-level (packaging) – Circuit (inter-chip parasitics modeling/simulation)– Layout (SiP global layout)– DFM (package-chip, SiP DFM)

Ex

isti

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Ad

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al

ITRS Design ITWG 2009 9

Design and System Drivers 2009

Worldwide Design ITWG

Key actions / messages:

1. Design update to ORTCs: SRAM, logic, defect density models2. Updated key system drivers: SOC-Consumer Portable, MPU3. Frequency-power envelope remains critical for industry 4. Updated System Drivers, no new drivers5. Expanded cross-TWG and public activity (DAC ’09 workshop)

ITRS Design ITWG 2009 10

Overview (2004-9)1. Increasingly quantitative roadmap2. Increasingly complete driver set

2004

2005

2006

2007

ExploreDesign metrics

Design Technology metrics

Revised Design metrics

Revised Design Technology Metrics

ConsumerPortableDriver

Consumer Stationary, PortableDrivers

Consumer Stationary,Portable,Networking Drivers

More Than Moore analysis + iNEMI

Driver study

System DriversChapter

DesignChapter

2008

Revised Design MetricsDFM extension

Updated Consumer Stationary,Portable,and Networking Drivers

More Than Moore extension+ iNEMI+ SW !!

2009

AdditionalDesign MetricsDFM ExtensionSystem level extension

Updated Consumer Stationary,Portable architecture,and Networking Drivers

More Than Moore extension+ iNEMI synch+ SW !!

ITRS Design ITWG 2009 11

ORTCs: New A-Factor Models(Area = A-factor F2)

Logic: A-factor = 175

NAND2 Area

= 3 PPoly 8 PM2

(3 1.5 PM1) (8 1.25 PM1)

= 45 (PM1)2

= 180 F2 175 F2

SRAM: A-factor = 60

SRAM Bitcell Area

= 2 PPoly 5 PM1

= 3 PM1 5 PM1= 15 (PM1)2

= 15 (2 F)2 = 60 F2

NWell

Contact

Active

M1

Poly

Contacted-poly pitch(PPoly 1.5PM1)

M2 pitch (PM2 1.25PM1)

Fitted to industry data

Contacted-poly pitch (PPoly 1.5PM1)

M1 pitch (PM1)

ITRS Design ITWG 2009 12

Key System Drivers Constantly Updated Consumer Driver Model 2008: Updated power model with realistic dynamic power

– Memory dynamic power 10X less than modeled previously

Will identify key driver requirements, explore coloring– E.g., excessive power beyond portable limit (1 W 0.5W)

Exploring RF/A/MS for future portable consumer drivers– Extends existing driver (or, future “wireless” driver is possible)

Exploring additional parameters per Test requests– #clocks, #power domains, #unique cores, #IOs, etc.

Figure 6 SoC Power Trends

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Trend: Memory Static Power Trend: Logic Static PowerTrend: Memory Dynamic Power Trend: Logic Dynamic PowerRequirement: Dynamic plus Static Power

8 W max total (2022) 4.3 W max total (2022)

Figure SYSD6 SOC Consumer Portable Power Consumption Trends

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Trend: Memory Static Power Trend: Logic Static Power

Trend: Memory Dynamic Power Trend: Logic Dynamic Power

Requirement: Dynamic plus Static Power

ITRS Design ITWG 2009 13

SOC Consumer Portable Architecture Model (updated)

MainMemory

PE-1

Peripherals

PE-2 PE-n…

MainPrc.

MainPrc.

MainPrc.

MainPrc.

Function A Function B Function C

Function D Function E

MainMemory PE

PE

PE

PE

PE

MainPrc.

PE

PE

PE

PE

PE

PE

PE

PE

PE Peripherals

MainPrc.

MainPrc.

MainPrc.

- #Main Processors grows to 2, 4 and beyond- Power budget reduced to 0.5W- Die size reduces slowly to 44mm2

ITRS Design ITWG 2009 14

Updated MPU Density/Power/Frequency

Physical Lgate (L)M1 Half-Pitch (F)

Decrease Pdyn and Pleak

Increase Pdyn , decrease Pleak

A-Factor (A) Logic: ~320 (WAS) 175 (IS) SRAM: ~100 (WAS) 60 (IS)

Increased Pdyn and Pleak

#core/die, #tr/core 12.2% / year (WAS) 18.9% / year (~2013, IS), 12.2% / year (2014~, IS)

Unit cell size Growth of #Tr 2x / 3 year (WAS) 2x / 2 year (IS) up to 2013 Die size reduction 310mm2 (WAS) 260mm2 (IS)

ITRS Design ITWG 2009 15

Design Pacing, Challenges Unabated

2009: Final Lgate and M1 HP scaling impact on Drivers

Updated MPU model (power)

Physical Lgate

M1 Half Pitch

1 year shift

2 year delay, but faster scaling0.7x / 3yr 0.7 / 2yr (~2013), 0.7x / 3yr (2014~)

#Tr per die

New A-factorsFaster M1 half pitch reduction

ITRS Design ITWG 2009 16

Frequency-Power Envelope Remains Critical System Issue

Current priorities Power #1 goal Frequency slowdown Multi-core enables

tradeoff

Need to track trade-off Market vigilance Yearly adjustment Possible 2009 survey

7.7% / year

~2013: 18.9% / year2014~: 12.2% / year

ITRS Design ITWG 2009 17

• 9:15am - 10:00am Plenary• The ITRS Semiconductor Industry Roadmap --- Alan K. Allan (Intel)

• 10:00am - noon Session I: EDA Roadmaps and Perspectives • The CATRENE (Europe) EDA Roadmap --- W. Rosenstiel (U. Tubingen)• The STRJ/WG1 (Japan) EDA Roadmap --- (STRJ representative)• The ITRS Design / System Drivers Roadmap – Carballo/Kahng (ITRS)• Synopsys Roadmap Perspective --- A. Domic (Synopsys) • Cadence Roadmap Perspective --- D. Noice (Cadence) • Mentor Roadmap Perspective --- R. Hum (Mentor) • Design Technology Coalition Perspective --- J. Darringer (IBM)• SI2 Perspective --- S. Dasgupta (SI2)• Mini-Panel Discussion: "Can We Roadmap EDA? For whom?”

• Noon - 1:30pm: Creating the Right EDA Industry Roadmap

DAC-2009 Roadmapping WorkshopSan Francisco, July 27, 2009 9am – 3pm 35 Attendees

ITRS Design ITWG 2009 18

Design and System Drivers 2010

Worldwide Design ITWG

Key actions / messages:

1. Update key system drivers: SOC-Consumer Portable, MPU2. Update frequency-power MPU roadmap3. Continue to broaden System Drivers, but more cautiously4. Develop new “MtM” System Driver parameters, “SIP fabric”5. Continue cross-TWG and public activity (DAC2010 workshop)6. Maintain iNEMI relationship/linkage around portable driver

ITRS Design ITWG 2009 19A&DNetwork ConsumerPortable

OfficeMedical Automotive ConsumerStationary

MPU

PE/DSP

AMS

Memory

Fabrics

Markets

20062007 2006 20062010?2010?

SIP

New System Drivers? At the right pace…

• New SIP Fabric driver effort started in 2009• Others (aerospace & defense, medical, auto, FPGA) deferred

2010?

ITRS Design ITWG 2009 20

More Than Moore Brings Alternative Set of Parameters (2010-) Will create additional inventory of parameters

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Power

NormalizedCost

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Performance

NormalizedCost

CONCEPT: Current SoC scenario vs. Additional SiP scenario

ITRS Design ITWG 2009 21

System Drivers and iNEMI (2009)Proposal to iNEMI: develop Portable System Architecture TemplateNew Chair with domain expertise – expect deeper commitment

Application processor

Baseband processor

MemoryNAND Flash

MemoryWireless

Flash

Audio / video codec

Power mgt.

I/O controller

I/O transceivers

Oth

er

(ME

MS

, etc

.)

ProcessingPOWER

Memory / FlashCOST

Analog / I/ONOISE SENSITIVITY

ITRS Design ITWG 2009 22

Design & Key ITRS Cross-TWG Initiatives

With Interconnect (A&P): 3D / TSV roadmapping survey

With PIDS, FEP, IRC: Power-driven roadmap; modeling and requirements support for CV/I RO-based transistor metric

With CSTNSG: Updated frequency, SRAM area, active area (yield) projects

With More Than Moore Study Group: Definition of SIP-scenario System Driver roadmaps to complement existing SOC-scenario Driver roadmaps

ITRS Design ITWG 2009 23

1. Update key system drivers: SOC-Consumer Portable, MPU2. Update frequency-power MPU roadmap3. Continue to broaden System Drivers, but more cautiously4. Develop new “MtM” System Driver parameters, “SIP fabric”5. Continue cross-TWG and public activity (DAC2010 workshop)6. Maintain iNEMI relationship/linkage around portable driver

Summary

1. Continue expanding importance of SW and system level2. Quantify design tech. impact on variability / “sigma” control3. Update “design cost control through innovation” chart4. Develop design technology roadmap for 3D / TSV5. Develop new set of Design requirements/solutions from MtM6. Complete reliability roadmap for 2011

Design Actions 2010

System Drivers Actions 2010