ITRS 2008 Update – April, Konigswinter, Germany 1 International Technology Roadmap for...

1

ITRS 2008 Update – April, Konigswinter, Germany

International Technology Roadmap for Semiconductors

2008 ITRS Update ORTC[ Konigswinter Germany ITRS ITWG Plenary]

A.Allan, Rev 2, [notes on IRC/CTSG More Moore, More than Moore, Beyond CMOS 04/04/08]

2


Preliminary Comments

“..the future ain’t what it used to be..” – Yogi Berra

“..the more things change, the more they remain the same..” – Jean-Baptiste Alphonse Karr

“..for everything there is a time..” – Solomon

“..I want what I want when I want it..” – the Customer

“..the customer is king..” – the Seller

3


2008 Update Definition of the Half Pitch[No single-product “node” designation; DRAM half-pitch still litho driver; however,

other product technology trends may be drivers on individual TWG tables]

Poly Pitch

Typical flash Un-contacted Poly

FLASH Poly Silicon ½ Pitch = Flash Poly Pitch/2

8-16 Lines

Metal Pitch

Typical DRAM/MPU/ASIC Metal Bit Line

DRAM ½ Pitch = DRAM Metal Pitch/2

MPU/ASIC M1 ½ Pitch = MPU/ASIC M1 Pitch/2

Source: 2005 ITRS - Exec. Summary Fig 2

2008 - Unchanged

4


Production Ramp-up Model and Technology Cycle Timing

Vo

lum

e (P

arts

/Mo

nth

)

1K

10K

100K

Months0-24

1M

10M

100M

Alpha

Tool

12 24-12

Development Production

Beta

Tool

Production

Tool

First

Conf.

Papers

First Two Companies

Reaching Production

Vo

lum

e (W

afer

s/M

on

th)

2

20

200

2K

20K

200K

Source: 2005 ITRS - Exec. Summary Fig 3

Fig 32008 - Unchanged

5


Agenda• Pre-Summary

• MPU Gate Length Technology Trends Update

• Summary

• Backup– Frequency– Bohr URL– SICAS

6


ORTC Pre-Summary – 2008 Update• Flash Model un-contacted poly half-pitch trend

– Unchanged 2-year cycle* through 2008/45nm, then 3-year cycle* (2014/22.5; 2020/11.25); ;– Unchanged: Cell Design Factor; Array Efficiency; Bits/Chip– PIDS Flash Survey Team to report status of survey data update and proposals in April meetings.

• Inui-san report:– No Change to number; Floating Gate to Charge from 2010 to 2011; 3D structure from 2013 to 2018– NAND 2 MLC to 4MLC 2010; possible 3 bits/cell – need inputs from additional companies– Recommend Litho Overlay 33%; LWR 12% of CD (Half-Pitch based) [no change to Litho drivers]

• DRAM Model stagger-contacted M1 half-pitch updated to the MPU 2.5-year cycle* through 2010/45nm, then

– Unchanged 3-year cycle* beginning 2010/45nm (2016/22.5; 2022/11.25); – Unchanged: Cell Design Factor; Array Efficiency; Bits/Chip

• DRAM function size, function density, and chip size models have been updated to latest Product 2.5-year cycle scaling rate;

– Only 2007-2009 years affected in 2008 Table Update. – Unchanged 2010-2022

• MPU Model M1 stagger-contact half-pitch unchanged from 2007– 2.5-year cycle* through 2010/45nm, then 3-year cycle* (2016/22.5; 2022/11.25).

• MPU/ASIC Printed Gate Length Updated – Unchanged 3-year cycle through 2018, – then 3.8-year cycle* 2019-2022.

• MPU/ASIC High-Performance Physical Gate Length – 3.8-year cycle* beginning 2007. – Declining printed/etch ratio – need FEP and Litho TWGs to agree on new annual ratios– Slower unchanged On-Chip Frequency trend (8% trend) was set by Design TWG in 2007 ITRS ORTC) -

need updated transistor and design model alignment by PIDS, FEP, and Design.– New drivers will be Ion/W, CV/I – possibly add to ORTC – need PIDS and FEP 2008 Update and

provide ORTC line items.* ITRS Cycle definition = time to .5x linear scaling every two cycle periods]

7


ORTC Pre-Summary – 2008 Update (cont.)• MPU/ASIC Low Operating Power Printed Gate Length

– Two-year delay 2007 from High Performance; one-year delay 2008-2012; and no delay 2013-2022.

• MPU/ASIC Low Standby Power Physical Gate Length [add to ORTC 1a,b]– No Change 2007, 2008; two-year delay 2009-2011 from High Performance; one-year delay in

2012; and no delay 2013-2022.• Also, one decimal place rounding was added to all ORTC 1a,b from 2016-2022

• New 2008 “Moore’s Law and More” Working Groups and Definitions Work : – “More Moore” (“Moore’s Law;” typically digital computing) Functional and Performance scaling is

enabled by both “Geometrical” and also “Equivalent” scaling technologies; Design “Equivalent Scaling” to be added in 2008

– More than Moore “Functional diversification” text will be impacted (typically non-digital sensing, interacting) system board-level migration/miniaturization is enabled by system-in-package and system-on-chip

– “Beyond CMOS” definition and timing range will be added, focused on the Logic Switch transition at “Ultimately Scaled CMOS”

• The average of the industry product “Moore’s Law” (2x functions/chip per 2 years) rate forecast to continue throughout the latest 2007-2022 ITRS timeframe

• Total MOS Capacity (SICAS) growing at ~16% CAGR (SICAS); new “<80nm” data split out; and 300mm Capacity Demand has ramped to 33% of Total MOS

• Industry Technology Capacity Demand (SICAS) – [3Q,4Q07 published status] continues on a on 2-year cycle* rate at the leading edge.

8


Technology Trends vs Actuals and Survey

0.1

1

10

100

1000

2000 2005 2010 2015 2020 2025

Year

(nm

, nm

/ua,

ua,

pic

o-s

ec)

Jeff Butterbaugh/FEPActuals (leading):

Kwok Ng/PIDS Survey(leading): [Ng/HP]:

M1 Half Pitch(nm) MPU(ITRS 05-07)

Glpr(nm) MPU (ITRS 05-07)

Glph(nm) MPU (ITRS 05-07)

2007 ITRS: 2007-2022

M1 Half-pitch& GLphysical =0.7071x/ 3yrs=0.8909x/yr=0.5x/6yrs

GLphysical =~0.71x/ 3.8yrs

=0.9073/yr=~0.5x/7.6yrs

Source: 2007 ITRS www.itrs.net

9



0.1

1

10

100

1000

2000 2005 2010 2015 2020 2025

Year

(nm

, nm

/ua,

ua,

pic

o-s

ec)






2007 ITRS: 2007-2022

2005 ITRS: 2005-2019

1 / Ion =0.76x/ 3yrs=0.9117/yr=0.57x/6yrs


x

1 / Ion Factor =1.07x/ 3yrs=1.02335/yr =


=0.9073/yr=~0.5x/7.6yrs

1 /Ion Factor= 0.99/3.8yrs

= 0.70 / 3.8yrs = 1 /Ion for previous 1.17x/yr On-Chip Frequency.What is the Factor for 2007 ITRS 1.08x/yr On-Chip Freqencyand 0.71x/3.8yrs GLphysical?

GLphysical= 0.71/3.8yrs

1/Ion n-channel

1/Ion p-channel

Source: 2007 ITRS www.itrs.net ; Bouef et al VLSI 2007

10



0.1

1

10

100

1000

2000 2005 2010 2015 2020 2025

Year

(nm

, nm

/ua,

ua,

pic

o-s

ec)






I p (ua)

I n (ua)

CV/I (ps) [AA estimatefrom Boeuf VLSI Foil]

2007 ITRS: 2007-2022

2005 ITRS: 2005-2019

1 / Ion =0.76x/ 3yrs=0.9117/yr=0.57x/6yrs


x

1 / Ion Factor =1.07x/ 3yrs=1.02335/yr =


=0.9073/yr=~0.5x/7.6yrs

1 /Ion Factor= 0.99/3.8yrs

= 0.70 / 3.8yrs = 1 /Ion for previous 1.17x/yr On-Chip Frequency.What is the Factor for 2007 ITRS 1.08x/yr On-Chip Freqencyand 0.71x/3.8yrs GLphysical?

GLphysical= 0.71/3.8yrs

1/Ion n-channel

1/Ion p-channel

I n,p (ua)=~0.71x/ 8.8yrs

=0.9616/yr =~0.5x/19.6yrs

Source: 2007 ITRS www.itrs.net ; Bouef et al VLSI 2007

1/(CV/I ) trend = 1 / 0.855x per yr =~1.17x per year

= Ionn,p / Wn,p

11


ORTC Summary – 2008 Update• Flash Model un-contacted poly half-pitch trend

– Unchanged 2-year cycle* through 2008/45nm, then 3-year cycle* (2014/22.5; 2020/11.25); ;– Unchanged: Cell Design Factor; Array Efficiency; Bits/Chip– PIDS Flash Survey Team to report status of survey data update and proposals in April meetings.

• Inui-san report:– No Change to number; Floating Gate to Charge from 2010 to 2011; 3D structure from 2013 to 2018– NAND 2 MLC to 4MLC 2010; possible 3 bits/cell – need inputs from additional companies– Recommend Litho Overlay 33%; LWR 12% of CD (Half-Pitch based) [no change to Litho drivers]

• DRAM Model stagger-contacted M1 half-pitch updated to the MPU 2.5-year cycle* through 2010/45nm, then

– Unchanged 3-year cycle* beginning 2010/45nm (2016/22.5; 2022/11.25); – Unchanged: Cell Design Factor; Array Efficiency; Bits/Chip

• DRAM function size, function density, and chip size models have been updated to latest Product 2.5-year cycle scaling rate;

– Only 2007-2009 years affected in 2008 Table Update. – Unchanged 2010-2022

• MPU Model M1 stagger-contact half-pitch unchanged from 2007– 2.5-year cycle* through 2010/45nm, then 3-year cycle* (2016/22.5; 2022/11.25).

• MPU/ASIC Printed Gate Length Updated – Unchanged 3-year cycle through 2018, – then 3.8-year cycle* 2019-2022.

• MPU/ASIC High-Performance Physical Gate Length – 3.8-year cycle* beginning 2007. – Declining printed/etch ratio – need FEP and Litho TWGs to agree on new annual ratios– Slower unchanged On-Chip Frequency trend (8% trend) was set by Design TWG in 2007 ITRS ORTC) -

need updated transistor and design model alignment by PIDS, FEP, and Design.– New drivers will be Ion/W, CV/I – possibly add to ORTC – need PIDS and FEP 2008 Update and

provide ORTC line items.* ITRS Cycle definition = time to .5x linear scaling every two cycle periods]

12


ORTC Summary – 2008 Update (cont.)• MPU/ASIC Low Operating Power Printed Gate Length

– Two-year delay 2007 from High Performance; one-year delay 2008-2012; and no delay 2013-2022.

• MPU/ASIC Low Standby Power Physical Gate Length [add to ORTC 1a,b]– No Change 2007, 2008; two-year delay 2009-2011 from High Performance; one-year delay in

2012; and no delay 2013-2022.• Also, one decimal place rounding was added to all ORTC 1a,b from 2016-2022

• New 2008 “Moore’s Law and More” Working Groups and Definitions Work : – “More Moore” (“Moore’s Law;” typically digital computing) Functional and Performance scaling is

enabled by both “Geometrical” and also “Equivalent” scaling technologies; Design “Equivalent Scaling” to be added in 2008

– More than Moore “Functional diversification” text will be impacted (typically non-digital sensing, interacting) system board-level migration/miniaturization is enabled by system-in-package and system-on-chip

– “Beyond CMOS” definition and timing range will be added, focused on the Logic Switch transition at “Ultimately Scaled CMOS”

• The average of the industry product “Moore’s Law” (2x functions/chip per 2 years) rate forecast to continue throughout the latest 2007-2022 ITRS timeframe

• Total MOS Capacity (SICAS) growing at ~16% CAGR (SICAS); new “<80nm” data split out; and 300mm Capacity Demand has ramped to 33% of Total MOS

• Industry Technology Capacity Demand (SICAS) – [3Q,4Q07 published status] continues on a on 2-year cycle* rate at the leading edge.

13


ORTC Pre-Summary – 2008 Update (cont.)• More than Moore [discussion leader – Mart Graef also see

Backup for additional MtM presentation information]– Objective:

Define and quantify value-adding parameters for functional diversification

• Identify/elaborate Technical Parameters• Added Value to the target application• Usual ITRS goals: Grand Challenges, Potential Solutions, narrowing

over time• Pitfall(Design TWG comment): line item doesn’t “fit”• May need to “tweak” to “fit” the MtM taxonomy• Key parameters for MtM examples in marketplace

– Involve IRC/ITWGs• A&P, Design, RF/AMS, Test, Interconnect, but open to other TWGs• Key Categories to address: Sensors, Actuators (MEMS, Optical)

– Key Issue differentiating “MtM”: Integration– Next Meeting will be called by Mart Graef

• TWGs notify Mart of their participant at the April ITRS meeting

More than Moore Study Group 4/3/08

14


Design TWG Proposed “More Moore” and “MtM” Text, 3 apr 2008 Plenary v2a[discussion leader – Andrew Kahng]• 1 = More Moore

– 1a = geometric scaling– 1b = equivalent scaling– 1c = Design equivalent scaling– NEED: quantifiable, specific Design Technologies that deal with More Moore

– “Design equivalent scaling occurs in conjunction with Equivalent Scaling and continued Geometric Scaling, and refers to design technologies that enable high performance, low power, high reliability, low cost, and high design productivity.”

– “Examples (not exhaustive) are: Design for variability; low power design (sleep modes, hibernation, clock gating, multi-VDD, ...); and homogeneous and heterogeneous multicore SOC architectures.”

– Request: Please remove “b) Multi-core MPU architecture” from 2 (MTM Functional Diversification)

• 2 = More than Moore– NEED: Design technologies to enable functional diversification

– “Design technologies enable new functionality that takes advantage of More than Moore technologies.”

– “Examples (not exhaustive) are: Heterogeneous system partitioning and simulation; software; analog and mixed signal design technologies for sensors and actuators; and new methods and tools for co-design and co-simulation of SIP, MEMS, and biotechnology.”

More than Moore Study Group 4/3/08

ORTC Pre-Summary – 2008 Update (cont.)

15


ORTC Summary – 2008 Update• MPU/ASIC High-Performance Physical Gate Length [discussion leader – A.Allan]

– 3.8-year cycle* beginning 2007. – Declining printed/etch ratio – need FEP and Litho TWGs to agree on new annual ratios– Slower unchanged On-Chip Frequency trend (8% trend) was set by Design TWG in 2007 ITRS

ORTC) - need updated transistor and design model alignment by PIDS, FEP, and Design.– New drivers will be Ion/W, CV/I – possibly add to ORTC – need PIDS and FEP 2008 Update

and provide ORTC line items.– Thomas Scotnicki review of Paper and VLSI presentation (see Scotnicki files)

• Discrepancy between measured vs ITRS model• Andrew Kahng review – what interconnect capacitance assumed (~zero in ring oscillators)• Proposal for 3 changes to

– 17% not needed, 8% is enough (due to increased 1 core to 2 core architecture performance)– Variability not taken into account (no manufacturing flexibility) PIDS recommendation

» MASTAR Random Generator– Variability vs Device Structure– Not a model problem/limitation – need decision

» Not supporting 1/Ion; Want CV/I

– Paolo Gargini Review of “Equivalent Scaling Knobs” for Performance/Power tradeoffs• Smaller changes on 5 “knobs” (including Strain, Hik/MetGate, etc) vs historical 2 knobs (Oxide Thickness,

Gate Length)• More complex modeling options using Mobility, Dielectric Constant, Voltage “indicators”

– “equivalent channel length” possible approach• Andrew Kahng – please advise how to share the investment in manufacturing solutions (“knobs”)?

• Beyond CMOS [discussion leader – Jim Hutchby]• “new switch” (asterick “information processing” including interconnect and memory);• Logic switch -> SIA/NRI “invent the new switch”• Graphics need a new color• ERD/ERM (Jim Hutchby, Mike Garner); PIDS (Kwok Ng, Thomas Skotnicki); Design (Andrew Kahng; Juan-

Antonio Carballo)

More Moore Study Group 4/3/08

Beyond CMOS Study Group 4/3/08

16


Backup

- On-chip Frequency Update- Bohr “Tutorial” URL- More than Moore Study Group Kickoff presentation- SICAS 3Q/4Q07 Update

17


18


Mark Bohr "Silicon Technology Tutorial" :

http://intel_im.edgesuite.net/2008/123085/IM2008_Bohr.pdf

….Etc.

19


More than Moore

ITRS Spring Meeting 2008

Königswinter, Germany, Rev 1

[Mart Graef]

MtM StudyGroup 4/3/08

20


Source: 2005 ITRS Document online at: http://www.itrs.net/Links/2005ITRS/Home2005.htm

Moore’s Law & MoreMore than Moore: Diversification

Mo

re M

oo

re:

Min

iatu

riza

tio

nM

ore

Mo

ore

: M

inia

turi

zati

on

Combining SoC and SiP: Higher Value SystemsBas

eli

ne

CM

OS

: C

PU

, M

emo

ry,

Lo

gic

BiochipsSensors

ActuatorsHV

PowerAnalog/RF Passives

130nm

90nm

65nm

45nm

32nm

22nm...V

130nm

90nm

65nm

45nm

32nm

22nm...V

Information Processing

Digital contentSystem-on-chip

(SoC)

Interacting with people and environment

Non-digital contentSystem-in-package

(SiP)

Beyond CMOS

Sca

lin

g (

Mo

re M

oo

re)

Functional Diversification (More than Moore)

Continuing SoC and SIP: Higher Value Systems


21


2007 ITRS “Moore’s Law and More” Definition Graphic Proposal

Computing &Data Storage

Heterogeneous IntegrationSystem on Chip (SOC) and System In Package (SIP)

Sense, interact, Empower

BaselineCMOS Memory RF HV

PowerPassives Sensors,

ActuatorsBio-chips,Fluidics

“More Moore”

“More than Moore”

Source: ITRS, European Nanoelectronics Initiative Advisory Council (ENIAC)


22


• “More Moore”: ScalingContinued shrinking of physical feature sizes of the digital functionalities (logic and memory storage) in order to improve density (cost per function reduction) and performance (speed, power).

• “More than Moore”: Functional DiversificationIncorporation into devices of functionalities that do not necessarily scale according to "Moore's Law“, but provide additional value in different ways. The "More-than-Moore" approach allows for the non-digital functionalities to migrate from the system board-level into the package (SiP) or onto the chip (SoC).

• The Challenge: Integration of MM with MtMCreation of intelligent compact systems.

“More Moore” and “More than Moore”MtM Study

Group 4/3/08

23


Following Moore’s Law is one approach:

Monolithic CMOS logic System-on-Chip

PowerSensor

Actuator

Storage

Processor

Radio

Advantage:-Smallest footprint

Disadvantage:-Limited functionality

More Moore

MtM Study Group 4/3/08

24


Adding More-than-Moore is another:System-on-Chip and System-in-Package

PowerSensor

Actuator

Storage

Processor

Radio

Advantage:-Full functionality

Disadvantage:-Complex supply chain

More than Moore

More Moore


25


Proposal for MtM Study Group• Objective:

Define and quantify value-adding parameters for functional diversification– Identify/elaborate Technical Parameters– Added Value to the target application– Usual ITRS goals: Grand Challenges, Potential Solutions,

narrowing over time– Pitfall(Design): line item doesn’t “fit”

• May need to “tweak” to “fit” the MtM taxonomy– Key parameters for MtM examples in marketplace

• Involve IRC/ITWGs– A&P, Design, RF/AMS, Test, Interconnect, but open to other TWGs– Key Categories to address: Sensors, Actuators (MEMS, Optical)

• Key Issue differentiating “MtM”: Integration• Next Meeting will be called by Mart Graef

– TWGs notify Mart of their participant at the April ITRS meeting


26


Design TWG Proposed MTM Text, 3 apr 2008 Plenary v2a• 1 = More Moore

– 1a = geometric scaling– 1b = equivalent scaling– 1c = Design equivalent scaling– NEED: quantifiable, specific Design Technologies that deal with More Moore

– “Design equivalent scaling occurs in conjunction with Equivalent Scaling and continued Geometric Scaling, and refers to design technologies that enable high performance, low power, high reliability, low cost, and high design productivity.”

– “Examples (not exhaustive) are: Design for variability; low power design (sleep modes, hibernation, clock gating, multi-VDD, ...); and homogeneous and heterogeneous multicore SOC architectures.”

– Request: Please remove “b) Multi-core MPU architecture” from 2 (MTM Functional Diversification)

• 2 = More than Moore– NEED: Design technologies to enable functional diversification

– “Design technologies enable new functionality that takes advantage of More than Moore technologies.”

– “Examples (not exhaustive) are: Heterogeneous system partitioning and simulation; software; analog and mixed signal design technologies for sensors and actuators; and new methods and tools for co-design and co-simulation of SIP, MEMS, and biotechnology.”

More Moore Study Group 4/3/08

27


SICAS Update (www.sia-online.org )MOS Capacity by Technology

0.0

200.0

400.0

600.0

800.0

1000.0

1200.0

1400.0

1600.0

1800.0

2000.0

1Q05

2Q05

3Q05

4Q05

1Q06

2Q06

3Q06

4Q06

1Q07

2Q07

3Q07

4Q07

Year

(000

's w

spw

)

0.7µm

<0.7µm to 0.4µm

<0.4µm to 0.3µm

<0.3µm to 0.2µm

<0.2µm to 0.16µm

<0.16µm to 0.12µm

<0.12µm

<0.12µm to 0.08µm

<0.08µm

15.5% CAGR

59.7% CAGR

Source: SICAS www.sia-online.org, ca

28


SICAS Update (www.sia-online.org )MOS Capacity by Dimensions

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

1Q05

2Q05

3Q05

4Q05

1Q06

2Q06

3Q06

4Q06

1Q07

2Q07

3Q07

4Q07

WS

pW

x 1

000

0.7µm

<0.7µm to0.4µm

<0.4µm to0.3µm

<0.3µm to0.2µm

<0.2µm to0.16µm

<0.16µm to0.12µm

<0.12µm

<0.12µm to0.08µm

<0.08µm

["65nm" ITRS Technology CycleIntro Year: 2007]

[2-yr SICAS Data Technology CycleIntro Year: 2006]

1-yr Ramp to 20-30%

"90nm" "65nm"~0.7x

Source: SICAS www.sia-online.org, ca

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