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30 Years of RF SOI Past, Present and Future · 2019. 11. 27. · • FET stacking allows...

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A Murata Company Jim Cable 17 Sept. 2019 30 Years of RF SOI Past, Present and Future
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Page 1: 30 Years of RF SOI Past, Present and Future · 2019. 11. 27. · • FET stacking allows UltraCMOS® technology to handle high RF power levels (>+40 dBm) – Higher power handling

A Murata Company

Jim Cable17 Sept. 2019

30 Years of RF SOI Past, Present and Future

Page 2: 30 Years of RF SOI Past, Present and Future · 2019. 11. 27. · • FET stacking allows UltraCMOS® technology to handle high RF power levels (>+40 dBm) – Higher power handling

2Copyright © pSemi Corporation. All rights reserved. 25 September 2019

Murata Facts and Figures

Our BusinessWe are worldwide leaders in the design, manufacture and supply of semiconductors, electronic components and solutions. We are Innovators in Electronics.

Our Strengths• Advanced RF, mixed signal and materials technology• Broad and vertically integrated product portfolio• Extensive global manufacturing and sales network

Our Figures• Net sales 14 billion USD* • Employees 77,751* • Number of locations 102* (30 in Japan, 72 overseas)• Established in 1944

*as of March 31, 2019

Page 3: 30 Years of RF SOI Past, Present and Future · 2019. 11. 27. · • FET stacking allows UltraCMOS® technology to handle high RF power levels (>+40 dBm) – Higher power handling

3Copyright © pSemi Corporation. All rights reserved. 25 September 2019

Vision to Reality – CMOS Won

UltraCMOS®

Integrated RF Front End

ConventionalRF Front End

CMOSTransceiver

AntennaSwitches

RFFETuning

MMMBSwitches

Low NoiseAmplifiers

Tunable Filters

mmWaveRFFE

Timeline of Key Innovations

Our Vision

Sampling

In Production

Power Amplifiers

20202000

Page 4: 30 Years of RF SOI Past, Present and Future · 2019. 11. 27. · • FET stacking allows UltraCMOS® technology to handle high RF power levels (>+40 dBm) – Higher power handling

4Copyright © pSemi Corporation. All rights reserved. 25 September 2019

Combining the Best of the BestHighly

Insulating SubstrateSAPPHIRE + HR SILICON

• Proven SOI Technology

• Outstanding RF Properties

• RF + Digital + Analog + Passive Integration

Most Widely UsedSemiconductor Technology

CMOS• Scalable

• Lowest Power and Cost

• Fabless Model

Combining the Best of the Best• Unique Position in Industry• Better Performance• Highly Scalable• Enables Integration• Proven Global Fabless Model

Industry-leading RF Semiconductor Technology

+

Page 5: 30 Years of RF SOI Past, Present and Future · 2019. 11. 27. · • FET stacking allows UltraCMOS® technology to handle high RF power levels (>+40 dBm) – Higher power handling

5Copyright © pSemi Corporation. All rights reserved. 25 September 2019

Cgd

Cgs

Cbd

Cbs

gbsgdsgm

Cgd

Cgs

Cgb

gdb

rd

rs

Gate Bulk

Source

Drain

The small signal model is simplified with the removal of the shaded elements associated

with the bulk node.

• Reduced bulk parasitics• Fully-depleted is preferred for no kink effect• Faster devices• Reduced CV2f power loss• Improved linearity• High isolation• High passive Q

Why CMOS Won – UltraCMOS® Technology

Sapphire Substrate Eliminates Bulk Nonlinear Capacitances

Page 6: 30 Years of RF SOI Past, Present and Future · 2019. 11. 27. · • FET stacking allows UltraCMOS® technology to handle high RF power levels (>+40 dBm) – Higher power handling

6Copyright © pSemi Corporation. All rights reserved. 25 September 2019

• FET stacking allows UltraCMOS® technology to handle high RF power levels (>+40 dBm)

– Higher power handling will NOT degrade performance– Stacking creates a virtual high-voltage CMOS FET that can handle high power levels

• High power handling requires low-loss, insulating substrate– Bulk-CMOS will not work due to conducting substrate

What Does RF SOI Enable?

Page 7: 30 Years of RF SOI Past, Present and Future · 2019. 11. 27. · • FET stacking allows UltraCMOS® technology to handle high RF power levels (>+40 dBm) – Higher power handling

7Copyright © pSemi Corporation. All rights reserved. 25 September 2019

Fundamental Technical Problems: Innovation Required

-2 -1 0 1 2-3 3

2E-12

3E-12

4E-12

1E-12

5E-12

vdc

Cbulk

Csoi

• Bulk CMOS accumulates in deep subthreshold because of hole source from P+ well contact

• SOS will accumulate from EHP generation (thermal/light/etc.)

• Charged is trapped in channel by reverse-biased PN junctions

– Forms anti-series diodes • Creates harmonics with RF excitation

– Charge sloshing

SOI Accumulation Capacitance and Charge

Simulated charge accumulationwith RF signal present

Page 8: 30 Years of RF SOI Past, Present and Future · 2019. 11. 27. · • FET stacking allows UltraCMOS® technology to handle high RF power levels (>+40 dBm) – Higher power handling

8Copyright © pSemi Corporation. All rights reserved. 25 September 2019

-120

-115

-110

-105

-100

-95

-90

-85

-80

0 50 100 150 200

IMD

3 (d

Bm

)

Relative phase @ f=1.76GHz

IM3 vs Relative Phase between Duplexer and SwitchPTX = +20 dBm, PBL= -15 dBm

PE4263 IMD3 HaRP 4263 IMD3

IM3 Specification

GSM Cell

WCDMA Phone> 25 dBm

3GPP Intermodulation Specification

HaRP™ Invention: Linearity Breakthrough

SP6T SP6T + HaRP™ Technology

Interference

Page 9: 30 Years of RF SOI Past, Present and Future · 2019. 11. 27. · • FET stacking allows UltraCMOS® technology to handle high RF power levels (>+40 dBm) – Higher power handling

9Copyright © pSemi Corporation. All rights reserved. 25 September 2019

HaRP™ Technology Impact

2010 Today

Cellular Switch Market Share

Today & Tomorrow

SOI GaAs

2005Before HaRP™

Page 10: 30 Years of RF SOI Past, Present and Future · 2019. 11. 27. · • FET stacking allows UltraCMOS® technology to handle high RF power levels (>+40 dBm) – Higher power handling

10Copyright © pSemi Corporation. All rights reserved. 25 September 2019

UltraCMOS® Technology Evolution

9,000 Gross Die per 6” Wafer150 mm

200 mm

300 mm>25,000 Gross Die per 8” Wafer

>85,000 Gross Die per 12” Wafer

60% smaller 20x better linearity

50% smaller 10x better linearity

25% smaller 4x better linearity

60 nm

130 nm

0.35 μm

Page 11: 30 Years of RF SOI Past, Present and Future · 2019. 11. 27. · • FET stacking allows UltraCMOS® technology to handle high RF power levels (>+40 dBm) – Higher power handling

11Copyright © pSemi Corporation. All rights reserved. 25 September 2019

UltraCMOS® Technology IP: Value to the Industry

TOP10Semiconductor Manufacturing

Patent Power Scorecard 2017

Company by Pipeline Power

Page 12: 30 Years of RF SOI Past, Present and Future · 2019. 11. 27. · • FET stacking allows UltraCMOS® technology to handle high RF power levels (>+40 dBm) – Higher power handling

12Copyright © pSemi Corporation. All rights reserved. 25 September 2019

THE FUTURE: Appears We Were Right

• Monolithic multichannel FULLY Integrated RF Front End– 28 GHz and 39 GHz

8-Channel mmW RFFE – Sampling

RFFE = SOI Our Foreseeable Future

Page 13: 30 Years of RF SOI Past, Present and Future · 2019. 11. 27. · • FET stacking allows UltraCMOS® technology to handle high RF power levels (>+40 dBm) – Higher power handling

THANK YOU


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