32-BIT MICROCONTROLLER MB91270 Series ......Purchase of Fujitsu I2C components conveys a license...

FUJITSU SEMICONDUCTORCONTROLLER MANUAL

FR60Lite32-BIT MICROCONTROLLER

MB91270 SeriesHARDWARE MANUAL

CM71-10128-2E

FUJITSU LIMITED

FR60Lite32-BIT MICROCONTROLLER

MB91270 SeriesHARDWARE MANUAL

“Check Sheet” is seen at the following support page

URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html

“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development.

Be sure to refer to the “Check Sheet” for the latest cautions on development.

PREFACE

■ Purpose of this document and intended readerWe sincerely thank you for your continued use of Fujitsu semiconductor products.

The MB91270 series is shingle chip microcontroller that builds various I/O resources and the bus control

mechanisms into by using 32-bit efficient RISC CPU for the built-in control being demanded for CPU

processing high performance/high-speed. Because the vast address space that 32 bits CPU access is

supported, the external bus access is basically. To speed up CPU instruction execution, MB91270 series

has built-in RAM of 24KB (for data).

This series is optimized to the embedded applications; automotive applications such as car audio or car air-

conditioning equipment that require high-performance CPU processing power.

The MB91270 series power-up the bus access based on FR30/40 family CPU, and is FR60Lite family

corresponding to use at high speed.

This manual describes the functions and operations of the MB91270 Series for engineers who develop

products using the MB91270 Series. Please read through this manual.

For more information on various instructions, refer to "Instruction Manual".

Note: FR is the abbreviation of FUJITSU RISC CONTROLLER, which is a product of Fujitsu.

■ TrademarksThe company names and brand names herein are the trademarks or registered trademarks of their respective

owners.

■ I2C license

Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these

components in an I2C system provided that the system conforms to the I2C Standard Specification as

defined by Philips.

■ Organization of this documentThis manual contains the following 27 chapters and appendix.

CHAPTER 1 OVERVIEW

FR family is a standard single-chip microcontroller that has a 32-bit high-performance RISC CPU as wellas built-in I/O resources and bus control mechanisms for embedded controller requiring high-performance and high-speed CPU processing.

CHAPTER 2 HANDLING DEVICES

This chapter provides precautions on handling the FR family.

CHAPTER 3 CPU and CONTROL UNIT

This chapter provides basic information required to understand the CPU core functions of FR family. Itcovers architecture, specifications, and instructions.

CHAPTER 4 RESET

This chapter describes reset.

CHAPTER 5 EXTERNAL BUS INTERFACE

The external bus interface controller controls the interfaces with the internal bus for chips and withexternal memory and I/O devices. This chapter explains each function of the external bus interface and itsoperation.

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CHAPTER 6 I/O PORT

This chapter describes the I/O ports and the configuration and functions of registers.

CHAPTER 7 INTERRUPT CONTROLLER

This chapter describes the overview of the interrupt controller, the configuration and functions ofregisters, and interrupt controller operation.

CHAPTER 8 EXTERNAL INTERRUPT

This chapter describes the overview of the external interrupt, the configuration and functions of registers,and operation of the external interrupt.

CHAPTER 9 REALOS-RELATED HARDWARE

REALOS-related hardware is used by the real-time OS. Therefore, when REALOS is used, the hardwarecannot be used with the user program.

CHAPTER 10 DMA CONTROLLER (DMAC)

This chapter describes the overview of the DMA controller (DMAC), the configuration and functions ofregisters, and DMAC operation.

CHAPTER 11 CAN CONTROLLER

This chapter explains the functions and operations of CAN controller.

CHAPTER 12 LIN-UART

This chapter explains functions and operation of LIN-UART.

CHAPTER 13 I2C INTERFACE

This chapter describes the outline of the I2C interface, the configuration and functions of registers, and

I2C interface operation.

CHAPTER 14 16-BIT RELOAD TIMER

This chapter explains register configuration/ function and timer operation of 16-bit reload timer.

CHAPTER 15 16-BIT FREE-RUN TIMER

This chapter describes the functions and operation of the 16-bit free-run timer.

CHAPTER 16 INPUT CAPTURE

This chapter describes the function and operation of the input capture.

CHAPTER 17 OUTPUT COMPARE

This chapter explains functions and operation of the output compare.

CHAPTER 18 PPG TIMER

This chapter describes the PPG timer.

CHAPTER 19 UP/DOWN COUNTER

This chapter describes the function and operation of 8/16-bit up/down counter.

CHAPTER 20 CLOCK MONITOR

This chapter explains the functions and operation of clock monitor.

CHAPTER 21 REAL TIME CLOCK

This chapter describes the register structure and functions of the Real Time Clock (hereafter, referred toas RTC) and describes the operation of RTC module.

CHAPTER 22 A/D CONVERTER

This chapter explains the overview of the A/D converter, the configuration/function of the register, andits operation.

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CHAPTER 23 D/A CONVERTER

This chapter describes the overview of the D/A converter, the configuration and functions of registers,and the D/A converter operation. Note: MB91V280 Only

CHAPTER 24 CLOCK MODULATOR

This chapter describes the register configuration, function and operation of the clock modulator.

CHAPTER 25 CLOCK SUPERVISOR

This chapter explains clock supervisor's function.

CHAPTER 26 FLASH MEMORY

This chapter provides an outline of flash memory and explains its register configuration, registerfunctions, and operations.

CHAPTER 27 HARDWARE WATCHDOG TIMER

This chapter explains the functions of hardware watchdog timer.

APPENDIX

The appendixes describe the I/O map, interrupt vectors, and pin states in each CPU state.

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Copyright© 2007 FUJITSU LIMITED All rights reserved

• The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering.

• The information, such as descriptions of function and application circuit examples, in this document are presentedsolely for the purpose of reference to show examples of operations and uses of FUJITSU semiconductor device;FUJITSU does not warrant proper operation of the device with respect to use based on such information. Whenyou develop equipment incorporating the device based on such information, you must assume any responsibilityarising out of such use of the information. FUJITSU assumes no liability for any damages whatsoever arising outof the use of the information.

• Any information in this document, including descriptions of function and schematic diagrams, shall not beconstrued as license of the use or exercise of any intellectual property right, such as patent right or copyright, orany other right of FUJITSU or any third party or does FUJITSU warrant non-infringement of any third-party'sintellectual property right or other right by using such information. FUJITSU assumes no liability for anyinfringement of the intellectual property rights or other rights of third parties which would result from the use ofinformation contained herein.

• The products described in this document are designed, developed and manufactured as contemplated for generaluse, including without limitation, ordinary industrial use, general office use, personal use, and household use, butare not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangersthat, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly todeath, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch controlin weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificialsatellite).Please note that FUJITSU will not be liable against you and/or any third party for any claims or damages arising inconnection with above-mentioned uses of the products.

• Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or lossfrom such failures by incorporating safety design measures into your facility and equipment such as redundancy,fire protection, and prevention of over-current levels and other abnormal operating conditions.

• If any products described in this document represent goods or technologies subject to certain restrictions on exportunder the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government willbe required for export of those products from Japan.

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CONTENTS

CHAPTER 1 OVERVIEW ................................................................................................... 11.1 Features .............................................................................................................................................. 21.2 Block Diagram .................................................................................................................................... 71.3 Package Dimension ............................................................................................................................ 81.4 Pin Assignment ................................................................................................................................... 91.5 Memory Map ..................................................................................................................................... 101.6 Description of Pin Function ............................................................................................................... 111.7 I/O Circuit Type ................................................................................................................................. 25

CHAPTER 2 HANDLING DEVICES ................................................................................ 312.1 Precautions when Handling Devices ................................................................................................ 32

CHAPTER 3 CPU and CONTROL UNIT ......................................................................... 353.1 Memory Space .................................................................................................................................. 363.2 Internal Architecture .......................................................................................................................... 37

3.2.1 Internal Architecture .................................................................................................................... 383.2.2 Overview of Instructions .............................................................................................................. 41

3.3 Programming Model ......................................................................................................................... 433.3.1 General-Purpose Registers ......................................................................................................... 443.3.2 Dedicated Registers .................................................................................................................... 45

3.4 Data Configuration ............................................................................................................................ 523.5 Memory Map ..................................................................................................................................... 543.6 Branch Instructions ........................................................................................................................... 55

3.6.1 Operation with Delay Slot ............................................................................................................ 563.6.2 Operation without Delay Slot ....................................................................................................... 58

3.7 EIT (Exception, Interruption, and Trap) ............................................................................................ 593.7.1 EIT Interrupt Levels ..................................................................................................................... 603.7.2 ICR (Interrupt Control Register) ................................................................................................... 623.7.3 SSP (System Stack Pointer) ........................................................................................................ 643.7.4 Interrupt Stack ............................................................................................................................. 653.7.5 TBR (Table Base Register) ......................................................................................................... 663.7.6 EIT Vector Table .......................................................................................................................... 673.7.7 Multiple EIT Processing ............................................................................................................... 703.7.8 Operations ................................................................................................................................... 72

3.8 Operating Mode ................................................................................................................................ 763.8.1 Bus Modes ................................................................................................................................... 773.8.2 Mode Settings .............................................................................................................................. 78

3.9 Clock Generation Control ................................................................................................................. 813.9.1 PLL Controls ................................................................................................................................ 823.9.2 Oscillation stability waiting and PLL lock waiting time ................................................................. 843.9.3 Clock Distribution ......................................................................................................................... 853.9.4 Clock Division .............................................................................................................................. 873.9.5 Block Diagram of Clock Generation Controller ............................................................................ 88

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3.9.6 Register of Clock Generation Controller ...................................................................................... 893.9.7 Peripheral Circuits of Clock Controller ....................................................................................... 106

3.10 Device state control ........................................................................................................................ 1093.10.1 State of device and each transition ........................................................................................... 1103.10.2 Low-power Consumption Mode ................................................................................................. 113

3.11 Main Clock Oscillation Stabilization Wait Timer .............................................................................. 117

CHAPTER 4 RESET ...................................................................................................... 1254.1 Overview of Reset .......................................................................................................................... 1264.2 Reset Factors and Oscillation Stabilization Wait Times ................................................................. 1284.3 Reset Levels ................................................................................................................................... 1304.4 External Reset Pin .......................................................................................................................... 1324.5 Reset Operation .............................................................................................................................. 1334.6 Reset Factor Bit .............................................................................................................................. 1344.7 State of Each Pin at Reset .............................................................................................................. 136

CHAPTER 5 EXTERNAL BUS INTERFACE ................................................................ 1375.1 Features of External Bus Interface ................................................................................................. 1385.2 External Bus Interface Registers .................................................................................................... 141

5.2.1 ASR0 to ASR3 (Area Select Register) ...................................................................................... 1425.2.2 ACR0 to ACR3 (Area Configuration Register) ........................................................................... 1435.2.3 AWR0 to AWR3 (Area Wait Register) ....................................................................................... 1485.2.4 CSER (Chip Select Enable Register) ........................................................................................ 153

5.3 Chip Select Area ............................................................................................................................. 1545.4 Endian and Bus Access .................................................................................................................. 156

5.4.1 Relationship between Data Bus Width and Control Signal ........................................................ 1575.4.2 Bus Access ................................................................................................................................ 1585.4.3 External Access ......................................................................................................................... 163

5.5 Ordinary Bus Interface .................................................................................................................... 1675.6 Address/Data Multiplex Interface .................................................................................................... 1755.7 DMA Access ................................................................................................................................... 1785.8 Procedure for Setting Registers ...................................................................................................... 181

CHAPTER 6 I/O PORT .................................................................................................. 1836.1 Overview of I/O Ports ...................................................................................................................... 1846.2 Port Data Register (PDR)/Data Direction Register (DDR) .............................................................. 1866.3 Setting of the Port Function Register .............................................................................................. 1886.4 Rearrangement of External Interrupt Input ..................................................................................... 2046.5 Selection of Pin Input Level ............................................................................................................ 2066.6 Pull-up and Pull-down Control Register .......................................................................................... 2086.7 Input Data Direct Read Register ..................................................................................................... 211

CHAPTER 7 INTERRUPT CONTROLLER ................................................................... 2137.1 Overview of the Interrupt Controller ................................................................................................ 2147.2 Interrupt Controller Registers .......................................................................................................... 217

7.2.1 Interrupt Control Register (ICR) ................................................................................................. 2187.2.2 Hold Request Cancellation Request Level Setting Register (HRCL) ........................................ 219

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7.3 Interrupt Controller Operation ......................................................................................................... 220

CHAPTER 8 EXTERNAL INTERRUPT ......................................................................... 2278.1 Overview of the External Interrupt .................................................................................................. 2288.2 External Interrupt Registers ............................................................................................................ 229

8.2.1 Interrupt Enable Register (ENIR) ............................................................................................... 2308.2.2 External Interrupt Factor Register (EIRR) ................................................................................. 2318.2.3 External Interrupt Request Level Setting Register (ELVR) ........................................................ 232

8.3 Operation of the External Interrupt ................................................................................................. 233

CHAPTER 9 REALOS-RELATED HARDWARE .......................................................... 2379.1 Delayed Interrupt Module ............................................................................................................... 238

9.1.1 Overview of the Delayed Interrupt Module ................................................................................ 2399.1.2 Delayed Interrupt Module Registers .......................................................................................... 2409.1.3 Operation of the Delayed Interrupt Module ............................................................................... 241

9.2 Bit Search Module .......................................................................................................................... 2429.2.1 Overview of the Bit Search Module ........................................................................................... 2439.2.2 Bit Search Module Registers ..................................................................................................... 2449.2.3 Bit Search Module Operation .................................................................................................... 246

CHAPTER 10 DMA CONTROLLER (DMAC) .................................................................. 24910.1 Overview of the DMA Controller (DMAC) ....................................................................................... 25010.2 Register Details Explanation ........................................................................................................... 253

10.2.1 Control/Status Registers A (DMACA0 to DMACA4) .................................................................. 25410.2.2 Control/Status Registers B (DMACB0 to DMACB4) .................................................................. 25810.2.3 Transfer Source/Transfer Destination Address Setting Registers

(DMASA0 to DMASA4/DMADA0 to DMADA4) .......................................................................... 26410.2.4 All-Channel Control Register (DMACR) .................................................................................... 266

10.3 DMA Controller Operation .............................................................................................................. 26810.3.1 DMA Controller Operation ......................................................................................................... 26910.3.2 Setting up Transfer Requests .................................................................................................... 27110.3.3 Transfer Sequence .................................................................................................................... 27210.3.4 General Aspects of DMA Transfer ............................................................................................. 27410.3.5 Addressing Mode ....................................................................................................................... 27510.3.6 Data Types ................................................................................................................................ 27610.3.7 Control of the Transfer Count .................................................................................................... 27710.3.8 CPU Control .............................................................................................................................. 27810.3.9 Operation Start .......................................................................................................................... 27910.3.10 Transfer Request Acceptance and Transfer .............................................................................. 28010.3.11 Clearing Peripheral Interrupts by DMA ...................................................................................... 28110.3.12 Temporary Stopping .................................................................................................................. 28210.3.13 Operation End/Stopping ............................................................................................................ 28310.3.14 Stopping Due To an Error .......................................................................................................... 28410.3.15 DMAC Interrupt Control ............................................................................................................. 28510.3.16 DMA Transfer during Sleep Mode ............................................................................................. 28610.3.17 Channel Selection and Control .................................................................................................. 287

10.4 Operation Flowcharts ...................................................................................................................... 289

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10.5 Data Path ........................................................................................................................................ 291

CHAPTER 11 CAN CONTROLLER ................................................................................ 29311.1 Feature of CAN ............................................................................................................................... 29411.2 CAN Block Diagram ........................................................................................................................ 29511.3 Register of CAN .............................................................................................................................. 29611.4 Functions of CAN Registers ........................................................................................................... 300

11.4.1 Overall Control Registers .......................................................................................................... 30111.4.1.1 CAN Control Registers (CTRLR0, CTRLR1) .......................................................................... 30211.4.1.2 CAN Status Register (STATR) ............................................................................................... 30511.4.1.3 CAN Error Counter (ERRCNT0 to ERRCNT2) ....................................................................... 30811.4.1.4 CAN Bit Timing Register (BTR0 to BTR2) .............................................................................. 30911.4.1.5 CAN Interrupt Register (INTR0 to INTR2) .............................................................................. 31011.4.1.6 CAN Test Register (TESTR0 to TESTR2) .............................................................................. 31111.4.1.7 BRP Extension Register (BRPER0 to BRPER2) .................................................................... 313

11.4.2 Message Interface Register ....................................................................................................... 31411.4.2.1 IFx Command Request Register (IFxCREQ) ......................................................................... 31511.4.2.2 IFx Command Mask Register (IFxCMSK) .............................................................................. 31711.4.2.3 IFx Mask Register 1 and 2 (IFxMSK1, IFxMSK2) ................................................................... 32211.4.2.4 IFx Arbitration Register 1 and 2 (IFxARB1, IFxARB2) ............................................................ 32311.4.2.5 IFx Message Control Register (IFxMCTR) ............................................................................. 32411.4.2.6 IFx Data Register A1,A2,B1,B2(IFxDTA1, IFxDTA2, IFxDTB1, IFxDTB2) ............................. 325

11.4.3 Message Object ......................................................................................................................... 32611.4.4 Message Handler Register ........................................................................................................ 331

11.4.4.1 CAN Transmission Request Register (TREQR1, TREQR2) .................................................. 33211.4.4.2 CAN New Data Register (NEWDT1, NEWDT2) ..................................................................... 33411.4.4.3 CAN Interrupt Pending Register (INTPND1, INTPND2) ......................................................... 33611.4.4.4 CAN Message Valid Register (MSGVAL1, MSGVAL2) .......................................................... 338

11.4.5 CAN Prescaler Register (CANPRE) .......................................................................................... 34011.5 CAN Functions ................................................................................................................................ 341

11.5.1 Message Object ......................................................................................................................... 34211.5.2 Message Transmission Operation ............................................................................................. 34411.5.3 Message Reception Operation .................................................................................................. 34611.5.4 FIFO Buffer Function ................................................................................................................. 34911.5.5 Interrupt Function ...................................................................................................................... 35111.5.6 Bit Timing ................................................................................................................................... 35211.5.7 Test Mode .................................................................................................................................. 35511.5.8 Software Initialization ................................................................................................................. 35911.5.9 CAN Clock Prescaler ................................................................................................................. 360

CHAPTER 12 LIN-UART ................................................................................................. 36312.1 Overview ......................................................................................................................................... 36412.2 Configuration of UART .................................................................................................................... 36712.3 Register of UART ............................................................................................................................ 372

12.3.1 Serial Control Register (SCR) ................................................................................................... 37412.3.2 Serial Mode Register (SMR) ...................................................................................................... 37712.3.3 Serial Status Register (SSR) ..................................................................................................... 380

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12.3.4 Reception/Transmission Data Register (RDR/TDR) .................................................................. 38312.3.5 Extended Status/Control Register (ESCR) ................................................................................ 38512.3.6 Extended Communication Control Register (ECCR) ................................................................. 38812.3.7 Baud Rate/Reload Counter Register (BGR) .............................................................................. 391

12.4 UART Interrupt ................................................................................................................................ 39212.4.1 Generation of Reception Interrupt and Flag Set Timing ............................................................ 39512.4.2 Transmission Interrupt Generation and Flag Timing ................................................................. 397

12.5 UART Baud Rate ............................................................................................................................ 39912.5.1 Setting the Baud Rate ............................................................................................................... 40112.5.2 Restart of the Reload Counter ................................................................................................... 404

12.6 Operation of UART ........................................................................................................................ 40612.6.1 Operation in the Asynchronous Mode (Operation Mode 0 and Mode 1) ................................... 40812.6.2 Operation in the Synchronous Mode (Operation Mode 2) ......................................................... 41012.6.3 Operating in LIN Function (Operation Mode 3) ......................................................................... 41312.6.4 Direct Access to Serial Pins ...................................................................................................... 41712.6.5 Bidirectional Communication Function (Normal Mode) ............................................................. 41812.6.6 Master-Slave Communication Function (Multiprocessor Mode) ................................................ 42012.6.7 LIN Communication Function .................................................................................................... 42312.6.8 LIN Communication Mode (Operation Mode 3) UART Sample Flowchart ................................ 425

12.7 Precautions when Using UART ...................................................................................................... 428

CHAPTER 13 I2C INTERFACE ....................................................................................... 43113.1 Outline of I2C Interface ................................................................................................................... 43213.2 I2C Interface Register ..................................................................................................................... 436

13.2.1 Bus Status Register (IBSR0 to IBSR2) ...................................................................................... 43713.2.2 Bus Control Register (IBCR0 to IBCR2) .................................................................................... 44013.2.3 Clock Control Register (ICCR0 to ICCR2) ................................................................................ 44713.2.4 10-bit Slave Address Register (ITBAH0 to ITBAH2, ITBAL0 to ITBAL2) .................................. 44913.2.5 10-bit Slave Address Mask Register (ITMKH0 to ITMKH2, ITMKL0 to ITMKL2) ....................... 45013.2.6 7-bit Slave Address Register (ISBA0 to ISBA2) ........................................................................ 45213.2.7 7-bit Slave Address Mask Register (ISMK0 to ISMK2) ............................................................. 45313.2.8 Data Register (IDAR0 to IDAR2) ............................................................................................... 454

13.3 Operation Explanation of I2C Interface ........................................................................................... 45513.4 Operation Flowcharts ...................................................................................................................... 460

CHAPTER 14 16-BIT RELOAD TIMER ........................................................................... 46314.1 Overview of the 16-bit Reload Timer .............................................................................................. 46414.2 Registers of the 16-bit Reload Timer ............................................................................................. 465

14.2.1 Control Status Registers (TMCSR) ........................................................................................... 46614.2.2 16-bit Timer Register (TMR) ...................................................................................................... 46914.2.3 16-bit Reload Register (TMRLR) ............................................................................................... 470

14.3 Operation of 16-bit Reload Timer ................................................................................................... 471

CHAPTER 15 16-BIT FREE-RUN TIMER ....................................................................... 47515.1 Overview of 16-bit Free-run Timer .................................................................................................. 47615.2 16-bit Free-run Timer Registers ...................................................................................................... 477

15.2.1 Timer Data Register (TCDT) ..................................................................................................... 478

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15.2.2 Timer Control Status Register (TCCS) ...................................................................................... 47915.3 Operation of 16-bit Free-run Timer ................................................................................................. 48215.4 Notes on Using the 16-bit Free-run Timer ...................................................................................... 484

CHAPTER 16 INPUT CAPTURE ..................................................................................... 48516.1 Overview of the Input Capture ........................................................................................................ 48616.2 Input Capture Registers .................................................................................................................. 487

16.2.1 Input Capture Register (IPCP) ................................................................................................... 48816.2.2 Input Capture Control Register (ICS) ........................................................................................ 489

16.3 Operation of Input Capture ............................................................................................................. 490

CHAPTER 17 OUTPUT COMPARE ................................................................................ 49117.1 Overview of the Output Compare ................................................................................................... 49217.2 Registers of the Output Compare ................................................................................................... 493

17.2.1 Compare Register (OCCP) ........................................................................................................ 49417.2.2 Control Register (OCS) ............................................................................................................. 495

17.3 Output Compare Operation ............................................................................................................ 497

CHAPTER 18 PPG TIMER .............................................................................................. 50118.1 Overview ......................................................................................................................................... 50218.2 Block Diagram ................................................................................................................................ 50318.3 PPG Register .................................................................................................................................. 506

18.3.1 PPG Operation Mode Control Register (PPGC) ........................................................................ 50718.3.2 Reload Registers (PRLL/PRLH) ................................................................................................ 50918.3.3 PPG Starting Register (TRG) .................................................................................................... 51018.3.4 Output Inverted Register (REVC) .............................................................................................. 511

18.4 Operation Explanation .................................................................................................................... 512

CHAPTER 19 UP/DOWN COUNTER .............................................................................. 51919.1 Overview of Up/Down Counter ....................................................................................................... 52019.2 Register of Up/Down Counter ......................................................................................................... 523

19.2.1 Up/Down Count Register (UDCR) ............................................................................................. 52419.2.2 Reload Compare Register (RCR) .............................................................................................. 52519.2.3 Counter Status Register (CSR) ................................................................................................. 52619.2.4 Counter Control Register (CCR) ................................................................................................ 528

19.3 Operation of Up/Down Counters ..................................................................................................... 531

CHAPTER 20 CLOCK MONITOR ................................................................................... 54120.1 Overview of Clock Monitor .............................................................................................................. 54220.2 Clock Output Enable Register ........................................................................................................ 544

CHAPTER 21 REAL TIME CLOCK ................................................................................. 54521.1 Configuration of Registers .............................................................................................................. 54621.2 Block Diagram ................................................................................................................................ 54821.3 Details of Registers ......................................................................................................................... 54921.4 Clock Calibration Unit ..................................................................................................................... 55421.5 Register of Clock Calibration Unit ................................................................................................... 555

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21.5.1 Calibration Unit Control Register (CUCR) ................................................................................. 55621.5.2 Sub Timer Data Register (CUTD) .............................................................................................. 55821.5.3 Main Timer Data Register (CUTR) ............................................................................................ 560

21.6 Using of Clock Calibration Unit ....................................................................................................... 561

CHAPTER 22 A/D CONVERTER .................................................................................... 56322.1 Overview of A/D Converter ............................................................................................................. 56422.2 Block Diagram of the A/D Converter ............................................................................................... 56522.3 Registers of A/D Converter ............................................................................................................. 566

22.3.1 Analog Input Enable Register (ADER) ...................................................................................... 56822.3.2 A/D Control Status Register (ADCS) ......................................................................................... 56922.3.3 Data Register (ADCR1, ADCR0) ............................................................................................... 57522.3.4 Conversion Time Setting Register (ADCT) ............................................................................... 57622.3.5 Start Channel Setting Register (ADSCH) End Channel Setting Register (ADECH) ................. 578

22.4 Operation of A/D Converter ............................................................................................................ 580

CHAPTER 23 D/A CONVERTER .................................................................................... 58323.1 Overview of D/A Converter ............................................................................................................. 58423.2 Registers of D/A Converter ............................................................................................................. 58523.3 Operation of the D/A Converter ...................................................................................................... 589

CHAPTER 24 CLOCK MODULATOR ............................................................................. 59124.1 Overview of Clock Modulator .......................................................................................................... 59224.2 Registers of Clock Modulator .......................................................................................................... 593

24.2.1 Clock Modulator Parameter Register (CMPR) .......................................................................... 59424.2.2 Clock Modulator Control Register (CMCR) ............................................................................... 595

CHAPTER 25 CLOCK SUPERVISOR ............................................................................. 59725.1 Overview of Clock Supervisor ......................................................................................................... 59825.2 Clock Supervisor Control Register (CSVCR) .................................................................................. 59925.3 Clock Supervisor Operation ............................................................................................................ 602

CHAPTER 26 FLASH MEMORY ..................................................................................... 60526.1 Outline of Flash Memory ................................................................................................................. 60626.2 Flash Memory Registers ................................................................................................................. 609

26.2.1 FLASH Control/Status Registers (FLCR) ................................................................................. 61026.2.2 Wait Register (FLWC) ............................................................................................................... 612

26.3 Explanation of Flash Memory Operation ....................................................................................... 61426.4 Automatic Algorithm of Flash Memory ............................................................................................ 616

26.4.1 Command Sequence ................................................................................................................. 61726.4.2 Check the Execution State of Automatic Algorithm ................................................................... 621

26.5 Writing to and Erasing from Flash Memory .................................................................................... 62626.5.1 Read/Reset Status .................................................................................................................... 62726.5.2 Data Writing ............................................................................................................................... 62826.5.3 Data Erase (Chip Erase) ........................................................................................................... 63026.5.4 Data Erase (Sector Erase) ........................................................................................................ 63126.5.5 Temporary Sector Erase Stop ................................................................................................... 633

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26.5.6 Sector Erase Restart ................................................................................................................. 63426.6 Wild Register .................................................................................................................................. 63526.7 Notes on Flash Memory Programming ........................................................................................... 636

CHAPTER 27 HARDWARE WATCHDOG TIMER .......................................................... 63727.1 Overview of Hardware Watchdog Timer ......................................................................................... 63827.2 Configuration of Hardware Watchdog Timer .................................................................................. 63927.3 Hardware Watchdog Timer Registers ............................................................................................. 64027.4 Function of Hardware Watchdog Timer .......................................................................................... 64127.5 Precautions ..................................................................................................................................... 642

APPENDIX ......................................................................................................................... 643APPENDIX A I/O Map ................................................................................................................................ 644APPENDIX B Interrupt Vector .................................................................................................................... 661APPENDIX C Pin States in Each CPU State .............................................................................................. 664APPENDIX D Programming Example of Serial Programming (Asynchronous) ......................................... 680APPENDIX E Programming Example of Serial Programming (Synchronous) ........................................... 683

INDEX................................................................................................................................... 691

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Main changes in this edition

Page Changes (For details, refer to main body.)

- First edition

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CHAPTER 1OVERVIEW

FR family is a standard single-chip microcontroller that has a 32-bit high-performance RISC CPU as well as built-in I/O resources and bus control mechanisms for embedded controller requiring high-performance and high-speed CPU processing.

1.1 Features

1.2 Block Diagram

1.3 Package Dimension

1.4 Pin Assignment

1.5 Memory Map

1.6 Description of Pin Function

1.7 I/O Circuit Type

1

CHAPTER 1 OVERVIEW

1.1 Features

This section describes the features of MB91270 series.

■ Feature of FR CPU• 32 bits RISC, load/store architecture and five steps in pipeline

• Maximum operating frequency: 32MHz [use of PLL: when source oscillation is 4MHz]

• 16-bit fixed length instruction (basic instruction), one instruction/one cycle

• Memory to memory transfer, bit processing and instruction of barrel shift and so on.

- Instruction suitable for embedded application

• Function entry and exit instructions, multi load/store instructions of register content- Instructions compatible with high-level languages

• Register interlock function- Simplification of assembler description

• Built-in multiplier/instruction-level support

- 32-bit multiplication with sign : Five cycles

- 16-bit multiplication with sign : Three cycles

• Interruption (save of PC and PS): Six cycles and 16 priority levels

• Harvard architecture enabling simultaneous execution of both program access and data access

• The instruction is interchangeable with the FR family.

■ External Bus Interface• Maximum operating frequency 16MHz

• 24-bit address full output enable (16MB space)

• 8- and 16-bit data output

• Unused data and address pins are usable as a general I/O port.

• Totally independent 4-area chip select output that can be defined at a minimum of 64 KB

• Support in interface to various memoriesSRAM, ROM/FLASH

• Basic bus cycle: Two cycles

• Automatic wait cycle generator that can be programmed for each area and can insert waits

• External wait cycle by RDY input

2

CHAPTER 1 OVERVIEW

■ Built-in MemoryTable 1.1-1 shows the details of built-in memory.

Overview of peripheral circuit is described in the following.

Check Table 1.1-2 for built-in channel number of each product.

■ DMAC (DMA Controller)• Maximum 5 channels can be operated simultaneously.

• Two forwarding factors (internal peripheral/software)

■ Bit Search Module (Using REALOS) • Searches for the position of the first bit varying between 1 and 0 in the MSB of a word

■ UART which Supports for LIN: Maximum 7 Channels• Asynchronous (Start-Stop synchronous) communication, clock synchronous communication

• Synch-break detection

• Baud rate generator is installed in each channel.

• Can be for SPI (Mode 2: clock synchronous communication mode)

■ CAN Controller: Maximum 3 Channels• Maximum transferring rate: 1Mbps

• 32 message buffers (128 message buffers in MB91V280)

■ Timers• 16-bit reload timer 3 channels (including 1 ch for REALOS)

Internal clock is selectable from 2/8/32-division.

• 16-bit free-run timer: 4 channelsOutput compare: 8 channelsInput capture: 8 channels

• 8/16-bit PPG: 8 bits × 16 channels or 16 bits × 8 channels

Table 1.1-1 Details of Internal Memory

MB91V280 MB91F273(S) MB91F278(S)

Built-in ROM/FLASH External SRAM FLASH 512KB FLASH 512KB

F bus RAM 48KB 24KB 24KB

3

CHAPTER 1 OVERVIEW

■ Interrupt Controller: Maximum 40 Channels• Interruption from internal peripheral

• Priority level is settable by software (16 levels).

■ D/A Converter: 2 Channels (MB91V280 Only)• 8-/10-bit resolution, R-2R type

■ A/D Converter: 24 Channels (in MB91V280, Support +8 Channels as Independent Module)

• 10-bit resolution

• Successive conversion typeConversion time: 3µs

• Conversion mode (Single conversion mode and serial conversion mode)

• Start-up factor (soft, external trigger and peripheral interrupt)

■ Other Interval Timer/Counter• 8/16-bit up/down counter:

8-bit × 4 channels or 16-bit × 2 channels• 16-bit time-base timer/ watchdog timer

■ I2C Interface (Supported for 400Kbps) : 3 Channels• Master/slave transmission and reception

• Arbitration function and clock synchronization function

■ Hardware Watchdog• Interval time: 569ms(min), 771ms(max)

* Use of self-oscillation circuit with trimming (100 kHz)

■ I/O Port• Each pin can control pull-up or pull-down.

• Each pin can select CMOS Schmitt trigger or CMOS automotive Schmitt trigger as input level.

• Direct read of pin level is enabled.

• Maximum 128 ports

4

CHAPTER 1 OVERVIEW

■ Other Features• Internal oscillation circuit is provided as a clock source. PLL multiplication can also be selected.

• INIT is prepared as a reset terminal.

• Additionally, a watchdog timer reset and software reset are provided.

• Support for stop mode, sleep mode and real time clock mode as low-power consumption mode. Low-power consumption by 32kHz CPU operation is enabled. (only for products without "S" type)

• Gear function

• Built-in time-base timer

• Wild register

• Clock output (clock monitor)

• Clock modulator

• Clock supervisorThe stop of the main clock is supervised by the internal self-oscillation.

• Package: LQFP-100

• CMOS technology (0.35µm)

• Power supply voltage: 3.5V to 5.5VInternal circuit is supplied 3.3 V by the built-in step-down circuit.

5

CHAPTER 1 OVERVIEW

■ Comparison of FunctionsTable 1.1-2 shows the comparison of functions in MB91270 series.

Table 1.1-2 Comparison of Functions

MB91V280 MB91F273(S) MB91F278(S)

Package PGA-401 LQFP-100

Built-in ROM/FLASH External SRAM FLASH 512KB

RAM 48KB 24KB

External busAddress: 24 bits

Data: 16 bits

Address: 24 bitsData: 16 bits

(only for multiplex)

External interrupt 40channels 16channels

DMA controller 5channels

Clock modulator Yes

Clock supervisor Yes No Yes

Clock monitor Yes

32kHz sub clock Yes Option (only for products without "S" type)

Real time clock Yes

CAN controller3channels (128 message

buffer)1channel (32 message buffer)

LIN corresponded UART 7channels

I2C interface 3channels

16-bit reload timer 3channels

8-/16-bit up/down counter 2channels

16-bit free-run timer 4channels

Input capture 8channels

Output compare 8channels

8-/16-bit PPG8channels × 16-bit16channels × 8-bit

10-bit A/D converter 24channels + 8channels 24channels

8-/10-bit D/A converter 2channels None

Pin pull-up/pull-down All pins Refer to the Section "1.6 Description of Pin Function".

Input level selector All pins Refer to the Section "1.6 Description of Pin Function".

Debug support DSU4 Wild register

6

CHAPTER 1 OVERVIEW

1.2 Block Diagram

This section shows the block diagram of MB91270 series.

■ Block Diagram of the MB91270 Series

Figure 1.2-1 Block Diagram of the MB91270 Series

FR60 LiteCPU Core

32

32 32

16

32

FLASH memory/MASK ROM

CAN

F-bus-RAM

R-busadaptor

DAC*

ADC

LIN-

UART

I2C400kHz

Clock generator

F-bus

D-bus

32

R-bus

I-busBit search

module

Debug support

DMA controller

Watchdog timer

Voltage regulator

Harvard busconverter

External businterface

External bus24-bit address

16-bit data

Sub clock

Real time clockClock monitorReload timer

ICU16-bit

Free-run timer OCU16-bit

External interruptUp/down counter

8/16-bitPPG

8/16-bit

Clock supervisor

Hardwarewatchdog

*: Only for MB91V280

7

CHAPTER 1 OVERVIEW

1.3 Package Dimension

This section shows the package dimensions of MB91270 series.

■ LQFP 100-pin

Figure 1.3-1 Package Dimension of FPT-100P-M5

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html

100-pin plastic LQFP Lead pitch 0.50 mm

Package width × package length

14.0 × 14.0 mm

Lead shape Gullwing

Sealing method Plastic mold

Mounting height 1.70 mm MAX

Weight 0.65g

Code(Reference)

P-LFQFP100-14 × 14-0.50

100-pin plastic LQFP(FPT-100P-M05)

(FPT-100P-M05)

C 2003 FUJITSU LIMITED F100007S-c-4-6

14.00±0.10(.551±.004)SQ

16.00±0.20(.630±.008)SQ

26

51

76 50

75

100

0.50(.020) 0.20±0.05(.008±.002)

M0.08(.003)0.145±0.055

(.0057±.0022)

0.08(.003)

"A"

INDEX.059 –.004

+.008–0.10+0.20

1.50(Mounting height)

0°~8°

0.50±0.20(.020±.008)0.60±0.15

(.024±.006)

0.25(.010)

0.10±0.10(.004±.004)

Details of "A" part

(Stand off)

*

Dimensions in mm (inches).Note: The values in parentheses are reference values.

Note 1) * : These dimensions do not include resin protrusion.Note 2) Pins width and pins thickness include plating thickness.Note 3) Pins width do not include tie bar cutting remainder.

1 25

8

CHAPTER 1 OVERVIEW

1.4 Pin Assignment

This section shows the pin assignments of MB91270 series.

■ LQFP 100-pin

P25

/A21

/IN1

P24

/A20

/IN0

P23

/A19

/PP

GF

P22

/A18

/PP

GD

P21

/A17

/PP

GB

P20

/A16

/PP

G9

P17

/AD

15/S

CK

4P

16/A

D14

/SO

T4

P15

/AD

13/S

IN4

X0

X1

VS

S

VC

C

P14

/AD

12/S

CK

3P

13/A

D11

/SO

T3

P12

/AD

10/S

IN3/

INT

11R

P11

/AD

09/T

OT

1P

10/A

D08

/TIN

1P

07/A

D07

/INT

15P

06/A

D06

/INT

14P

05/A

D05

/SC

K6/

INT

13P

04/A

D04

/SO

T6/

INT

12P

03/A

D03

/SIN

6/IN

T11

P02

/AD

02/S

CK

5/IN

T10

P01

/AD

01/S

OT

5/IN

T9

100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

P26/A22/IN2P27/A23/IN3P30/AS/IN4P31/RD/IN5

P32/WR0/RX2/INT10RP33/WR1/TX2

P34/BRQ/OUT4P35/BGRNT/OUT5

P36/RDY/OUT6P37/SYSCLK/OUT7

P40/(X0A)P41/(X1A)

VCCVSS

CP42/IN6/RX1/INT9R

P43/IN7/TX1P44/SDA0/FRCK0

P45/AIN2/SCL0/FRCK1P46/BIN2/SDA1P47/ZIN2/SCL1P50/AN8/SIN2

P51/AN9/SOT2P52/AN10/SCK2P53/AN11/BIN1

123456789

10111213141516171819202122232425

75747372717069686766656463626160595857565554535251

P00/AD00/SIN5/INT8PA1/TX0PA0/RX0/INT8RP97/OUT3P96/OUT2/ZIN0P95/OUT1/BIN0P94/OUT0/AIN0P93/PPG7/ZIN3/CS3P92/PPG5/BIN3/CS2P91/PPG3/AIN3/CS1P90/PPG1/CS0VSSVCCP87/SCK1P86/SOT1P85/SIN1P84/SCK0/INT15RP83/TOT2/SOT0P82/TIN2/SIN0/INT14RP81/TOT0/INT13R/CKOTP80/TIN0/INT12R/ADTGP77/AN23/INT7/SCL2P76/AN22/INT6/SDA2INITMD0

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

P54

/AN

12/A

IN1

P55

/AN

13/Z

IN1

P56

/AN

14/D

AO

0P

57/A

N15

/DA

O1

AV

CC

AV

RH

AV

RL

AV

SS

P60

/AN

0/P

PG

0P

61/A

N1/

PP

G2

P62

/AN

2/P

PG

4P

63/A

N3/

PP

G6

P64

/AN

4/P

PG

8P

65/A

N5/

PP

GA

P66

/AN

6/P

PG

CP

67/A

N7/

PP

GE

VS

S

P70

/AN

16/IN

T0

P71

/AN

17/IN

T1

P72

/AN

18/IN

T2

P73

/AN

19/IN

T3

P74

/AN

20/IN

T4

P75

/AN

21/IN

T5

MD

2M

D1

9

CHAPTER 1 OVERVIEW

1.5 Memory Map

This section shows the memory map of MB91270 series.

■ Memory Map of MB91270 Series

Figure 1.5-1 Memory Map of MB91270 Series

Note:

The initial value for emulation SRAM area of MB91V280 is 512KB(0x80000-0x100000). The area upto 1024KB(0x50000-0x150000) is supported as SRAM area.

I/O

MB91V280

0000 0000H

0002 0000H

0002 0500H

0003 4000H

0003 A000H

0003 D800H

0004 0000H

0008 0000H

0010 0000H

FFFF FFFFH

0000 0400H

0001 0000H

0000 0000H

MB91F273(S)MB91F278(S)

I/O

Built-in RAM48KB Built-in

RAM24KB

FLASH512KB

CAN CAN

I/O

I/O

Direct addressing areaRefer to I/O map

Access prohibited Access prohibited

Access prohibited Access prohibited

Access prohibited

Access prohibited

EmulationRAM area

External area External area

10

CHAPTER 1 OVERVIEW

1.6 Description of Pin Function

This section shows the description of pin function.

■ Description of Pin Function

Table 1.6-1 Description of Pin Function (1 / 13)

Pin No. Pin name Function nameI/O circuit

type* Function

90 X1 X1 OB Oscillator output pin

91 X0 X0 OA Oscillator input pin

52 INIT INIT N Reset input pin (“L” active)

49 to 51 MD2 to MD0 MD2 to MD0 JOperation mode select input pin. Connect to VCC or VSS directly.

Port 0

75P00/AD00/SIN5/INT8

P00

T

General-purpose I/O ports. This function is enabled in single-chip mode.

AD00External address/data bus I/O pin bit 0This function is enabled when the external bus is enabled.

INT8 External interrupt request 8 input pin

SIN5 Serial data input pin for LIN-UART5

76P01/AD01/SOT5/INT9

P01

T




SOT5 Serial data output pin for LIN-UART5

77P02/AD02/

SCK5/INT10

P02

T




SCK5 Clock I/O pin for LIN-UART5

78P03/AD03/SIN6/INT11

P03

T





11

CHAPTER 1 OVERVIEW

79P04/AD04/

SOT6/INT12

P04

T





80P05/AD05/

SCK6/INT13

P05

T





81P06/AD06/

INT14

P06

T




82P07/AD07/

INT15

P07

T




Port 1

83P10/AD08/

TIN1

P10

T



TIN1 Event input pin for reload timer 1

84P11/AD09/

TOT1

P11

T



TOT1 Output pin for reload timer 1

85P12/AD10/

SIN3/INT11R

P12

T




INT11R External interrupt request 11 input pin (Set by EISSR)



type* Function

12

CHAPTER 1 OVERVIEW

86P13/AD11/

SOT3

P13

T




87P14/AD12/

SCK3

P14

T




92P15/AD13/

SIN4

P15

T




93P16/AD14/

SOT4

P16

T




94P17/AD15/

SCK4

P17

T




Port 2

95P20/A16/

PPG9

P20

A


A16External address bus output pin bit 16This function is enabled when the external bus is enabled.

PPG9 Output pin for PPG9

96P21/A17/

PPGB

P21

A



PPGB Output pin for PPGB

97P22/A18/

PPGD

P22

A



PPGD Output pin for PPGD



type* Function

13

CHAPTER 1 OVERVIEW

98P23/A19/

PPGF

P23

A



PPGF Output pin for PPGF

99, 100, 1, 2

P24/A20/IN0 to

P27/A23/IN3

P24 to P27

A


A20 to A23External address bus output pin bits 20 to 23This function is enabled when the external bus is enabled.

IN0 to IN3 Data sample input pins for input capture ICU0 to ICU3

Port 3

3 P30/AS/IN4

P30

A


ASExternal address strobe output pinThis function is enabled when the external bus is enabled.

IN4 Data sample input pin for input capture ICU4

4 P31/RD/IN5

P31

A


RDExternal read strobe output pinThis function is enabled when the external bus is enabled.


5P32/WR0/

RX2/INT10R

P32

A


WR0

External data bus write strobe output pin. Enabled when the external bus is enabled.WR0 is used as the data write strobe for 8-bit access and as the upper 8 bits of the data in 16-bit access.

RX2 CAN2 RX input pin (MB91V280 only)


6P33/WR1/

TX2

P33

A


WR1Write strobe output pin for lower 8 bits in external data busEnabled when the external bus is enabled and external bus 16-bit mode is selected.

TX2 CAN2 TX output pin (MB91V280 only)

7P34/BRQ/

OUT4

P34

T (A)


BRQ

External bus request input pinEnabled when the external bus and the bus request func-tions are enabled.(MB91V280 only)

OUT4 Waveform output pin for output compare OCU4.



type* Function

14

CHAPTER 1 OVERVIEW

8P35/

BGRNT/OUT5

P35

A


BGRNT

External bus acknowledge output pinEnabled when the external bus and the bus request functions are enabled. (MB91V280 only)


9P36/RDY/

OUT6

P36

T


RDYExternal ready input pinEnabled when the external bus and the bus request func-tions are enabled.


10P37/

SYSCLK/OUT7

P37

A


SYSCLKExternal clock output pinThis function is enabled when the external bus is enabled.


Port 4

11, 12P40/ (X0A) , P41/ (X1A)

P40, P41 AGeneral-purpose I/O ports (S-suffix models)

X0A, X1AWAWB

Sub clock oscillator input pin (without S-suffix models)

16P42/IN6/

RX1/INT9R

P42

A

General-purpose I/O ports


RX1 CAN1 RX input pin (MB91V280 only)


17 P43/IN7/TX1

P43

A



TX1 CAN1 TX output pin (MB91V280 only)

18P44/SDA0/

FRCK0

P44

C


SDA0 Serial data I/O pin for I2C0

FRCK0 16-bit input/output timer 0 input pin

19P45/AIN2/

SCL0/FRCK1

P45

C


SCL0 Serial clock I/O pin for I2C0

FRCK1 16-bit input/output timer 1 input pin

AIN2 16/8-bit up-count input pin for up down counter 2/3

20P46/BIN2/

SDA1

P46

C


SDA1 Serial clock I/O pin for I2C1

BIN2 16/8-bit down-count input pin for up down counter 2/3



type* Function

15

CHAPTER 1 OVERVIEW

21P47/ZIN2/

SCL1

P47

C



ZIN2 16/8-bit reset input pin for up down counter 2/3

Port 5

22P50/AN8/

SIN2

P50

D


AN8 Analog input pin of A/D converter


23P51/AN9/

SOT2

P51

D




24P52/AN10/

SCK2

P52

D




25P53/AN11/

BIN1

P53

D



BIN1 8-bit down-count input pin for 16-bit up down counter 1

26P54/AN12/

AIN1

P54

D



AIN1 8-bit up-count input pin for 16-bit up down counter 1

27P55/AN13/

ZIN1

P55

D



ZIN1 8-bit reset input pin for 16-bit up down counter 1

28P56/AN14/

DAO0

P56

E



DAO0 Analog output pin 0 for D/A converter (MB91V280 only)

29P57/AN15/

DAO1

P57

E



DAO1 Analog output pin 1 for D/A converter (MB91V280 only)

Port 6

34 to 41

P60/AN0/PPG0

to P67/AN7/

PPGE

P60 to P67

D


AN0 to AN7 Analog input pin of A/D converter

PPG0PPG2PPG4PPG6PPG8PPGAPPGCPPGE

Output pin for PPG



type* Function

16

CHAPTER 1 OVERVIEW

Port 7

43 to 48

P70/AN16/INT0 to

P75/AN21/INT5

P70 to P75

D


AN16 to AN21

Analog input pin of A/D converter

INT0 to INT5 External interrupt request 0 to 5 input pin

53P76/AN22/INT6/SDA2

P76

CA




SDA2 Serial data I/O pin for I2C2

54P77/AN23/INT7/SCL2

P77

CA





Port 8

55P80/TIN0/INT12R/ADTG

P80

A



ADTG Trigger input pin for A/D converter


56P81/TOT0/

INT13R/CKOT

P81

A



CKOT Output pin for clock monitor


57P82/TIN2/

SIN0/INT14R

P82

A





58P83/TOT2/

SOT0

P83

A




59P84/SCK0/

INT15R

P84

A




60 P85/SIN1P85

AGeneral-purpose I/O ports


61 P86/SOT1P86



62 P87/SCK1P87





type* Function

17

CHAPTER 1 OVERVIEW

Port 9

65P90/PPG1/

CS0

P90

A


CS0External chip select 0This function is enabled when the external bus is enabled.


66P91/PPG3/AIN3/CS1

P91

A




AIN3 8-bit up-count input pin for up down counter 3

67P92/PPG5/BIN3/CS2

P92

A




BIN3 8-bit down-count input pin for up down counter 3

68P93/PPG7/ZIN3/CS3

P93

A




ZIN3 8-bit reset input pin for up down counter 3

69P94/OUT0/

AIN0

P94

A


OUT0 Waveform output pin for output compare OCU0

AIN0 16/8-bit up-count input pin for up down counter 0/1

70P95/OUT1/

BIN0

P95

A



BIN0 16/8-bit down-count input pin for up down counter 0/1

71P96/OUT2/

ZIN0

P96

A



ZIN0 16/8-bit reset input pin for up down counter 0/1

72 P97/OUT3P97



Port A

73PA0/RX0/

INT8R

PA0

A


RX0 RX input pin for CAN0


74 PA1/TX0PA1


TX0 TX output pin for CAN0



type* Function

18

CHAPTER 1 OVERVIEW

Port B (MB91V280 only)

⎯ PB0

PB0

A


INT8-2 External interrupt request 8 input pin (Set by EPFRB)

SIN5-2 Serial data input pin for LIN-UART5 (Set by PFRB)

⎯ PB1

PB1

A



SOT5-2 Serial data output pin for LIN-UART5

⎯ PB2

PB2

A



SCK5-2 Clock I/O pin for LIN-UART5 (set by PFRB)

⎯ PB3

PB3

A



SIN6-2 Serial data input pin for LIN-UART6 (Set by PFRB)

⎯ PB4

PB4

A




⎯ PB5

PB5

A



SCK6-2 Clock I/O pin for LIN-UART6 (set by PFRB)

Port C (MB91V280 only)

⎯ PC0

PC0

A


OUT4-2 Output pin for output compare OCU4


⎯ PC1

PC1

A


OUT5-2 Output pin for output compare OCU5


⎯ PC2

PC2

A


SIN3-2 Serial data input pin for LIN-UART3 (Set by PFRC)


⎯ PC3

PC3

A




⎯ PC4

PC4

A


SCK3-2 Clock I/O pin for LIN-UART3 (set by PFRC)


⎯ PC5

PC5

A


SIN4-2 Serial data input pin for LIN-UART4 (Set by PFRC)




type* Function

19

CHAPTER 1 OVERVIEW

⎯ PC6

PC6

A




⎯ PC7

PC7

A


SCK4-2 Clock I/O pin for LIN-UART4 (set by PFRC)


Port D (MB91V280 only)

⎯ PD0

PD0

A



PPG9-2 Output pin for PPG9 (8)

⎯ PD1

PD1

A



PPGB-2 Output pin for PPGB (A)

⎯ PD2

PD2

A



PPGD-2 Output pin for PPGD (C)

⎯ PD3

PD3

A



PPGF-2 Output pin for PPGF (E)

⎯ PD4

PD4

A



IN0-2 Input pin for input capture ICU0 (set by PFRD)

⎯ PD5

PD5

A




⎯ PD6

PD6

A




⎯ PD7

PD7

A


Date post:	21-Oct-2020
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