I2C Communication Protocol -...

I2C Communication

ProtocolLecture# 24

Microprocessor System and Interfacing

Dr. Sohaib Ayyaz QaziCOMSATS University Islamabad

1

I2C Bus Protocol

I2C Bus

I2C is used for communication at short distance

I2C is a two wire interface

SCL (Serial CLock)

Synchronize the data transfer between two chips

SDA (Serial DAta)

data line


2

I2C Bus Protocol

I2C Electrical Characteristics

2 bidirectional open drain pins

Concept of Open Drain


3

This is a wired-AND structure, i.e., if one or more devices pull the line

to low (zero) level, the line state is zero and the level of the line will be

1 only if none of the devices pull the line to low level

I2C Bus Protocol

I2C Nodes

In AVR up to 119 different devices can share an I2C bus.

Each of the device is called node

MASTER node

Generates the clock and initiate or terminate the

transmission

SLAVE Node

Receives the clock and is addressed by the master

Different Modes (Both nodes can transmit/receive data)

Master Transmitter / Receiver

Slave Transmitter / Receiver


4

I2C Bus Protocol

I2C Bit Format

I2C is a synchronous serial protocol

The data line cannot change when the clock line is high

Data can change only when the clock line is low

Exceptions are START and STOP conditions


5

I2C Bus Protocol

Start and Stop Bits

START and STOP are generated by keeping the level of

SCL line high and then changing the level of SDA line.

The START condition is generated by a high-to-low

change in SDA line when SCL is high.

The STOP condition is generated by a low-to-high change

in SDA line when SCL is high


6

I2C Bus Protocol

Start and Stop Bits

The BUS is busy between each START and STOP

conditions, and no other master try to take control of the

bus when busy

If the master who has the control of the bus, wishes to

initiate new transfer and does not want to release the

bus then

Before starting the new transfer, it issues a new START

condition, called as REPEATED START


7

I2C Bus Protocol

Packet Format in I2C

The packet (address or data) consists of 9 bits

8 bits are put on SDA line by master

Master releases control of SDA during 9th bit and left high

Slave pulls down 9th bit to indicate acknowledge to

master

Clock is generated by master regardless if it is Rx/Tx


8

I2C Bus Protocol

Address Packet Format

The Address packet has the same format (9-bits wide)

7 bits are reserved for target slave address

1 bit for read/write

1 = read data from salve, 0 = write data to slave

1 bit for acknowledgment

The combination 0000000 and 1111xxx can not be used

for slave address. This means (128-1-8 = 119) devices can

be attached to master


9

I2C Bus Protocol

Data Packet Format

The Address packet has the same format (9-bits wide)

8 bits are reserved for data to be transmitted

1 bit for acknowledgment

If receiver cannot receive or process more data, will

send NACK signal to transmitter by leaving SDA line high


10

I2C Bus Protocol

Combining Address and Data Packets for Transmission

Transmission is started by a START condition

Followed by address packed (SLA + R/W)

One or more data packets

Finished by a STOP condition


11

I2C Bus Protocol

Clock Stretching

Kind of flow control

If slave is not ready to process more data

The clock line is stretched by holding SCL low after

receiving / transmitting a bit of data

Master will hold the line until slave releases the SCL line to

receive more data


12

I2C Bus Protocol

Arbitration

I2C supports a multi-master bus system

Each master waits for current transmission to finish

A case when two masters request at the same time

Transmitter checks level of the bus, compares the level it

expects, if not the level expected, converted to slave

mode


13

Master A wants to write 0010 000

Master B wants to write 0001 111

I2C Bus Protocol

Multibyte Burst Write

Address of first location and data is sent, consecutive

memory locations are written in memory

Generate a START condition

Transmit the slave address followed by 0 for write operation

After ACK, transmit the address of first location and receive

ACK

Transmit the data of the first location, then, send the bytes

of consecutive data to be placed at consecutive memory

locations

Generate stop condition


14

Sta

rt

H2L

Slave

Address

1111000

Wri

te

0

AC

K

A

First Location

Address

00001111

AC

K

A

Data Byte

# 1

00001111A

CK

A

Data Byte

# 1

00001111

AC

K

A

Sto

p

L2H

I2C Bus Protocol

Multibyte Burst Read

Generate a START condition

Transmit the slave address followed by 0 for address write

operation

Transmit the address of first location

Generate a START (REPEATED START) condition

Transmit the slave address followed by 1 for read operation

Read the data of the first location, then, receive the bytes

from consecutive memory locations

Generate stop condition


15

I2C in the AVR

Five Registers in AVR to control I2C Mode


16

I2C in the AVR

TWI (I2C) Bit Rate Register (TWBR)

TWBR selects the division factor to control the SCL clock

frequency in master mode

The SCL frequency is controlled jointly by

TWBR Register

Prescaler bits in TWSR (Status Register)

TWPS1 and TWPS0 (2 bit wide)


17

𝑓𝑆𝐶𝐿 =𝐶𝑃𝑈 𝐶𝑙𝑜𝑐𝑘 𝐹𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦

16 + 2 𝑇𝑊𝐵𝑅 × 4𝑇𝑊𝑃𝑆

TWBR7 TWBR6 TWBR5 TWBR4 TWBR3 TWBR2 TWBR1 TWBR0

I2C in the AVR

TWI (I2C) Status Register (TWSR)

Only 5 bits are dedicated for status of I2C logic and bus

While reading TWSR mask lower 2-bits


18

TWS7 TWS6 TWS5 TWS4 TWS3 --- TWPS1 TWPS0

I2C in the AVR

TWI (I2C) Control Register (TWCR)

Bit7 – TWINT: TWI Interrupt

Bit6 – TWEA: TWI Enable Acknowledge

Bit5 – TWSTA: TWI Start Condition Bit

Bit4 – TWSTO: TWI Stop Condition Bit

Bit3 – TWWC: TWI Write Collision Flag

Bit2 – TWEN: TWI Enable

Bit0 – TWIE: TWI Interrupt Enable


19

I2C in the AVR

TWI (I2C) Data Register (TWDR)

In Transmit mode, we should write next byte to TWDR

register

In Receive mode, the last byte will be in TWDR register

We can only access TWDR, when TWINT is high, otherwise

collision will occur

TWI (I2C) Address Register (TWAR)

TWAR contains 7-bit slave address to which the TWI will

respond when working as slave


20

AVR TWI Programming in C

AVR Programming in Master Operation Mode

Set the TWI module clock frequency (TWBR, TWPS)

Enable TWI module by setting TWEN bit in TWCR

Transmit a START condition

Set TWINT (clear the flag to make it ready)

Set TWSTA (generate start signal as bus is free)

Check TWINT flag to complete

Send Data

Copy the data byte to the TWDR

Set TWEN, TWINT, Check TWINT flag to complete

Receive Data

Transmit STOP condition


21

Example 1


22

Make a master node write 1111 0000 to a slave with address 1101

0000

int main (void)

{

i2c_init (); // initialize I2C

i2c_start (); // Transmit START Condition

i2c_write (0b11010000); // Transmit SLA and W(0)

i2c_write (0b11110000); // Transmit Data

i2c_stop (); // Transmit STOP condition

while (1); // stay here forever

return 0;

}

Example 1


23

Make a master write 1111 0000 t0 a slave with address 1101 0000

int main (void)

{







return 0;

}

i2c_init ()

{

TWSR = 0x00; // set pre-scalar bits to zero

TWBR = 0x47; // SCL frequency is 50K for XTAL = 8MHz

TWCR = 0x04; // enable TWI module

}

Set the TWI module clock frequency (TWBR, TWPS)

Enable TWI module by setting TWEN bit in TWCR

Example 1


24


int main (void)

{







return 0;

}

void i2c_start ()

{

TWCR = (1 << TWINT) | (1 << TWSTA) | (1 << TWEN);

while ((TWCR & (1 << TWINT)) == 0)

}

Set TWINT (clear the flag to make it ready)

Set TWSTA (generate start signal as bus is free)

Check TWINT flag to complete

Example 1


25


int main (void)

{







return 0;

}

void i2c_write (unsigned char data)

{

TWDR = data;

TWCR = (1 << TWINT) | (1 << TWEN);


}

Copy the data byte to the TWDR

Set TWEN, TWINT, Check TWINT flag to complete

Example 1


26


int main (void)

{







return 0;

}

void i2c_stop ( )

{

TWCR = (1 << TWINT) | (1 << TWEN) | (1 << TWSTO);

}

Class Exercise 1


27

A master reads from a slave with address 1101000 and displays

the result on PORT A

Class Exercise 1


28



int main (void)

{

unsigned char I = 0;

DDRA = 0xFF; // Port A is output

i2c_init (); // initialize I2C for Master Mode


i2c_write (0b11010001); // Transmit SLA and R(1)

i = i2c_read ( 1 ); // Read one byte of Data

PORTA = i; // Send received data to Port A



return 0;

}

Class Exercise 1


29



int main (void)

{










return 0;

}

void i2c_init ()

{

TWSR = 0x00; // set pre-scalar bits to zero

TWBR = 0x47; // SCL frequency is 50K for XTAL = 8MHz

TWCR = 0x04; // enable TWI module

}

Class Exercise 1


30



int main (void)

{










return 0;

}

void i2c_start ()

{

TWCR = (1 << TWINT) | (1 << TWSTA) | (1 << TWEN);


}

Class Exercise 1


31



int main (void)

{










return 0;

}

void i2c_write (unsigned char data)

{

TWDR = data;

TWCR = (1 << TWINT) | (1 << TWEN);


}

Class Exercise 1


32



int main (void)

{










return 0;

}

unsigned char i2c_read (unsigned char isLast)

{

if (isLast == 0);

TWCR = (1 << TWINT) | (1 << TWEN) | (1 << TWEA);

else

TWCR = (1 << TWINT) | (1 << TWEN);


return TWDR;

}

Class Exercise 1


33



int main (void)

{










return 0;

}

void i2c_stop ( )

{

TWCR = (1 << TWINT) | (1 << TWEN) | (1 << TWSTO);

}

Home Task and Assignment


34

Home Task

Q. No. 1: Understand the working of Slave Node whilereading and writing the data.

Q. No. 2: Understand C program for the Read andWrite Operations

Assignment No 4:

Q. No 1 – 6 : Programs 1 – 6 in C for I2C Protocol

Q. No 7: Explain working of Multibyte Burst Readoperation

Date post:	18-Aug-2020
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