3Gb/s SDI Interface

Yannick LE DREAU

3Gb/s SDI Interface

SMPTE Standards for 3Gb/s Interface

Physical Layer Specification

Mapping Structures

3Gb/s Measurements

3Gb/s Test Signals

04/22/23 3Gb/s SDI Interface2

Hybrid Facility


3Gb/s SMPTE 424M

1.5Gb/s SMPTE 292M

270Mb/s

Dual Link SMPTE 372M

Physical LayerCable TypeTerminationInter-Connections

Picture

Formats

RRGGBB((AA))

YYCbCbCrCr

44::44::44::44

RRGGBB

44::22::22

12-bit12-bit

10-bit10-bit

Sampling Structures

Physical Layer

HD

DVD

Blu-Ray

SD

TransmissionMedia

Dual Link Format

Using existing HD-SDI infrastructure

Requires two signal paths– Link A & Link B

SMPTE 352M to identify links

Mapping various formats into existing HD-SDI structure

Problems Interconnection issues

Swapped or Missing links

Cable Path different for each Link


Signal Format Sampling Structure

/ Pixel Depth

Frame/ Field Rate

4:2:2 (Y’C’bC’r) / 10-bit

60, 60/1.001 & 50 P

4:4:4 (R’G’B’)4:4:4:4 (R’G’B’ + A)/ 10-bit

30. 30/1.001, 25, 24 & 24/1.001, P, PsF60, 60/1.001 & 50 fields interlaced4:4:4 (R’G’B’)

/ 12-bit

4:4:4 (Y’C’bC’r) 4:4:4:4 (Y’C’bC’r + A) / 10-bit

4:4:4 (Y’C’bC’r) / 12-bit

4:2:2 (Y’C’bC’r) / 12-bit

Why 3Gb/s SDI and High Speed Data?

Work at the highest resolution (Bit Depth and Colorspace) possible prior to rendering the product.

In standard HD-SDI limited to 4:2:2 YCbCr only at 10-bit

With Dual Link & 3Gb/s, users can:– Increase color range from 10 bits to 12 bits– Switch from 4:2:2 to 4:4:4 Sampling to the total

chrominance Bandwidth– Work in the RGB domain for easier integration with Special

Effects editors, and Telecine applications

Digital cinema cameras now being adopted for feature films, television shows, and even commercials

– Panavision Genesis™– Attack of the Clones, Revenge of the Sith, Apocalypto, …

– Thomson Viper FilmStream™


SMPTE424M Signal/Data Serial Interface Defines the transport of bit-serial data structure for 3.0Gb/s

Using a single coaxial cable interface

Supports either 10 or 12 bits data words

Mapped into two virtual interfaces – 10 bit parallel data streams (Data Stream One & Data Stream Two)


Data stream one of the virtual interfaceInterface Frequency 148.5MHz or148.5/1.001 MHz

Data stream two of the virtual interfaceInterface Frequency 148.5MHz or148.5/1.001 MHz

SA

V

EA

V

+ L

ine

No.

+ C

RC

Digital Active LineActive Picture or Ancillary Data

SA

V

Digital Line BlankingBlanking Level or Ancillary Data

SA

V

EA

V

+ L

ine

No.

+ C

RC

Digital Active LineActive Picture or Ancillary Data

SA

V

Digital Line BlankingBlanking Level or Ancillary Data

Digital Line Period

Image Structure Example of image mapping structure for 4:2:2 YCbCr 10 bits 60/59.94


SA

V(3

FF

h)

SA

V(0

00

h)

SA

V(0

00

h)

SA

V(X

YZ

h)

C’B

’0

C’R

’0C

’B’1

C’R

’1

Digital Active Line

C’R

’95

9C

’B’9

59

EA

V(3

FF

h)

EA

V(0

00

h)

EA

V(0

00

h)

EA

V(X

YZ

h)

LN

0

LN

1

CR

0

CR

1 Optional Ancillary

Data

SA

V(3

FF

h)

SA

V(0

00

h)

SA

V(0

00

h)

SA

V(X

YZ

h)

SA

V(3

FF

h)

SA

V(0

00

h)

SA

V(0

00

h)

SA

V(X

YZ

h)

Y’ 0 Y’1

Y’2

Y’3 Digital Active Line

Y’1

91

9Y

’19

18

EA

V(3

FF

h)

EA

V(0

00

h)

EA

V(0

00

h)

EA

V(X

YZ

h)

LN

0

LN

1

CR

0

CR


Data

SA

V(3

FF

h)

SA

V(0

00

h)

SA

V(0

00

h)

SA

V(X

YZ

h)

SA

VDigital Line

BlankingSA

V Digital Active LineActive Picture or Ancillary Data

EA

V

+ L

ine

No.

+ C

RC

Data Stream OneVirtual Interface

Data Stream TwoVirtual Interface

Digital Line Period

Image Structure Multiplexed

Data Stream one and two of the virtual interfaced are multiplexed together producing twice the data rate

Channel Coding uses NRZI


SA

V(3

FF

h)

SA

V(0

00

h)

SA

V(0

00

h)

SA

V(X

YZ

h)

Y’ 0

Y’1

Y’2

Y’3

Digital Active Line

Y’1

91

9Y

’19

18

EA

V(3

FF

h)

EA

V(0

00

h)

EA

V(0

00

h)

EA

V(X

YZ

h)

LN

0

LN

1

CR

0

CR

1

Optional Ancillary Data

SA

V(3

FF

h)

SA

V(0

00

h)

SA

V(0

00

h)

SA

V(X

YZ

h)

Data Stream OneVirtual Interface

SA

V(3

FF

h)

SA

V(0

00

h)

SA

V(0

00

h)

SA

V(X

YZ

h)

C’B

’0

C’R

’0

C’B

’1C

’R’1 Digital Active Line

C’R

’95

9C

’B’9

59

EA

V(3

FF

h)

EA

V(0

00

h)

EA

V(0

00

h)

EA

V(X

YZ

h)

LN

0

LN

1

CR

0

CR

1


SA

V(3

FF

h)

SA

V(0

00

h)

SA

V(0

00

h)

SA

V(X

YZ

h)

Data Stream TwoVirtual Interface

SA

V(3

FF

h)S

AV

(3F

Fh)

SA

V(0

00h)

SA

V(0

00h)

SA

V(0

00h)

SA

V(0

00h)

SA

V(X

YZ

h)S

AV

(XY

Zh)

C’B

’0Y

’ 0

Y’1

Y’2

Y’3

C’R

’0

C’B

’1

C’R

’1

Digital Active Line

C’B

’959

C’R

’959

Y’1

919

Y’1

918

EA

V(3

FF

h)

EA

V(0

00h)

EA

V(0

00h)

EA

V(X

YZ

h)

LN0

LN1

CR

0

CR

1

SA

V(3

FF

h)

SA

V(0

00h)

SA

V(0

00h)

SA

V(X

YZ

h)

EA

V(3

FF

h)

EA

V(0

00h)

EA

V(0

00h)

EA

V(X

YZ

h)

LN0

LN10

CR

0

CR

1

SA

V(3

FF

h)

SA

V(0

00h)

SA

V(0

00h)

SA

V(X

YZ

h)Optional Ancillary Data

Multiplexed 10-bitParallel interface

Mapping 2x SMPTE 292 HD-SDI Level B

Mapping of two parallel 10 bit interfaces with same line and frame structure in conformance with SMPTE292.

Payload Identifier


C’B

’0

Y’ 0

Y’1

Y’2

Y’3

C’R

’0

C’B

’1

C’R

’1

C’B

’959

C’R

’959

Y’1

919

Y’1

918

EA

V(3

FF

h)

EA

V(0

00h)

EA

V(0

00h)

EA

V(X

YZ

h)

LN0

LN1

CR

0

CR

1

SA

V(3

FF

h)

SA

V(0

00h)

SA

V(0

00h)

SA

V(X

YZ

h)

EA

V(3

FF

h)

EA

V(0

00h)

EA

V(0

00h)

EA

V(X

YZ

h)

LN0

LN10

CR

0

CR

1

SA

V(3

FF

h)

SA

V(0

00h)

SA

V(0

00h)

SA

V(X

YZ

h)


EAV SAV

10-bit multiplex inaccordance with SMPTE 292M

LN CRC

Interface clock frequency148.5MHz or 148.5MHz/1.001 MHz

Mapping Nomenclature Byte 1 Video payload and digital interface

SMPTE 372M Dual link payload on a 3 Gb/s serial digital interface 8Ah

2 x720-line video payload on a 3 Gb/s serial digital interface 8Bh

2 x1080-line video payload on a 3 Gb/s serial digital interface 8Ch

2 x483/576-line video payload on a 3 Gb/s serial digital interface 8Dh

Mapping 2x SMPTE 292 HD-SDI Level B


Level B “Fast Progressive” Dual Link SMPTE372M SMPTE 274M 4:2:2 YCbCr 10 bit 60,59,94 & 50


C’b

0

Y’ 0

C’r

0

Y’ 1

Y’1

919

C’r

959

EA

V(3

FF

h)

EA

V(0

00h)

EA

V(0

00h)

EA

V(X

YZ

h)

LN0

LN1

CR

0

CR


Data

SA

V(3

FF

h)

SA

V(0

00h)

SA

V(0

00h)

SA

V(X

YZ

h)

C’b

0

Y’ 0

C’r

1

Y’ 1

Y’1

919

C’r

959

EA

V(3

FF

h)

EA

V(0

00h)

EA

V(0

00h)

EA

V(X

YZ

h)

LN0

LN1

CR

0

CR


Data

SA

V(3

FF

h)

SA

V(0

00h)

SA

V(0

00h)

SA

V(X

YZ

h)

Y’ 0

Y’ 1

Y’ 2

Y’ 3

Y’ 1

919

Y’ 1

918

Y’ 1

920

Y’ 1

921

Y’ 1

922

Y’ 1

923

Y’ 1

924

Y’ 1

925

Y’ 1

926

Y’ 1

927

C’r

959

C’b

959

C’b

960

C’b

961

C’b

962

C’b

963

C’r

960

C’r

961

C’r

962

C’r

963

C’r

0

C’r

1

C’r

(N

)

C’r

(N

-1)

C’r

(N

-2)

C’b

(N

)

C’b

(N

-1)

C’b

(N

-2)

C’b

0

C’b

1

Y’ (

N)

Y’ (

N-1

)

Y’ (

N-2

)

Y’ (

N-3

)

Y’ (

N-4

)

Y’ (

N-5

)

Y’ Data

C’b Data

C’r Data

Interface sampling frequency= 148.5MHz or 148.5/1.001 MHzas defined in SMPTE 274M



Interface sampling frequency= 148.5MHz or 148.5/1.001 MHz


Data Stream One Of the virtual interfaceLink A

Data Stream Two Of the virtual interfaceLink B

C’b

959

Y’1

918

C’b

959

Y’1

918

Dual Link SMPTE372MSMPTE 274M 4:2:2 YCbCr 10 bit 60,59,94 & 50


SMPTE425M Signal/Data Serial Interface Source Image Format (Level A)


Mappingstructure

ReferenceSMPTE

StandardPicture Format

Signal Format sampling structure/pixel Depth

Frame/Field Rates

1 274M 1920 1080 4:2:2 (Y’C’BC’R)/10-bit 60, 60/1.001 and 50 Frames Progressive

2

296M 1280 x 720

4:4:4 (R’G’B’), 4:4:4:4 (R’G’B’ +A)/10-bit 60, 60/1.001 and 50 Frames Progressive

30, 30/1.001, 25, 24 and 24/1.001 Frames Progressive4:4:4 (Y’C’BC’R),

4:4:4:4 (Y’C’BC’R+A)/10-bit

274M 1920 x 1080

4:4:4 (R’G’B’), 4:4:4:4 (R’G’B’ +A)/10-bit 60, 60/1.001 and 50 Fields Interlaced

30, 30/1.001, 25, 24 and 24/1.001 Frames Progressive4:4:4 (Y’C’BC’R),

4:4:4:4 (Y’C’BC’R+A)/10-bit

3

274M 1920 x 1080

4:4:4 (R’G’B’)/12-bit 60, 60/1.001 and 50 Fields Interlaced30, 30/1.001, 25, 24 and 24/1.001 Frames Progressive4:4:4 (Y’C’BC’R)/12-bit

428 2048 1080 4:4:4 (X’Y’Z’)/12-bit 24 Frames Progressive, PsF

4 274M 1920 x 1080 4:2:2 (Y’C’BC’R)/12-bit30, 30/1.001, 25, 24 and 24/1.001 Frames Progressive60, 60/1.001 and 50 Fields Interlaced

Comparison of Level A vs. Level B

1080p 50/59.94/60– SMPTE 425 Mapping structure 1 – alternates Y and Cb/Cr samples,

effect is similar to standard HD-SDI but at twice the rate

– SMPTE 372M §4.1 – alternates entire lines, each with Y and Cb/Cr


Stream 1(Line N+1)

Cb0 Cr0 Cb1 … Cb959 Cr959

Y0 Y1 Y2 … Y1918 Y1919

Stream 2(Line N)

Cb0 Cr0 Cb1 … Cb959 Cr959

Y0 Y1 Y2 … Y1918 Y1919

Stream 1Y0 Y2 Y4 … Y1916 Y1918

Y1 Y3 Y5 … Y1917 Y1919

Stream 2Cb0 Cb1 Cb2 … Cb958 Cb959

Cr0 Cr1 Cr2 … Cr959 Cr959

SMPTE 425M Mapping 1SMPTE 274M 4:2:2 YCbCr 10 bit 60,59,94 & 50


Y’ 0

Y’1

Y’2

Y’3

Y’1

919

Y’1

918

EA

V(3

FF

h)

EA

V(0

00h)

EA

V(0

00h)

EA

V(X

YZ

h)

LN0

LN1

CR

0

CR

1Optional Ancillary Data

SA

V(3

FF

h)

SA

V(0

00h)

SA

V(0

00h)

SA

V(X

YZ

h)

C’B

’0

C’R

’0

C’B

’1

C’R

’1

C’R

’959

C’B

’959

EA

V(3

FF

h)

EA

V(0

00h)

EA

V(0

00h)

EA

V(X

YZ

h)

LN0

LN1

CR

0

CR

1


SA

V(3

FF

h)

SA

V(0

00h)

SA

V(0

00h)

SA

V(X

YZ

h)

Y’ 0

Y’1

Y’2

Y’3

Y’1

919

Y’1

918

Y’1

920

Y’1

921

Y’1

922

Y’1

923

Y’1

924

Y’1

925

Y’1

926

Y’1

927

C’R

959

C’B

959

C’B

960

C’B

961

C’B

962

C’B

963

C’R

960

C’R

961

C’R

962

C’R

963

C’R

0

C’R

1

C’R

(N

)

C’R

(N

-1)

C’R

(N

-2)

C’B

(N

)

C’B

(N

-1)

C’B

(N

-2)

C’B

0

C’B

1

Y’ (

N)

Y’ (

N-1

)

Y’ (

N-2

)

Y’ (

N-3

)

Y’ (

N-4

)

Y’ (

N-5

)

Y’ Data

C’b Data

C’r Data






Data Stream One Of the virtual interface

Data Stream Two Of the virtual interface

ReferenceSMPTE Standard

FrameRate

First active sample number

Last activesample number

Last Samplenumber 'n'(total lines)

274M Sys 1 & 2 60 or 60/1.001 0 1919 2199

274M Sys 3 50 0 1919 2639

SMPTE 425M Mapping 1 Data Display Data mode SMPTE 274M 4:2:2 YCbCr 10 bit 60,59,94 & 50


SMPTE 425M Mapping 1 Data Display Video modeSMPTE 274M 4:2:2 YCbCr 10 bit 60,59,94 & 50


SMPTE 425M Mapping 24:4:4:4 RGB (A) or 4:4:4:4 YCbCr (A) 10-bit


Y0

A0 Pb0

Pr0 Y1

A1 Pb1

Pr1 Y2

A2 Pb2

Pr2Data Stream One

Data Stream Two


FrameRate




296M Sys 1 & 2 60 or 60/1.001 0 1279 1649

296M Sys 3 50 0 1279 1979

274M Sys 4 & 5, 7 & 8 30 or 30/1.001 0 1919 2199

296M Sys 4 & 5 30 or 30/1.001 0 1279 3299

274M Sys 6 & 9 25 0 1919 2639

296M Sys 6 25 0 1279 3959

274M Sys 10 & 11 24 or 24/1.001 0 1919 2749

296M Sys 7 & 8 24 or 24/1.001 0 1279 4124

G0

A0 B0

R0 G1

A1 B1

R1 G2

A2 B2

R2

SMPTE 425M Mapping 24:4:4:4 RGB (A) or 4:4:4:4 YCbCr (A) 10-bit


G’ 0

R’0

G’1

R’1

R’ (

a)

G’ (

a)

EA

V(3

FF

h)

EA

V(0

00h)

EA

V(0

00h)

EA

V(X

YZ

h)

LN0

LN1

CR

0

CR


SA

V(3

FF

h)

SA

V(0

00h)

SA

V(0

00h)

SA

V(X

YZ

h)

A 0

B’0

A 1

B’1

B’ (

a)

A (

a)

EA

V(3

FF

h)

EA

V(0

00h)

EA

V(0

00h)

EA

V(X

YZ

h)

LN0

LN1

CR

0

CR

1


SA

V(3

FF

h)

SA

V(0

00h)

SA

V(0

00h)

SA

V(X

YZ

h)

G’ / Y’ Data







G’(a

)

G’(a

+1)

G’(a

+2)

G’(a

+3)

G’(a

+4)

G’(N

-2)

G’(N

-1)

G’ (

N)

G’ 0

G’ 1

B’(a

)

B’(a

+1)

B’(a

+2)

B’(a

+3)

B’(a

+4)

B’(N

-2)

B’(N

-1)

B’ (

N)

B’ 0

B’ 1

R’(a

)

R’(a

+1)

R’(a

+2)

R’(a

+3)

R’(a

+4)

R’(N

-2)

R’(N

-1)

R’ (

N)

R’ 0

R’ 1

A (

a)

A (

a+1)

A (

a+2)

A (

a+3)

A (

a+4)

A (

N-2

)

A (

N-1

)

A (

N)

A 0

A 1


Interface sampling frequency= 74.25MHz or 74.25/1.001 MHzas defined in SMPTE 274M A’ Data

B’ / C’b Data

R’/ C’b Data

R’(a

-1)

G’(a

-1)

B’ (

a-1)

A (

a-1)

G’(a

-1)

B’(a

-1)

R’(a

-1)

A (

a-1)


4:4:4(:4) 10-bit– SMPTE 425 Mapping structure 2 – R samples always on stream 1, B on

stream 2. Alpha channel on stream 2.

– SMPTE 372M §4.2 – Even B+R samples on stream 1, odd B+R samples on stream 2. Alpha channel on stream 2.


Stream 1Y0 or G0 Y1 or G1 Y2 or G2 … Y/G1919

Cr0 or R0 Cr1 or R1 Cr2 or R2 … Cr/R1919

Stream 2A0 A1 A2 … A1919

Cb0 or B0 Cb1 or B1 Cb2 or B2 … Cb/B1919

Stream 1Cb0 or B0 Cr0 or R0 Cb2 or B2 … Cr/R1918

Y0 or G0 Y1 or G1 Y2 or G2 … Y/G1919

Stream 2Cb1 or B1 Cr1 or R1 Cb3 or B3 … Cr/R1919

A0 A1 A2 … A1919

SMPTE 425M Mapping 34:4:4 RGB or 4:4:4 YCbCr or XYZ 12-bit


RGB/XYZ[11:9]a/n

RGB/XYZ[8:6]a/n

RGB/XYZ[2:0]a/n

RGB/XYZ[5:3] a/n

RGB/XYZ[11:9 ]a+1/n+1

RGB/XYZ[8:6]a+1/n+1

RGB/XYZ[2:0]a+1/n+1

RGB/XYZ[5:3]a+1/n+1

RGB/XYZ[11:9 ]a+2/n+2

RGB/XYZ[8:6 ]a+2/n+2

RGB/XYZ[2:0]a+2/n+2

RGB/XYZ[5:3]a+2/n+2Data Stream One

Data Stream Two

G’B’R’/X’Y’Z’(a) / (n) [x:y] bit structure mapping into data words of the virtual interface

Bit Number

Data Stream 9 8 7 6 5 4 3 2 1 0

Data Stream OneFirst word ofSample (a) / (n)

Not B8R’/C‘r/X'

(a) / (n) [11:9]G’/Y'/Y’

(a) / (n) [11:9]B'/C’b/Z’ (a) / (n)

[11:9]


Not B8R’/C‘r/X'

(a) / (n) [5:3]G’/Y'/Y’

(a) / (n) [5:3]B'/C’b/Z’

(a) / (n) [5:3]

Data Stream TwoFirst word ofSample (a) / (n)

Not B8R’/C‘r/X’

(a) / (n) [8:6]G’/Y'/Y’

(a) / (n) [8:6]B'/C’b/Z’

(a) / (n) [8:6]


Not B8R’/C‘r/X’

(a) / (n) [2:0] G’/Y'/Y’

(a) / (n) [2:0] B'/C’b/Z’

(a) / (n) [2:0]

SMPTE 425M Mapping 3 4:4:4 RGB or 4:4:4 YCbCr or XYZ 12-bit


GBR/XYZ[11:9]a/n

GBR/XYZ[8:6]a/n

GBR/XYZ[2:0]a/n

GBR/XYZ[5:3] a/n

GBR/XYZ[11:9 ]a+1/n+1

GBR/XYZ[8:6]a+1/n+1

GBR/XYZ[2:0]a+1/n+1

GBR/XYZ[5:3]a+1/n+1

GBR/XYZ[11:9 ]a+2/n+2

GBR/XYZ[8:6 ]a+2/n+2

GBR/XYZ[2:0]a+2/n+2

GBR/XYZ[5:3]a+2/n+2Data Stream One

Data Stream Two

Location of the first and last active samples for 4:4:4 (R’G’B’) and (X’Y’Z’)/12-bit Signals


FrameRate



(a)


274M Sys 4 & 5, 7 & 8 30 or 30/1.001 0 1919 2199

274M Sys 6 & 9 25 0 1919 2639

274M Sys 10 & 11 24 or 24/1.001 0 1919 2749

yyyM 24 0 2039 2749

SMPTE 425M Mapping 3 4:4:4 RGB or 4:4:4 YCbCr or XYZ 12-bit


RG

B(0

)11

:9

RG

B(0

)5:3

RG

B(1

)11

:9

RG

B(1

)5:3

RG

B (

a)5

:3

RG

B (

a)1

1:9

EA

V(3

FF

h)

EA

V(0

00h)

EA

V(0

00h)

EA

V(X

YZ

h)

LN0

LN1

CR

0

CR


SA

V(3

FF

h)

SA

V(0

00h)

SA

V(0

00h)

SA

V(X

YZ

h)

RG

B (

0)8

:6

RG

B (

0)2

:0

RG

B (

1)8

:6

RG

B (

1)2

:0

RG

B (

a)2

:0

RG

B (

a)8

:6

EA

V(3

FF

h)

EA

V(0

00h)

EA

V(0

00h)

EA

V(X

YZ

h)

LN0

LN1

CR

0

CR

1


SA

V(3

FF

h)

SA

V(0

00h)

SA

V(0

00h)

SA

V(X

YZ

h)

G’/ Y’ /X’ Data







G/X

(a

)

G/X

(a

+1

)

G/X

(a

+2

)

G/X

(a

+3

)

G/X

(a

+4

)

G/X

(N

-2)

G/X

(N

-1)

G/X

(N

)

G/X

0

G/X

1

C'B

(a

)

C'B

(a

+1

)

C'B

(a

+2

)

C'B

(a

+3

)

C'B

(a

+4

)

C'B

(N-2

)

C'B

(N-1

)

C'B

(N

)

C'B

0

C'B

1

C'R

(a

)

C'R

(a

+1

)

C'R

(a

+2

)

C'R

(a

+3

)

C'R

(a

+4

)

C'R

(N

-2)

C'R

(N

-1)

C'R

(N

)

C'R

0

C'R

1


B’/ C’b /Y’ Data

R’/ C’r /Z’ Data

RG

B(a

-1)5

:3

RG

B(a

-1)1

1:9

RG

B (

a-1

)2:0

RG

B (

a-1

)8:6

G/X

(a

-1)

C'B

(a

-1)

C'R

(a

-1)

GBR/XYZ[11:9]a/n

GBR/XYZ[8:6]a/n

GBR/XYZ[2:0 ]a/n

GBR/XYZ[5:3] a/n

GBR/XYZ[11:9 ]a+1/n+1

GBR/XYZ[8:6]a+1/n+1

GBR/XYZ[2:0]a+1/n+1

GBR/XYZ[5:3]a+1/n+1

GBR/XYZ[11:9 ]a+2/n+2


GBR/XYZ[2:0]a+2/n+2


Data Stream Two

SMPTE 425M Mapping 34:4:4 XYZ 12-bit


XY

Z(0

)11

:9

XY

Z(0

)5:3

XY

Z(1

)11

:9

XY

Z(1

)5:3

XY

Z(a

)5:3

XY

Z(a

)11

:9

EA

V(3

FF

h)

EA

V(0

00h)

EA

V(0

00h)

EA

V(X

YZ

h)

LN0

LN1

CR

0

CR


SA

V(3

FF

h)

SA

V(0

00h)

SA

V(0

00h)

SA

V(X

YZ

h)

XY

Z (

0)8

:6

XY

Z (

0)2

:0

XY

Z (

1)8

:6

XY

Z (

1)2

:0

XY

Z (

a)2

:0

XY

Z (

a)8

:6

EA

V(3

FF

h)

EA

V(0

00h)

EA

V(0

00h)

EA

V(X

YZ

h)

LN0

LN1

CR

0

CR

1


SA

V(3

FF

h)

SA

V(0

00h)

SA

V(0

00h)

SA

V(X

YZ

h)

G’/X’ Data







G/X

(a

)

G/X

(a

+1

)

G/X

(a

+2

)

G/X

(a

+3

)

G/X

(a

+4

)

G/X

(N

-2)

G/X

(N

-1)

G/X

(N

)

G/X

0

G/X

1

C'B

(a

)

C'B

(a

+1

)

C'B

(a

+2

)

C'B

(a

+3

)

C'B

(a

+4

)

C'B

(N-2

)

C'B

(N-1

)

C'B

(N

)

C'B

0

C'B

1

C'R

(a

)

C'R

(a

+1

)

C'R

(a

+2

)

C'R

(a

+3

)

C'R

(a

+4

)

C'R

(N

-2)

C'R

(N

-1)

C'R

(N

)

C'R

0

C'R

1


B’/Y’ Data

R’/Z’ Data

XY

Z(a

-1)5

:3

XY

Z(a

-1)1

1:9

XY

Z (

a-1

)2:0

XY

Z (

a-1

)8:6

G/X

(a

-1)

C'B

(a

-1)

C'R

(a

-1)

GBR/XYZ[11:9]a/n

GBR/XYZ[8:6]a/n

GBR/XYZ[2:0 ]a/n

GBR/XYZ[5:3] a/n

GBR/XYZ[11:9 ]a+1/n+1

GBR/XYZ[8:6]a+1/n+1

GBR/XYZ[2:0]a+1/n+1

GBR/XYZ[5:3]a+1/n+1

GBR/XYZ[11:9 ]a+2/n+2


GBR/XYZ[2:0]a+2/n+2


Data Stream Two


4:4:4 12-bit– SMPTE 425 Mapping structure 3 – every 10 bit word includes 3 bits of

each of the three channels (four words comprise complete sample)

– SMPTE 372M §4.3 and §4.4 – most significant 10 bits of the three channels appear as in §4.2 formats, and two LSBs of each channel are grouped together into a single word that displaces the A channel

9 8 7 6 5 4 3 2 1 0

Stream 1B8 Cr or R [11:9] Y or G [11:9] Cb or B [11:9]

B8 Cr or R [5:3] Y or G [5:3] Cb or B [5:3]

Stream 2B8 Cr or R [8:6] Y or G [8:6] Cb or B [8:6]

B8 Cr or R [2:0] Y or G [2:0] Cb or B [2:0]

Stream 1Cb0/B0 Cr0 or R0 … Cb/B1918 Cr/R1918

Y0 or G0 Y1 or G1 … Y/G1918 Y/G1919

Stream 2Cb1 or B1 Cr1 or R1 … Cb/B1919 Cr/R1919

SMPTE 425M Mapping 44:2:2 YCbCr 12 bit

G’/X’ samples maybe replaced with Y’ samples

B’/Y’ samples maybe replaced with C’b samples

R’/Z’ samples maybe replaced with C’r samples


Y[11:6]a-1/n-1

Cb[11:6]a/n

Cb[5:0 ]a/n

Y[5:0] a-1/n-1

Y[11:6 ]a/n

Cr[11:6]a/n

Cr[5:0]a/n

Y[5:0]a/n

Y[11:6 ]a+1/n+1

Cb[11:6 ]a+1/n+!

Cb[5:0]a+1/n+1

Y[5:0]a+1/n+1Data Stream One

Data Stream Two


FrameRate



(a)


274M Sys 4 & 5, 7 & 8 30 or 30/1.001 0 1919 2199

274M Sys 6 & 9 25 0 1919 2639

274M Sys 10 & 11 24 or 24/1.001 0 1919 2749



Y[11:6]a-1/n-1

Cb[11:6]a/n

Cb[5:0 ]a/n

Y[5:0] a-1/n-1

Y[11:6 ]a/n

Cr[11:6]a/n

Cr[5:0]a/n

Y[5:0]a/nData Stream One

Data Stream Two

Bit Number

Data Stream 9 8 7 6 5 4 3 2 1 0


1 Reserved Y' (a) / (n) [11:6]


1 Reserved Y' (a) / (n) [5:0]

Bit Number

Data Stream 9 8 7 6 5 4 3 2 1 0


1 Reserved C‘B (a) / (n) [11:6]


1 Reserved C‘B (a) / (n) [5:0]


1 Reserved C‘R (a) / (n) [11:6]


1 Reserved C‘R (a) / (n) [5:0]



Y’ (

0)1

1:6

Y‘ (

0)5

:0

Y’ (

1)1

1:6

Y’ -

1)5

:0

Y’ (

a)5

:0

Y’ (

a)1

1:6

EA

V(3

FF

h)

EA

V(0

00h)

EA

V(0

00h)

EA

V(X

YZ

h)

LN0

LN1

CR

0

CR


SA

V(3

FF

h)

SA

V(0

00h)

SA

V(0

00h)

SA

V(X

YZ

h)

C’B

(0

)11

:6

C’B

(0

)5:0

C’R

(0

)11

:6

C’R

(0

)5:0

C’R

(a

)5:0

C’R

(a

)11

:6

EA

V(3

FF

h)

EA

V(0

00h)

EA

V(0

00h)

EA

V(X

YZ

h)

LN0

LN1

CR

0

CR

1


SA

V(3

FF

h)

SA

V(0

00h)

SA

V(0

00h)

SA

V(X

YZ

h)







C'B

(a

)

C'B

(a

+1

)

C'B

(a

+2

)

C'B

(N-1

)

C'B

(N

)

C'B

0

C'B

1

C'R

(a

)

C'R

(a

+1

)

C'R

(a

+2

)

C'R

(N

-1)

C'R

(N

)

C'R

0

C'R

1

C’B Data

C’R Data

Y’ (

a-1

)5:0

Y’ (

a-1

)11

:6

C’B

(a

)5:0

C’B

(a

)11

:6C

'B (

a-1

)C

'R (

a-1

)

Y[11:6]a-1/n

Cb[11:6]a/n

Cb[5:0 ]a/n

Y[5:0] a-1/n

Y[11:6 ]a/n

Cr[11:6]a/n

Cr[5:0]a/n

Y[5:0]a/nData Stream One

Data Stream Two

Y’ 0

Y’1

Y’2

Y’3

Y’(a

-3)

Y’(a

-2)

Y’(a

-1)

Y’ (

a)

Y’(a

+1)

Y’(a

+2)

Y’ (

a+3)

Y’ (

a+4)

Y’ (

N)

Y’ (

N-1

)

Y’ (

N-2

)

Y’ (

N-3

)

Y’ DataInterface sampling frequency= 74.25MHz or 74.25/1.001 MHzas defined in SMPTE 274M


4:2:2 12-bit– SMPTE 425 Mapping structure 4 – two 10 bit words each carry 6 bits of

each of the three channels. No alpha channel is supported, despite the available space (four bits unused per word).

– SMPTE 372M §4.5 – Stream 1 carries the 10 MSBs of each sample in the familiar Cb/Y/Cr/Y sequence, and stream 2 carries a word of LSBs (2 bits per channel) plus a 10 bit alpha channel.

Stream 1Cb0 [11:2] Cr0 [11:2] … Cb959 [11:2] Cr959 [11:2]

Y0 [11:2] Y1 [11:2] … Y1918 [11:2] Y1919 [11:2]

Stream 2A0 A1 … A1918 A1919

Stream 1Y0 [11:6] Y1 [11:6] … Y1919

Y0 [5:0] Y1 [5:0] … Y1919

Stream 2Cb0 [11:6] Cr0 [11:6] … Cr959

Cb0 [5:0] Cr0 [5:0] … Cr959

3Gb/s Serial Digital Interface

Pk-to-Pk Amplitude 800mV +/- 10%

DC Offset 0.0V +/- 0.5V

Rise/Fall Time between 20% & 80% no greater than 135ps and not differ by more than 50ps

Overshoot rise/fall not to exceed 10% of amplitude

Timing Jitter <= 2UI above 10Hz

Alignment Jitter <= 0.3UI above 100kHz04/22/23 3Gb/s SDI Interface32

Eye Specifications per SMPTE Standards


Rise/Fall Time

SD HD 3Gb/s

Shall be no less than 0.4ns, no greater than 1.50ns, and shall not differ by more than 0.5ns

Shall be no greater than 270ps and shall not differ by more than 100ps

Shall be no greater than 135ps and shall not differ by more than 50ps

Unit Interval

SD (259M)

HD (292M)

3Gb/s (424M)

3.7ns 673.4ps 336.7ps


How to Make Eye Measurement

Eye Display

Launch Amplitude

Short Length of Cable

Color Bar Test Signal

Automated Measurements

– Available on WM8300

– Amplitude Histogram

– Simplifies The Task

Infinite persistence can aid in seeing eye opening

Rise TimeFall Time

80%

20%

Eye Pattern Distortions

Long cable Decrease in amplitude

Decrease in Frequency response

Eye opening narrows

Rise/Fall time increases

Termination Incorrect termination

causes overshoot and undershoot

Shift in Eye Crossing Shifts 50% point of eye

opening

Caused by unequal rise or fall time


The variation in position of a signal’s transitions relative to those of a clock extracted from the signal.

The variation in position of a signal’s transitions occurring at a rate greater than a specified frequency, typically 10Hz

Alignment Jitter

SD HD 3Gb/s

0.2UI (740ps) @ 1kHz

0.2UI (135ps) @ 100kHz

0.3UI (101ps) @ 100kHz Maximum

Preferred 0.2UI (67.3ps) @ 100kHz

Timing Jitter (10Hz)

SD HD 3Gb/s

0.2UI (740ps) 1.0UI (673.4ps @ 1.485Gb/s)(674ps @

1.4835Gb/s)

2.0UI(673.4ps @ 2.97Gb/s)(674ps @

2.967Gb/s)

Jitter Measurements Timing Jitter

Alignment Jitter


What is Jitter?

Definition:

Jitter is defined as the variation of a digital signal’s significant instants (such as transition points) from their ideal positions in time.

Time Interval Error – Jitter

Introduced by frequency, amplitude and phase variation in signals transition

04/22/23 3Gb/s SDI & Advanced Data Analysis37

1 UI

Tj Jitter Frequency (Hz) = 1/Tj

Jitter Amplitude (peak-to-peak)

0 1 1 0 1

1 UI

Tj Jitter Frequency (Hz) = 1/Tj

Jitter Amplitude (peak-to-peak)

0 1 1 0 1

Types of Jitter

Types of Jitter

Random– Random Process– No Discernible pattern– All devices have random jitter present– Thermal or shot noise– Model by Gaussian distribution

Deterministic– Switching PSU– Frequency response

– cable or device– Rise/Fall Time of Transition


Why noise can introduce jitter


Cable frequency responce introduces jitter

Risign edges have high frequency content

Repetitive patterns have lower frequency content

Frfequencies travel at different speed in the cable (group delay)

This effect is visible only with long cables


Methods of Measuring Jitter

The Equivalent-time Eye method constructs an– Equivalent-time Eye diagram of the signal and measures the amount the

edge samples in the Eye vary from their ideal positions.

The Real-time Acquisition method – Applies signal processing algorithms to one or more acquisition records

captured in real-time from single trigger events to measure the amount each signal edge in the acquisition record varies from its ideal position.

The Phase Demodulation method – Applies two appropriately filtered clock signals to a phase detector. The

output from the phase detector is the demodulated jitter signal.

Color Bar Test signal Recommended not Pathological


EQ time Acquisition


Phase demodulation Method


PK-Pk but in which time interval?



How to Make Jitter Measurements

Jitter Meter shows direct readout

Ability to measure Timing and Alignment jitter simultaneously

Jitter waveform show variation of signal related to line and field rate of video signal

HD3G7 3 Gb/s SDI Generator/Converter Module for the TG700

All 1080-line formats of SMPTE 425 now supported– YPbPr 4:2:2/4:4:4 10/12-bit – RGB 4:4:4 10/12-bit– XYZ 4:4:4 12-bit– Complete coverage of both Level A and Level B mappings

Wide variety of standard test signals

Two signal outputs

HD-SDI input for up-converter function

Trigger output (frame pulse or 148.5 MHz clock) for external oscilloscope synchronization


SDI Checkfield Test Pattern

Defined in SMPTE RP 198 for HD-SDI

Equalizer test pattern has maximum DC content– Uses 20 bit pattern 1100000000 0110011000 (300h 198h) input to the

scrambler for the serial data stream– Produces output with repeated pattern of 19 consecutive high (low)

states followed by 1 low (high) state– Corresponds to Y=198h, Cb=Cr=300h (shade of magenta) for HD-SDI


SDI Checkfield Test Pattern

PLL test pattern has maximum low-frequency content and minimum high-frequency content

– Uses 20 bit pattern 1000000000 0100010000 (200h 110h) input to the scrambler for the serial data stream

– Produces output with repeated pattern of 20 consecutive high (low) states followed by 20 consecutive low (high) state

– Corresponds to Y=110h, Cb=Cr=200h (23.74% gray) for HD-SDI


SDI Checkfield Test Pattern for 3G-SDI

Why are the colors wrong?

In order to produce the same pathological patterns in the serial bit stream, the 10 bit words must be sequenced in the same order

This results in different colors from the familiar magenta/gray for various 3G mapping structures


HD-SDI 3G-SDI Equalizer test PLL test

Y channel Data stream 1 198h 110h

Cb/Cr channel Data stream 2 300h 200h

Level A MS1 (1080p) Level B 1080p

Data stream 1 carries the Y samples and data stream 2 carries the Cb/Cr samples, so the multiplexing is similar to HD-SDI and the pattern has the familiar colors.

In dual link, lines alternate between the two links. Therefore, in Level B, odd lines have one word for both Y and Cb/Cr samples, and even lines have the other word for both Y and Cb/Cr samples.


As it appears for other Level B formats:

Verify with data mode (not video mode) of data display


4:4:4 YCbCr 10-bit 4:4:4 GBR 12-bit 4:2:2:4 YCbCrA 12-bit


For Level A, the SDI checkfield pattern would be illegal for mapping structures 3 and 4, because unused bits would not be set to zero and parity bit would not be correct

– Mapping structure 3: not possible to encode 300h for first word of equalizer test (bit 9 would not be the complement of bit 8)

– Mapping structure 4: not possible to encode any 10 bit word other than 20Xh..23Xh

Best solution is to simply use Level A mapping structure 1


9 8 7 6 5 4 3 2 1 0

B8 Cr or R Y or G Cb or B

9 8 7 6 5 4 3 2 1 0

1 Reserved (000) Sample data [11:6] or [5:0]

Video Session Display and SMPTE352M


High Speed Data such as 3Gb/s can be monitored in a familiar way. Using traditional waveform displays

3Gb/s supports a variety of data mapping structures as defined in SMPTE 425M.

– Most equipment primarily supporting mapping structure 1.

Physical Layer Measurement using Eye and Jitter

Pathological Test Signals for Level A and Level B


Date post:	04-Feb-2016
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3Gb/s SDI Interface

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