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3T Final Internship Presentation

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CO-DEVELOPMENT MANUFACTURING INNOVATION & SUPPORT Akbar Pamungkas Sukasdi Final Internship Presentation
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Page 1: 3T Final Internship Presentation

CO-DEVELOPMENT

MANUFACTURING INNOVATION & SUPPORT

Akbar Pamungkas SukasdiFinal Internship Presentation

Page 2: 3T Final Internship Presentation

Agenda 3T BV Company Profile Introduction Assignment Project Summary Design Block Diagram Design Layout Results Recommendations

May 3, 2023www.3t.eu 2

Page 3: 3T Final Internship Presentation

Founded in 1982, 3T since 1994 45 – 50 employees (mainly MSc/BSc) Offices in Enschede (HQ) & Eindhoven Does co-development, product innovation &

support

May 3, 2023www.3t.eu 3

Page 4: 3T Final Internship Presentation

Introduction Born in Batam, Riau Islands, Indonesia 3rd year student of EPA Elektrotechniek Sep 2014 – Jan 2015 : 1st Internship Period in 3T

BV 2012 – 2016 : Bachelor of Electrical & Electronic

Engineering in Saxion University of Applied Sciences

May 3, 2023www.3t.eu 4

Page 5: 3T Final Internship Presentation

Assignment Construct and test a DC/DC Converter using push

pull topology scheme (incorporating galvanic isolation).

Topology : Push Pull Topology Input : 18 – 36 VDC Output : +/- 15 VDC Output Voltage Ripple : 150 mV peak-to-peak Efficiency : ≥ 89 % Output Power : 40 W Isolation

May 3, 2023www.3t.eu 5

Page 6: 3T Final Internship Presentation

Project Summary The project has investigated why custom DC-DC

converter should be made The project has considered that high efficiency and

low noise operation should be part of the final design

The project has recommended to give more attention to the components selection and careful PCB layout

May 3, 2023www.3t.eu 6

Page 7: 3T Final Internship Presentation

Design (Block Diagram)

May 3, 2023www.3t.eu 7

Page 8: 3T Final Internship Presentation

Design (PCB Layout)

May 3, 2023www.3t.eu 8

All components are on the top Short traces Compact size (143 mm x 56.5 mm) Most SMD components are used Provides heatsink Isolation

Page 9: 3T Final Internship Presentation

Design (PCB Layout) Component top:

Top Layer (Signal Layer):

May 3, 2023www.3t.eu 9

Page 10: 3T Final Internship Presentation

Design (PCB Layout) Second Layer (Ground Plane):

• Barrier width : 1.5 mm

Third Layer (Power Plane)

May 3, 2023www.3t.eu 10

Page 11: 3T Final Internship Presentation

Design (PCB Layout)

May 3, 2023www.3t.eu 11

Bottom Layer (Signal Layer):

Page 12: 3T Final Internship Presentation

Results Stable +/- 15 VDC dual output voltages Low ripple output voltages (17.60 mV p-p) High efficiency up to 92% (Full Load)

May 3, 2023www.3t.eu 12

Page 13: 3T Final Internship Presentation

Results Thermal picture:

May 3, 2023www.3t.eu 13

Page 14: 3T Final Internship Presentation

Recommendations Integrated Heatsink (Thermal Management) Use Thermal Blind / Buried Vias (Thermal

Management) Package Development (Thermal Management) MOSFETs w/ ultra low gate charge (Qg) (Efficiency) Ultra low forward voltage Schottky diodes

(Efficiency) Use lead wire instead of solid copper wire

(Efficiency)

May 3, 2023www.3t.eu 14

Page 15: 3T Final Internship Presentation

3T B.V.Institutenweg 6 Esp 4017521 PK Enschede 5633 AJ EindhovenThe Netherlands The Netherlands

T. +31 53 4 33 66 33F. +31 53 4 33 68 69E. [email protected]. www.3t.eu


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