4. MOS Amplifier Biasing & Discrete MOS Amplifiers
ECE 102, Fall 2012, F. Najmabadi
Sedra & Smith Sec. 5.7 & 5.8
(S&S 5th Ed: Sec. 4.7 & 4.9)
The major goal of “Bias” is to ensure that MOS is in saturation at all times
F. Najmabadi, ECE102, Fall 2012 (2/35)
Bias is the state of the system when there is no signal.
Bias point should be stable (i.e., resilient to variations in µnCox (W/L), Vt , … due to temperature and/or manufacturing variability.) o Important parameters are ID and VDS
In addition:
Bias point impacts the small-signal parameters.
Bias point impacts how large a signal can be amplified.
Bias point impact power consumption.
Bias with Gate Voltage
F. Najmabadi, ECE102, Fall 2012 (3/35)
This method is NOT desirable as µnCox (W/L) and Vt are not “well-defined.” Bias point (i.e., ID and VDS) can change drastically due to temperature and/or manufacturing variability. o See Exercise 5.33 (S&S 5th Ed: Exercise 4.19) Changing Vt from 1 to 1.5 V
leads to 75% change in ID.
DDDDDS
tGSoxnD
RIVV
VVL
WCI
−=
−= 2)( 5.0 µ
Bias with Source Degeneration (Resistor Rs provides negative feedback)
F. Najmabadi, ECE102, Fall 2012 (4/35)
Negative Feedback:
o If ID ↑ (because µnCox ↑ or Vtn ↓ ) VGS ↓ ID ↓
o If ID ↓ (because µnCox ↓ or Vtn ↑ ) VGS ↑ ID ↑
ID Eq. GS KVL
GS KVL ID Eq.
Feedback is most effective if
2)( 5.0 tGSoxnD
DSGGS
VVL
WCI
IRVV
−=
−=
µ
SGDDSGGS
GSDS
RVIIRVVVIR
/ 0 ≈⇒=+−>>
Examples of Bias with Source Degeneration
F. Najmabadi, ECE102, Fall 2012 (5/35)
Basic Arrangement
DSGGS IRVV −=
) 00 :(KVL SSDSGSG VIRVR −++×=
Bias with one power supply
DSGGS IRVV −= DSSSGS IRVV −=
Bias with two power supply
F. Najmabadi, ECE102, Fall 2012 (6/35)
Example: Find Bias point for Vt = 1 V and µnCox (W/L) = 1.0 mA/V2 (Ignore channel-width modulation.
Voltage divider (IG = 0)
V 715)87/()7( =×+=GV
V 1 065
7)105.0(101
7 7 :KVL-GS
5.0
2
234
2
=→=−+
=××++
=++=+=
=
−
OVOVOV
OVOV
DStOV
DSGSG
OVoxnD
VVVVV
IRVVIRVV
VL
WCI µ
V 5 V 1015
15 :KVL-DS
=−==−=
+=
SDDS
DDD
DDD
VVVIRV
VIR
mA 5.0/ V 527
V 21
===−=−=
=+=
SSD
GSGS
OVGS
RVIVVV
VV
Impact of RS (prove it) if Vt = 1.5 V (50% change), ID = 0.455mA (9% change)
Biasing in ICs
F. Najmabadi, ECE102, Fall 2012 (7/35)
Resistors take too much space on the chip. So, source degeneration with RS is NOT implemented in ICs.
Recall that the goal of a good bias is to ensure ID and VDS would not change (e.g., due to temperature variation). One can force ID to be constant using a current source.
1) Current source forces: IID =
4) GSGSGS VVVV −=−=
3) VGS is set by 2)( 5.0 tGSoxnD VV
LWCI −= µ
2) DDDDD IRVV −=
5) SDDS VVV −=
Current Mirrors or Current Steering Circuits are used as current sources for biasing ICs
F. Najmabadi, ECE102, Fall 2012 (8/35)
Circuit works as long as Q1 is in
saturation:
Identical MOS: Same µCox and Vt
Qref is always in saturation since
OVOVrefOV
GSGSrefGS
trefGSrefGSrefDS
VVVVVV
VVVV
==
==
−>=
1 ,
1 ,
,,,
2
1 11
2
ref,
5.0
5.0
OVoxnD
OVoxnrefDref
VL
WCII
VL
WCII
==
==
µ
µ
( )( )refref LW
LWII
// 1 1 =
tGSOVDS VVVV −=>1
An implementation of a Current Mirror
F. Najmabadi, ECE102, Fall 2012 (9/35)
Current mirror:
Since I1 = constant regardless of voltage, this is a current source!
Note: Circuit works as long as Q1 is in saturation.
The above 2 equations uniquely set Qref Bias point (ID,ref and VGS,ref = VDS,ref)
Identical MOS: Same µCox and Vt
2tGS, )V(V )/(5.0
:KVL-DS
−==
+=+
−+=
refoxnrefDref
SSDDGSref
SSGSrefDD
LWCII
VVVRIVVRIV
µ
( )( )refref LW
LWII
// 1 1 =
Examples of Current Steering circuits
F. Najmabadi, ECE102, Fall 2012 (10/35)
Current steering circuit can bias several transistors A PMOS current mirror
( )( )refref LW
LWII
// 1 1 =
( )( )refref LW
LWII
// 2 2 =
( )( )refref LW
LWII
// 1 1 =
An implementation of current steering circuit to bias several transistors in an IC
F. Najmabadi, ECE102, Fall 2012 (11/35) Exercise: Compute I4/Iref
F. Najmabadi, ECE102, Fall 2012 (12/35)
Discrete MOS Amplifiers
We will use MOS Fundamental Amplifier Configurations and Elementary R Forms to find the response of discrete MOS amplifiers
First, a few observations.
Stable Bias circuits for discrete MOS amplifiers
F. Najmabadi, ECE102, Fall 2012 (13/35)
We will do analysis for this configuration
Two power supplies
DSSSGS IRVV −=
Will Discuss later
Identical signal circuit for 21 || GGG RRR =
One power supply
DSGGS IRVV −=
Drain Feedback
Signal is typically coupled to discrete amplifiers via coupling capacitors
F. Najmabadi, ECE102, Fall 2012 (14/35)
Capacitors are open circuits for Bias (DC)
We assume that the signal is at sufficiently high frequencies, such that “large” capacitors can be approximated as shorts (|Z| = 1/ωC is small) o A lower cut-off frequency for amplifier
These capacitors can be added at input, output, and between amplifier stages.
These capacitor can also be used to “by-pass” resistors needed for bias but not for signal.
Note: In general, one should NOT assume
that all capacitors are short. We will see the impact of various capacitors later when we discuss frequency response of amplifiers.
F. Najmabadi, ECE102, Fall 2012 (15/35)
Real Circuit Test book uses current source for biasing (not a practical discrete circuit)
The analysis method introduced here, however, apply to any discrete bias case.
The best way to identify the type of amplifier is to follow the signal
F. Najmabadi, ECE102, Fall 2012 (16/35)
Common Source with RS
Common Drain/Source Follower
Common Source
Common Gate Input at the GATE
Output at the DRAIN Input at the SOURCE Output at the DRAIN
Input at the GATE Output at the DRAIN
Input at the GATE Output at the SOURCE
Analysis Steps
Note: We should solve the complete circuit (i.e., include vsig, Rsig , RL in our analysis).
Compute Bias point. o All capacitors are open circuits
o Compute gm and ro
Draw signal circuit (with MOS intact). o Low-frequency Caps are short, high-frequency Caps are open (high-
frequency caps discussed later)
Indentify fundamental amplifier configuration and compute proper amplifier gain (vo/vi) and the circuit gain (vo/vsig)
Use elementary R forms to find Ri and Ro o In general Ri will depend on RL and Ro depends on Rsig
F. Najmabadi, ECE102, Fall 2012 (17/35)
Discrete Common-source Amplifier
F. Najmabadi, ECE102, Fall 2012 (18/35)
This is a common-source amplifier (input at the gate and output at the drain).
Bias calculations are NOT done here as we have done that before.
Note (this is true for ALL circuits) sigi
i
sig
i
RRR
vv
+=
Derivation of small-signal circuit for Discrete CS Amplifier
F. Najmabadi, ECE102, Fall 2012 (19/35)
Real Circuit
Rearrange
Short caps Zero bias supplies
Signal Circuit
Discrete CS Amplifier – Gain
F. Najmabadi, ECE102, Fall 2012 (20/35)
i
o
sigi
i
sig
o
LDomi
o
vv
RRR
vv
RRrgvv
×+
=
−=
)||||(
Fundamental CS form
LDL RRR ||=′
Signal input at the gate Signal output at the drain No RS
Discrete CS Amplifier – Ri
F. Najmabadi, ECE102, Fall 2012 (21/35)
Gi RR =
∞= R
R
Replace transistor with its equivalent resistance Looking into the gate
Elementary R Configuration
∞= R
Discrete CS Amplifier – Ro
F. Najmabadi, ECE102, Fall 2012 (22/35)
|| oDo rRR =
orR =
R
Set vsig = 0 Replace transistor with its equivalent resistance Since ig = 0, Rsig and RG can be removed (vg = 0) Looking into the drain
Elementary R Configuration
orR =
Discrete CS Amplifier with RS
F. Najmabadi, ECE102, Fall 2012 (23/35)
Real Circuit
Signal Circuit
Short caps Zero bias supplies
Discrete CS Amplifier with RS – Gain
F. Najmabadi, ECE102, Fall 2012 (24/35)
i
o
sigi
i
sig
o
oLDSm
LDm
i
o
vv
RRR
vv
rRRRgRRg
vv
×+
=
++−=
/)||( 1
)||(
Fundamental CS form with RS
LDL RRR ||=′
Signal input at the gate Signal output at the drain RS !
Discrete CS Amplifier with RS – Ri
F. Najmabadi, ECE102, Fall 2012 (25/35)
Gi RR =
∞= R
R
Replace transistor with its equivalent resistance Looking into the gate
Elementary R Configuration
∞= R
Discrete CS Amplifier with RS – Ro
F. Najmabadi, ECE102, Fall 2012 (26/35)
[ ] )1( || SSmoDo RRgrRR ++=
R
R
Set vsig = 0 Replace transistor with its equivalent resistance Since ig = 0, Rsig and RG can be removed (vg = 0) Looking into the drain
Elementary R Configuration
SSmo RRgrR ++= )1(
SR=
SSmo RRgrR ++= )1(
Discrete CG Amplifier
F. Najmabadi, ECE102, Fall 2012 (27/35)
Real Circuit
Signal Circuit
Short caps Zero bias supplies
Discrete CG Amplifier – Gain
F. Najmabadi, ECE102, Fall 2012 (28/35)
Fundamental CG form
LDL RRR ||=′
Signal input at the source Signal output at the drain
i
o
sigi
i
sig
o
LDomi
o
vv
RRR
vv
RRrgvv
×+
=
+=
)||||(
Discrete CG Amplifier – Ri
F. Najmabadi, ECE102, Fall 2012 (29/35)
om
LDo
rgRRrR
++
=1
)||(
1
)||( ||
+
+=
om
LDoSi rg
RRrRR
R
Replace transistor with its equivalent resistance Looking into the source
Elementary R Configuration
LD RR ||=
om
LDo
rgRRrR
++
=1
)||(
Discrete CG Amplifier – Ro
F. Najmabadi, ECE102, Fall 2012 (30/35)
{ }sigSsigSmoDo RRRRgrRR ||)]||(1[ || ++=
R
R
Set vsig = 0 Replace transistor with its equivalent resistance Looking into the drain
Elementary R Configuration
sigSsigSmo RRRRgrR ||)]||(1[ ++=
sigS RR ||=
sigSsigSmo RRRRgr ||)]||(1[ ++
Discrete CD Amplifier (Source Follower)
F. Najmabadi, ECE102, Fall 2012 (31/35)
Signal Circuit
Short caps Zero bias supplies
Real Circuit
Discrete CG Amplifier – Gain
F. Najmabadi, ECE102, Fall 2012 (32/35)
Fundamental CS form
Signal input at the gate Signal output at the source
i
o
sigi
i
sig
o
LSom
LSom
i
o
vv
RRR
vv
RRrgRRrg
vv
×+
=
+=
)||||(1
)||||(
LSL RRR ||=′
Discrete CG Amplifier – Ri
F. Najmabadi, ECE102, Fall 2012 (33/35)
Replace transistor with its equivalent resistance Looking into the gate
R
Elementary R Configuration
∞= R
Gi RR =
∞= R
Discrete CG Amplifier – Ro
F. Najmabadi, ECE102, Fall 2012 (34/35)
1 || m
So gRR =
R
Elementary R Configuration
Set vsig = 0 Replace transistor with its equivalent resistance Since ig = 0, Rsig and RG can be removed (vg = 0) Looking into the source
Rm
om g
rg
1||1≈