39
4. Tunneling FETs Dmitri Nikonov Thanks to Uygar Avci [email protected] Beyond CMOS computing Nikonov 4. TFET 1
4. Tunneling FETs
Dmitri Nikonov
Thanks to Uygar Avci
Beyond CMOS computing
Nikonov 4. TFET 1
Outline
Band-to-band tunneling
Tunneling FET operation principles
Experimental realizations
Atomistic simulations
Homojunction TFET
Heterojunction TFET
Nikonov 4. TFET 2
Motivation • Need lower VDD to lower Switching Energy (~C.VDD
2) • When CMOS supply voltage is scaled <0.5V, performance suffers significantly
• TFET offers sharper turn-on devices compared to MOSFET
Better performance for ultra low-power applications
8x
For the same low switching energy and leakage power, TFET outperforms CMOS
Atomistic Model Prediction
Lg=20nm
InAs TFET
(VLSI 2011)
TFET
Switching
Energy0.3 fJ
Leakage
Power0.5 nW
Low-power MOSFET
Nikonov 4. TFET 3
Vd N i N
Vg Gate
Source Drain Subthreshold slope in MOSFETs is limited by the tail
of the Fermi distribution
To the thermodynamic limit value
Typically 80-120mV/dec at low current – depends on electrostatic control.
4
~ 1 / Subthreshold
Slope (mV/dec)
1
exp 1 expeV eV
fkT kT
1log( )
60 /g
d I eSS mV decade
dV kT
MOSFET
Nikonov 4. TFET 4
Vd P+ i-InAs N
Vg Gate
Source Drain
Tunneling
barriers Courtsey M. Luisier (Purdue)
M. Luisier and G. Klimeck, EDL, 2009
Tunnel FETs operate by tunneling through the S/D
barrier rather than diffusion over the barrier
Two required conditions:
• Thin enough barrier over a large enough area for effective (high current)
tunneling.
• Sufficient density of states on both the transmission and receiving sides to provide energetic
locations for the carriers.
5
Tunneling Field-Effect Transistor
Nikonov 4. TFET 5
2 22
Fmk
N
Bands parabolic close to edge = effective mass approximation
a=0.3nm m=mass ~ 0.2me=0.2*9.1*10-31kg kF=Fermi momentum~3/nm N=4*1046/(J*m3)=0.07/(eV*atom)
max 3 2
2mN
a
26
wE
ma
width of band: narrow band heavy mass
Fermi level
kF
density of states: it is larger for a heavy mass
* per 1 spin state Cartoon of density of States
Nikonov 4. TFET 6
Probability of tunneling http://en.wikipedia.org/wiki/Quantum_tunneling
2 2exp
b bw m U
T
w=width=1nm mb=mass= 0.2* 9.1*10-31kg Ub=height=0.8eV T~0.016
Tunneling current density http://arxiv.org/abs/0711.1461
22 42b l r
e VJ TU N N a
A~0.3m N= 4*1046 /(J*m3) J/V=1.2*1014 S/m2
2/ 0.5V J RA m
Heavier mass smaller tunneling probability
Quantum Tunneling
Nikonov 4. TFET 7
TFET Device and Operation
MOSFET-like structure, but with opposite type doping in Source and Drain
Can use different device geometries like MOSFET
TFET
MOSFET
Over the Barrier
Through the Barrier
Vg
Vg
Nikonov 4. TFET 8
Device Operation
S
D
S
S
D
S
D D
Nikonov 4. TFET 9
M. Luisier and G. Klimeck, IEEE EDL, 30, 602 (2009)
Device Operation
S
D
S
S
D
S
D D
Nikonov 4. TFET 10
M. Luisier and G. Klimeck, IEEE EDL, 30, 602 (2009)
Device Operation
S
D
S
S
D
S
D D
Nikonov 4. TFET 11
M. Luisier and G. Klimeck, IEEE EDL, 30, 602 (2009)
Device Operation
S
D
S
S
D
S
D D
Nikonov 4. TFET 12
M. Luisier and G. Klimeck, IEEE EDL, 30, 602 (2009)
Homojunction vs. Heterojunction
• Heterojunction can achieve higher tunneling current
Homojunction Heterojunction
Material- A Material- B
Nikonov 4. TFET 13
Si TFET (UC Berkeley)
• Show of highest possible current with Si with sub-60 mV/dec SS
– Best published Si or Ge TFET
– Shows high-angle to gate interface tunneling increases current
VLSI 2010
Nikonov 4. TFET 14
SiGe TFET (CEA-LETI)
• Show of high current with no sub-60 mV/dec SS
– Possibly not a TFET but metal contact to channel. No sub-60mV/dec expected.
VLSI 2012
Nikonov 4. TFET 15
Vertical III-V (Intel, Penn-State, Notre Dame)
• Intel: Showed sub-60mV/dec SS
• Penn-State: High-current capability of heterojunction TFET
• Notre Dame: High-current with tunneling perpendicular to gate interface
Penn-State (VLSI 2012) Intel (IEDM 2011) Notre Dame (EDL-2012)
Nikonov 4. TFET 16
Heterojunction InGaAs TFET. Side-gated. Better electrostatic control.
The only semiconductor TFET (there was one carbon-nanotube before) with <60mV/decade. Albeit at small Vds,
over a small Vg range.
G. Dewey et al., IEDM, 2011.
Intel TFET Demonstration !
Nikonov 4. TFET 17
Other Experimental TFET
• Stanford (2006): CNT – Good SS at very low current (pA)
• Stanford (2008): Strained-Ge Double-gate – Either high-current or good SS, not together
• Hitachi (2010): Novel TFET device idea (Si)
• Peking Uni. (2011): Novel TFET device idea (Si)
• Hokkaido Uni. (2012): InAs nanowire on Si he-j TFET – Very good SS ~21mV dec. with low Idsat
– No clear understanding of how this was achieved
Nikonov 4. TFET 18
• Still MUCH lower drive currents than
conventional MOS • Require band-gap
engineering with hetero-junction d layers
• Sub-threshold slope still poor
S. Mookerjea et al., IEDM ‘09 [1] K. Jeon, et al., VLSI (11.4.1.-1) 2010 [2] W. Choi et al., IEEE-EDL vol.28, no.8, p.743 (2007)
[3] F. Mayer et al., IEDM Tech Dig., p.163 (2008) [4] T. Krishnamohan et al., IEDM Tech Dig., p.947
(2008)
[1]
32nm MOS @ Vds = 0.8V
Most Experimental Still Poor Performance
Nikonov 4. TFET 19
TFET Modeling Approaches
For accurate prediction, quantum solution with band-structure calculation is chosen
Analytic modeling using Kane’s model
•Fast computation •Requires calibration to electrical data for reliable prediction.
•Suitable large geometries
Atomistic quantum modeling •Very slow computation •Requires input of tight-binding parameters for bandstructure calculation. •Suitable for small geometry
Used in this study
Nikonov 4. TFET 20
Atomistic Quantum Modeling
3D ballistic quantum transport and atomistic full-band tight-binding band structure calculation
No fitting to experimental electrical characteristics. The only input parameters are bandstructure of the material and geometry.
OMEN
Atomistic structure Density of states spectrum
Ec
Ev
E
x
Nikonov 4. TFET 21
TFET Sub-threshold Slope
Tunneling current increases sharply at the onset of Source
Valence Band and Channel Conduction Band overlap
E
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
0.0 0.1 0.2 0.3 0.4
ID (A
/um
)
VG (V)
VDS=0.4V
TFET
S
Ch
D
Nikonov 4. TFET 22
TFET Sub-threshold Slope
E
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
0.0 0.1 0.2 0.3 0.4
ID (A
/um
)
VG (V)
VDS=0.4V
TFET
S
Ch
Ch
D D
S
• Tunneling current increases sharply at the onset of Source
Valence Band and Channel Conduction Band overlap
Nikonov 4. TFET 23
Effect of Gate-length TFET subthreshold-slope improves significantly at longer gate-length for a 10nm-body with a single-gate
Lg=25 nm
50 nm 100nm
Single-gate 10nm body Vg (V)
Id (
uA/u
m)
Nikonov 4. TFET 24
Single-gate vs. Double-gate Increased gate-control continues to improve TFET characteristics, whereas MOSFET is limited by 60mV/dec
5nm body Lg=100nm For cnst. IOFF=1nA/um
DG TFET
SG TFET
2.5x
40 <20 mV/dec
SG or DG MOSFET ~60
Nikonov 4. TFET 25
Effect of Body thickness Thinner body has lower SS and higher drive
The effect is much less pronounced than SG/DG difference
Single-gate Lg=100nm For cnst. IOFF=1nA/um
tB=10 nm
20 nm
thinner
Nikonov 4. TFET 26
Effect of Device Geometry on Subthreshold-Slope
2x Lg
½ tB
SGDG Lg=50nm tB=10nm SG
Lg=100nm tB=10nm SG
Lg=100nm tB=5nm SG
Lg=100nm tB=5nm DG
Nikonov 4. TFET 27
InAs TFET Device Design
• Narrow bandgap (e.g. InAs) required for high ION
• Drain underlap to lower ambi-polar IOFF leakage
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
-0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5
ID (
uA
/um
)
VG (V)
ITRS Low Power CMOS
TFET- S/D Symmetric
TFET with Drain underlap
LG = 20 nm tBody = 5 nm tOx(SiO2) = 1 nm NSource = 5e19 cm-3
NDrain = 5e18 cm-3
VDS=0.5V
Nikonov 4. TFET 28
Transistor Characteristics - II TFET has better Rout in the saturation region (high VDS)
TFET has higher saturation voltage (VDSAT-EFF)
0
5
10
15
20
25
30
0.0 0.1 0.2 0.3
ID (u
A/u
m)
VDS (V)
0
5
10
15
20
25
30
0.0 0.1 0.2 0.3VDS (V)
IOFF =1nA/μm
VGS =0.35V
0.3V
0.25V
0.2V
0.35V
0.3V
0.25V 0.2V
TFET MOSFET (ITRS)
VDSAT-EFF
VDSAT-EFF
Nikonov 4. TFET 29
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
-0.1 0.0 0.1 0.2 0.3 0.4 0.5
ID (u
A/u
m)
VG (V)
Transistor Characteristics
• Subthreshold Slope (SS): 34-45 mV/dec
• Strong IOFF dependence on VDS
0.5V
0.1V 0.2V
0.3V 0.4V VDS
TFET
Nikonov 4. TFET 30
11
HTFET Material Considerations
Lattice matched to InP Metamorphic Growth on InP or GaAs
Staggered and broken gap systems have higher tunneling probability.
Theresa Mayer and Suman Datta, Penn State, SRC review 2011
31 Nikonov 4. TFET
InAs TFET, on current
Nikonov, Avci, Rios, Kuhn
Nikonov 4. TFET 32
InAs/GaSb TFET, on current
Nikonov, Avci, Rios, Kuhn
Nikonov 4. TFET 33
Both simulations and experimental data show significant improvement for heterojunction channel design over homojunction
Lg=15nm Simulation
Lg=100nm Experimental
Homojunc.
Heterojunc.
Homojunc.
Heterojunc.
(Dewey, IEDM’11)
(Avci, VLSI Tech ‘12)
Nikonov 4. TFET 34
Heterojunction TFET
1.E-05
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
-0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0
Id (u
A/u
m)
VG (V)
P1272 MOS
5nm Homo-jnc
2.5nm Hetero-jnc
T-FET ION/IOFF characteristic was improved for both N-type and P-type with:
• Thinner channel
• Changing device material from InAs homo-junction to a GaSb/InAs hetero-junction.
• P-TFET sub-threshold slope has MOS-like thermal behavior ~60mV/dec, due to low density of sates (DOS) in the conduction band.
1.E-05
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Id (u
A/u
m)
VG (V)
P1272 MOS
5nm Homo-jnc
2.5nm Hetero-jnc
N-type P-type
~60 mV/dec
30-45 mV/dec VDS = 0.5V
IOFF = 10pA/um
InAs/GaSb Heterojunction TFET
Nikonov 4. TFET 35
TFET Capacitance
Increased TFET CGD capacitance quoted in literature, due to the
choice of TFET material (Si or Ge). But lower capacitance at
smaller voltages – beneficial for delay.
Y. Yang et. al. (EDL 2010)
EF EF
S Channel D
TFET
Filled states
Nikonov 4. TFET 36
III-V N-TFET Capacitance
III-V Conduction Band has low density of states resulting in low
N-TFET Cgate and CGD
DOS
LOW
HIGH
E
x (nm)
1E+16
1E+17
1E+18
1E+19
1E+20
Si
Ge
InG
aAs
InA
s
InSb
Eff.
De
nsi
ty o
f Sta
tes
(1/c
m3
) ValanceBand
ConductionBand
EF
EF
Nikonov 4. TFET 37
Challenges
• Poor experimental drive currents • Ambipolar conduction
(high DB leakage for bulk devices) • No comparable PTFET
• Asymmetric device behavior (issues in SRAM)
• Most attractive at very low operating voltages (where product frequencies
may be not so interesting)
Benefits
• Steep sub-threshold slope (< 60 mV/dec)
• Large Ion/Ioff ratio • Geometry scales well
• Some designs are compatible with conventional SiGe/Si CMOS
processes
Vd P+ i-InAs N
Vg Gate
Source Drain
Tunneling
barriers Courtsey M. Luisier (Purdue)
M. Luisier and G. Klimeck, EDL, 2009
TFET Summary
Nikonov 4. TFET 38
Summary
Band-to-band tunneling underpins TFET
Gate voltage changes tunneling in a TFET
Most experimental devices are still far from ideal (Intel stands out)
Atomistic simulations with NEGF method
Homojunction TFET = lower on-current
Heterojunction TFET = higher on-current
Nikonov 4. TFET 39
