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LOW POWER VLSI

By,K.Nagendra

06S11A0421

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Why worry about power?

--Heat DissipationMicroprocessor power Consumption

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Why we go to Low Power..

PORTABILITY:

Enhanced run-time, Reduced weight, Reduced

volume, Low cost operation

High Performance:

Low-cost cooling, Low-cost packaging, Low-cost

operation

RELIABILITY: Avoid thermal problems

 Avoid scaling related problems

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Speed/Power performance for 

available Technologies

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Where Does Power Go In CMOS

Dynamic Power Consumption :

Charging and Discharging Capacitors

Short Circuit Currents :

Short circuit path between supply rails during

switching

Leakage:

Leakage diodes and transistorsPtotal = PDYN + PSC + PLeakage

=CLVDDF+VDDIPEAK{(Tr + Tf )/2}F+VDD ILEAK

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Dynamic Power Consumption

Energy/transition = CL

* Vdd

2

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Dynamic Power Consumption

Power = Energy / Transition * transition rate

=

So, power is proportional to Vdd , f ,CL

Power dissipation is data dependentFunction of switching activity

CL* Vdd

2* f 

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Reducing Vdd

Power P is proportional to square of V

VDD has decreased in modern processes

 ± High VDD would damage modern tiny transistors

 ± Lower VDD saves power  VDD = 5, 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, «

Further decreasing may cause affect to Threshold

voltage

Relatively independent of logic function and style.

Power Delay Product Improves with lowering Vdd.

By reducing Vdd Noise margin will be affected

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Noise Margin

NML = VIL - VOL

NMH = VOH - VIH

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Power Consumption is Data

Dependent A B Y

0 0 1

0 1 0

1 0 0

1 1 0

Ex: Static 2 i/p NOR Gate

P(A=1) = ½

P(B=1) = ½

Then

P(out=1) = ¼

P(out=0) = 1-P(out=1)

=1-1/4 = ¾

P(0->1) =P(out=1).P(out=0)

= ¾ * ¼ = 3/16

 A

BY

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Transition Probability of 2-input

NOR Gate

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Transition Probabilities for Basic

Gates

Switching Activity for Static CMOS

P0 -> 1

= P0

* P1

P0 -> 1

 AND(1-Pa * Pb) Pa Pb

OR (1-Pa)(1-Pb)(1-(1-Pa)(1-Pb))

EXOR (1-(Pa + Pb - 2Pa * Pb)) (Pa + Pb -

2Pa * Pb)

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How about Dynamic Circuits..?

Power is only

dissipated when

out=0

Ceff = P(out=0) * CL

In1

In2 PDN

In3

Me

Mp

Clk

Clk

Out

CL

Two phase operation

Precharge (CLK = 0)

Evaluate (CLK = 1)

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2 input NOR gate

 A B Y

0 0 1

0 1 0

1 0 0

1 1 0

P(A=1) = ½

P(B=1) = ½

P(out=0) = ¾

Ceff = ¾ * CL

Switching activity is

always Higher inDynamic Circuits

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Transition Probabilities For 

Dynamic GATES

Switching Activity for Precharged Dynamic

Gates

P0 -> 1

 AND(1-Pa * Pb)

OR (1-Pa)(1-Pb)

EXOR (1-(Pa

+ Pb

- 2Pa

* Pb

))

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Glitching«

Glitching refers to spurious and unwantedtransitions that occur before a node settledown to its final steady-state value.

Glitching often arises when paths withunbalanced propagation delay convergesat the same point in the circuit.

The dissipation caused by the spurioustransitions can reach up to 25% of the totaldissipation for some circuits.

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Glitching in Static CMOS

Each gate hasUnit delay

Input A, B, Carrive at sametime.

No glitching indynamic circuits

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How to Cope With Glitching..?

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Short Circuit Currents

Short circuit currents are encountered only

in static design.

In static CMOS circuits the flow currentfrom VDD to GND during Switching when

both NMOS and PMOS conducting

Simultaneously.

Such path never exists in a dynamic

circuits.

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Short Circuit Currents

V out 

V in0.5 1 1.5 2 2.5

        0  .

        5

        1

        1  .        5

        2

        2  .

        5

 NMOS res

PMOS off 

 NMOS sat

PMOS sat

 NMOS off 

PMOS res

 NMOS sat

PMOS res

 NMOS res

PMOS sat

Vin Vout

CL

Vdd

       I       V       D

       D

       (     m

       A       )

0.15

0.10

0.05

V in (V )5. 04. 03. 02. 01. 00. 0

Vin Vout

CL

Vdd

       I       V       D

       D

       (     m

       A       )

0.15

0.10

0.05

V in (V )5. 04. 03. 02. 01. 00. 0

Vin Vout

CL

Vdd

       I       V       D

       D

       (     m

       A       )

0.15

0.10

0.05

V in (V )5. 04. 03. 02. 01. 00. 0

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Impact of rise/fall time on Short-

Circuit Currents

Large Capacitive Load

The input through the

transient region before the

output start to change

Small capacitive Load

Output fall time is

Substantially smaller than

the input rise time

V in V out 

C L

V DD

V in V out 

C L

V DD

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Short-Circuit energy as a function

of slope ratio

Short-Circuit energy dissipation (normalized with

respect to zero i/p rise time energy) for a static

CMOS. The power dissipation due to short circuit

currents is minimized by matching the rise/fall

times of the input and output signals.

Short-Circuit reduced by lower the SupplyVoltage.

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Leakage

Sub-Threshold current Dominant factor 

Vo u t

V d d

S u b - T h r e s h o l d

C u r r e n t

D r a i n J u n c t i o nL e a k a g e

S u b - T h r e s h o l d C u r r e n t D o m i n a n t F a c t o r  

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System-Level optimization : Power 

Management

In event-driven application, large amounts of power are wasted while the system is in idle-mode.

The power consumption can be reducedsignificantly by using power managementscheme to shunt down idle component.

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Conclusion

Thus the low power can be achieved bydecreasing Vdd to certain level.

As leakage current cannot be reduced, the short

circuit currents are eliminated by dynamiccircuits.

The power dissipation due to short circuitcurrents is minimized by matching the rise/fall

times of the input and output signals Glitching makes power to dissipate so it is

reduced by cope process

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References

Digital Integrated Circuits ±JAN M.RABAEY

Encyclopedia of computer science and

technology,1995.

VLSI Design Techniques for Analog and Digital

Circuits ±Randall L.Geiger, Phillip E.Allen.

Basic VLSI Design A.PUCKNELL.

Low-Power CMOS Design ³IEEE journal of solidstate circuit -pages 472-484,Aprill 1992´.

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THANK 

µU¶