23194127 Cmos Vlsi Design

8/8/2019 23194127 Cmos Vlsi Design

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CMOS VLSIDigital Design Slide 1

CMOS VLSI Design

Digital Design


2/71


Overview

Physical principles

Combinational logic

Sequential logic

Datapath Memories

Trends


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Dopants

Silicon is a semiconductor

Pure silicon has no free carriers and conducts poorly

Adding dopants increases the conductivity

Group V: extra electron (n-type) Group III: missing electron, called hole (p-type)

As SiSi

Si SiSi

Si SiSi

B SiSi

Si SiSi

Si SiSi

-

+

+

-


4/71


nMOS Operation

Body is commonly tied to ground (0 V)

When the gate is at a low voltage:

P-type body is at low voltage

Source-body and drain-body diodes are OFF No current flows, transistor is OFF

n

p

GateSource Drain

bulk Si

SiO2

Polysilicon

nD

0

S


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Transistors as Switches

We can view MOS transistors as electricallycontrolled switches

Voltage at gate controls path from source to drain

g

s

d

g = 0

s

d

g = 1

s

d

g

s

d

s

d

s

d

nMOS

pMOS

OFFON

ONOFF


6/71


CMOS Inverter

A Y

0

1

A Y

NDA Y


7/71


Inverter Cross-section

Typically use p-type substrate for nMOS transistors

Requires n-well for body of pMOS transistors

n

p substrate

p

n well

A

YGND VDD

n p

SiO2

n diffusion

p diffusion

polysilicon

metal1

nMOS transistor pMOS transistor


8/71


Inverter Mask Set

Transistors and wires are defined bymasks

Cross-section taken along dashed line

GND VDD

Y

s strate ta ell tanM transistor M transistor


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Fabrication Steps

Start with blank wafer

Build inverter from the bottom up

First step will be to form the n-well

Cover wafer with protective layer of SiO2 (oxide) Remove layer where n-well should be built

Implant or diffuse n dopants into exposed wafer

Strip off SiO2

p substrate


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Oxidation

Grow SiO2 on top of Si wafer

900 1200 C with H2O or O2 in oxidation furnace

p substrate

SiO2


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Photoresist

Spin on photoresist

Photoresist is a light-sensitive organic polymer

Softens where exposed to light

p substrate

SiO2

Photoresist


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Lithography

Expose photoresist through n-well mask

Strip off exposed photoresist

p substrate

SiO2

Photoresist


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Etch

Etch oxide withhydrofluoric acid (HF)

Seeps through skin and eats bone; nasty stuff!!!

Only attacks oxide where resist has been exposed

p substrate

SiO2

Photoresist


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Strip Photoresist

Strip off remaining photoresist

Use mixture of acids called piranah etch

Necessary so resist doesnt melt in next step

p substrate

SiO2


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n-well

n-well is formed with diffusion or ion implantation

Diffusion

Place wafer in furnace with arsenic gas

Heat until As atoms diffuse into exposed Si Ion Implanatation

Blast wafer with beam ofAs ions

Ions blocked by SiO2, only enter exposed Si

n well

SiO2


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Simplified Design Rules

Conservative rules to get you started


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Complementary CMOS

Complementary CMOS logic gates

nMOSpull-down network

pMOSpull-up network

a.k.a. static CMOS

pMOSpull-upnetwork

output

inputs

nMOSpull-downnetwork

Pull-up OFF Pull-up ON

Pull-down OFF Z (float) 1

Pull-down ON 0 X (crowbar)


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Example: NAND3

Horizontal N-diffusion and p-diffusion strips

Vertical polysilicon gates

Metal1 VDD rail at top

Metal1 GND rail at bottom 32 P by 40 P


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I-V Characteristics

In Linear region, Ids depends on

How much charge is in the channel?

How fast is the charge moving?


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Channel Charge

MOS structure looks like parallel plate capacitorwhile operating in inversion

Gate oxide channel

Qchannel = CV C = Cg = IoxWL/tox = CoxWL

V = Vgc Vt = (Vgs Vds/2) Vt

+ +

-ty dy

+

Vgd

g t

+ +

s rc

-

Vgs-

dr i

Vds

ch l-

Vg

Vs Vd

g

+ +

-ty dy

W

L

t x

SiO2 g t xid(g d i s l t r, Iox = 3.9)

polysilicongate

Cox = Iox / tox


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Carrier velocity

Charge is carried by e-

Carrier velocityvproportional to lateral E-fieldbetween source and drain

v= QE Q called mobility

E = Vds/L

Time for carrier to cross channel:

t= L / v


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nMOS Linear I-V

Now we know

How much charge Qchannel is in the channel

How much time teach carrier takes to cross

channel

ox 2

2

ds

ds gs t ds

ds gs t ds

QIt

W VC V V V

L

VV V V

Q

F

!

!

!

ox=W

F


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Example

Example: a 0.6 Qm process from AMI semiconductor

tox = 100

Q = 350 cm2/V*s

Vt = 0.7 V Plot Ids vs. Vds

Vgs = 0, 1, 2, 3, 4, 5

Use W/L = 4/2 P

14

2

8

3.9 8.85 10350 120 /

100 10ox

W W WC A V

L L L F Q Q

y ! ! !

0 1 2 3 4 50

0 .5

1

1 .5

2

2 .5

Vds

Ids

(mA)

Vgs = 5

Vgs = 4

Vgs = 3

Vgs

= 2

Vgs = 1


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Capacitance

Any two conductors separated by an insulatorhavecapacitance

Gate to channel capacitor is very important

Creates channel charge necessary for operation Source and drain have capacitance to body

Across reverse-biased diodes

Called diffusion capacitance because it is

associated with source/drain diffusion


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Gate Capacitance

Approximate channel as connected to source

Cgs = IoxWL/tox = CoxWL = CpermicronW

Cpermicron is typically about 2 fF/Qm

+ +

-ty y

ti t i

( i s l t r, I . I )

lysilict


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Diffusion Capacitance

Csb, Cdb Undesirable, calledparasiticcapacitance

Capacitance depends on area and perimeter

Use small diffusion nodes Comparable to Cg

for contacted diff

C g for uncontacted

Varies with process


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RC Delay Model

Use equivalent circuits forMOS transistors

Ideal switch capacitance and ON resistance

Unit nMOS has resistance R, capacitance C

Unit pMOS has resistance 2R, capacitance C Capacitance proportional to width

Resistance inversely proportional to width

kg

s

d

g

s

d

kCkC

kC

R/k

kg

s

d

g

s

d

kC

kC

kC

2R/k


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Introduction

Chips are mostly made of wires called interconnect

In stick diagram, wires set size

Transistors are little things under the wires

Many layers of wires Wires are as important as transistors

Speed

Power

Noise Alternating layers run orthogonally


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Wire Capacitance

Wire has capacitance per unit length

To neighbors

To layers above and below

Ctotal = Ctop Cbot 2Cadj

layer n

layer n

layer n-

Cadj

Ctop

Cbot

ws

t

h1

h2


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Lumped Element Models

Wires are a distributed system Approximate with lumped element models

3-segment T-model is accurate to 3% in simulation L-model needs 100 segments for same accuracy! Use single segment T-model forElmore delay

C

R

C/N

R/N

C/N

R/N

C/N

R/N

C/N

R/N

R

C

L-model

R

C/2 C/2

R/2 R/2

C

N segments

T-model T-model


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Crosstalk

A capacitor does not like to change its voltageinstantaneously.

A wire has high capacitance to its neighbor.

When the neighbor switches from 1-> 0 or 0->1,the wire tends to switch too.

Called capacitive couplingorcrosstalk.

Crosstalk effects

Noise on nonswitching wires Increased delay on switching wires


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Coupling Waveforms

Aggressor

Victim (undriven): 50%

Victim (half size driver): 16%

Victim (equal size driver): 8%

Victim (double size driver): 4%

t(ps)

0 200 400 600 800 1000 1200 1400 1800 2000

0

0.3

0.6

0.9

1.2

1.5

1.8

Simulated coupling forCadj =Cvictim


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Introduction

What makes a circuit fast?

I = C dV/dt -> tpd w (C/I) (V

low capacitance

high current small swing

Logical effort is proportional to C/I

pMOS are the enemy!

High capacitance for a given current Can we take the pMOS capacitance off the input?

Various circuit families try to do this

B

A

11

4

4

Y


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Pseudo-nMOS

In the old days, nMOS processes had no pMOS

Instead, use pull-up transistor that is always ON

In CMOS, use a pMOS that is always ON

Ratio issue Make pMOS about effective strength of

pulldown network

Vout

Vin

16/2

P/2

Ids

load

.

.6

.

1.2 1.

1.8

.

.6

.

1.2

1.

1.8

P

24

P 4

P

14

Vin

Vout


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Dynamic Logic

Dynamicgates uses a clocked pMOS pullup

Two modes:precharge and evaluate

1

2A Y4/

2/A

Y1

1

AYJ

St tic Ps - M S Dy ic

J Pr charg Eval at

Y

Pr charg


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Pass Transistor Circuits

Use pass transistors like switches to do logic

Inputs drive diffusion terminals as well as gates

CMOS Transmission Gates: 2-input multiplexer

Gates should be restoring

A

B

S

S

S

Y

A

B

S

S

S

Y


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Sequencing

Combinational logic

output depends on current inputs

Sequential logic

output depends on current and previous inputs Requires separating previous, current, future

Called state ortokens

Ex: FSM, pipeline

CL

clk

in out

clk clk clk

CL CL

PipelineFinite State Machine


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Sequencing Overhead

Use flip-flops to delay fast tokens so they movethrough exactly one stage each cycle.

Inevitably adds some delay to the slow tokens

Makes circuit slower than just the logic delay Called sequencing overhead

Some people call this clocking overhead

But it applies to asynchronous circuits too

Inevitable side effect of maintaining sequence


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Sequencing Elements

Latch: Level sensitive

a.k.a. transparent latch, D latch

Flip-flop: edge triggered

A.k.a. master-slave flip-flop, D flip-flop, D register Timing Diagrams

Transparent

Opaque

Edge-trigger

D

l

p

atch

clk clk

D

clk

D

(latch)

(fl p)


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Latch Design

Buffered output

No backdriving

Widely used in standard cells

Very robust (most important)

- Rather large

- Rather slow (1.5 2 FO4 delays)- High clock loading

J

J

Q

DX

J

J


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Sequencing Methods

Flip-flops

2-Phase Latches

Pulsed Latches

Flip-Flops

Flop

Latch

Flop

clk

J1

J2

Jp

clk clk

atch

atch

Jp

Jp

J1

J1

J2

2

-Phas

Transpar

nt

atch

s

P

ls

atch

s

inati nal ! ic

inati

nal

! ic

inati

nal ! ic

inati

nal

!ic

atch

atch

Tc

Tc/2

tnonov

" rlapt

nonov" rlap

tpw

Half-

ycl#1 Half-

ycl

#1


42/71


Summary

Flip-Flops:

Very easy to use, supported by all tools

2-Phase Transparent Latches:

Lots of skew tolerance and time borrowing Pulsed Latches:

Fast, some skew tol & borrow, hold time risk


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Full Adder Design I

Brute force implementation from eqns

out ( , , )

S A B C

C MAJ A B C

!

!

ABC

S

Cout

MAJ

ABC

A

B BB

A

C SC

CC

B BB

A A

A B

C

B

A

CBA A B C

CoutC

A

A

BB


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Carry-Skip Adder

Carry-ripple is slow through all N stages

Carry-skip allows carry to skip over groups of n bits

Decision based on n-bit propagate signal

Cin

S4:1

P4:1

A4:1 B4:1

S $ :5

P8:5

A8:5 B8:5

S12:9

P12:9

A12:9 B12:9

S16:13

P16:13

A16:13 B16:13

CoutC4 1

0

C8

1

0

C12 1

0

1

0


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Tree Adder

If lookahead is good, lookahead across lookahead!

Recursive lookahead gives O(log N) delay

Many variations on tree adders


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Memory Arrays

MemoryArrays

Random Access Memory Serial Access Memory Content Addressable Memory(CAM)

Read/Write Memory

(RAM)(Volatile)

Read OnlyMemory

(ROM)(Nonvolatile)

Static RAM(SRAM)

Dynamic RAM(DRAM)

Shift Registers Queues

First InFirst Out(FIFO)

Last InFirst Out(LIFO)

Serial InParallel Out

(SIPO)

Parallel InSerial Out

(PISO)

Mask ROM ProgrammableROM

(PROM)

ErasableProgrammable

ROM(EPROM)

ElectricallyErasable

ProgrammableROM

(EEPROM)

Flash ROM


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Array Architecture

2n words of 2m bits each

If n >> m, fold by 2k into fewerrows of more columns

Good regularity easy to design

Veryhigh density if good cells are used

row

decoder

column

decoder

n

n-kk

2m bits

columncircuitry

bitline conditioning

memory cells:2n-k rows x2m % k columns

bitlines

wordlines


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6T SRAM Cell

Cell size accounts for most of array size Reduce cell size at expense of complexity

6T SRAM Cell Used in most commercial chips

Data stored in cross-coupled inverters Read:

Precharge bit, bit_b Raise wordline

Write: Drive data onto bit, bit_b Raise wordline

bit bit_b

word


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SRAM Sizing

High bitlines must not overpower inverters duringreads

But low bitlines must write new value into cell

bit bit b

med

A

weak

strong

med

A b

word


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Decoders

n:2n decoder consists of 2n n-input AND gates

One needed for each row of memory

Build AND from NAND or NOR gates

Static CMOS Pseudo-nMOS

word0

word1

word2

word3

A0A1

A1

word

A01 1

1/2

2

4

8

1&

word

A0

A1

1

1

11

4

8word0

word1

word2

word3

A0A1


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Decoder Layout

Decoders must be pitch-matched to SRAM cell

Requires very skinny gates

GND

VDD

word

buffer inverterNAND gate

A0A0A1A2A3 A2A3 A1


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Sense Amplifiers

Bitlines have many cells attached

Ex: 32-kbit SRAMhas 256 rows x 128 cols

128 cells on each bitline

tpdw

(C/I)(

V Even with shared diffusion contacts, 64C ofdiffusion capacitance (big C)

Discharged slowly through small transistors(small I)

Sense amplifiers are triggered on small voltageswing (reduce (V)


53/71


Queues

Queues allow data to be read and written at differentrates.

Read and write each use their own clock, data

Queue indicates whether it is full or empty

Build with SRAM and read/write counters (pointers)

Queue

rite lk

riteData

Read lk

ReadData

EMPTY


54/71


CAMs

Extension of ordinary memory (e.g. SRAM)

Read and write memory as usual

Also match to see which words contain a key

AM

adr data/key

atch

read

write


55/71


10T CAM Cell

Add four match transistors to 6T SRAM

56 x 43 P unit cell

bit bit_b

word

match

cell

cell_b


56/71


CAM Cell Operation

Read and write like ordinary SRAM

For matching:

Leave wordline low

Precharge matchlines Place key on bitlines

Matchlines evaluate

Miss line

Pseudo-nMOS NOR of match lines Goes high if no words match

row

decoder

weak

missmatch0

match1

match2

match3

clk

column circuitry

CAM cell

address

data

read/write


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ROM Example

4-word x 6-bit ROM

Represented with dot diagram

Dots indicate 1s in ROM

Word 0: 010101

Word 1: 011001

Word 2: 100101

Word 3: 101010

ROMArray

2:4DEC

A0A1

Y0Y1Y2Y3Y4Y5

weakpseudo-nMOS

pullups

Looks like 6 4-input pseudo-nMOS NORs


58/71


PLAs

AProgrammable LogicArrayperforms any functionin sum-of-products form.

Literals: inputs & complements

Products / Minterms: AND of literals

Outputs: OR ofMinterms

Example: Full Adder

out

s abc abc abc abc

c ab bc ac

!

!

AND Plane OR Plane

abc

abc

abc

abc

ab

bc

ac

sa b cout

c

Minter

'

s

Inputs Outputs


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PLA Schematic & Layout

AND Plane OR Plane

abc

abc

abc

abc

ab

bc

ac

s

a b c

outc


60/71


Ideal nMOS I-V Plot

180 nm TSMC process

Ideal Models

F = 155(W/L) QA/V2

Vt = 0.4 V

VDD = 1.8 V

Ids (QA)

Vds0 0.3 0.6 0.9 1.2 1.5 1.8

100

200

300

400

Vgs = 0.6Vgs = 0.9

Vgs = 1.2

Vgs = 1.5

Vgs = 1.8

0


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Simulated nMOS I-V Plot

180 nm TSMC process

BSIM 3v3 SPICE models

What differs?

Less ON current No square law

Current increases

in saturation

Vds

0 0.3 0. 0. 1.2 1.

Vgs 1.8

Ids (QA)

0

50

100

150

200

250

Vgs

1.5

Vgs 1.2

Vgs 0.

Vgs 0.


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Velocity Saturation

We assumed carrier velocity is proportional to E-field

v= QElat = QVds/L

At high fields, this ceases to be true

Carriers scatter off atoms Velocity reaches vsat Electrons: 6-10 x 106 cm/s

Holes: 4-8 x 106 cm/s

Better modelEsat0

0

slope Q

Elat

R

2Esat 3Esat

Rsat

Rsat / 2

latsat sat

lat

sat

1

Ev v E

E

E

! !


63/71


Channel Length Modulation

Reverse-biased p-n junctions form a depletion region

Region between n and p with no carriers

Width of depletion Ld region grows with reverse bias

Leff= L Ld Shorter Leffgives more current

Ids increases with Vds Even in saturation

n+

p

GateSource Drain

ulk Si

n+

VDDGND VDD

GND

LLeff

Depletion Regionidth: Ld


64/71


Body Effect

Vt: gate voltage necessary to invert channel

Increases if source voltage increases becausesource is connected to the channel

Increase in Vt

with Vs

is called the bodyeffect


65/71


OFFTransistorBehavior

What about current in cutoff?

Simulated results

What differs?

Current doesnt goto 0 in cutoff

Vt

Sub-threshold

Slope

Sub-threshold

Region

SaturationRegion

Vds 1.8

Ids

Vgs

0 0.3 0. 0. 1.2 1.5 1.8

10 pA

100 pA

1 nA

10 nA

100 nA

1QA

10QA

100QA

1 A


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Leakage Sources

Subthreshold conduction

Transistors cant abruptly turn ON or OFF

Junction leakage

Reverse-biased PN junction diode current Gate leakage

Tunneling through ultrathin gate dielectric

Subthreshold leakage is the biggest source inmodern transistors


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Low Power Design

Reduce dynamic power

E: clock gating, sleep mode

C: small transistors (esp. on clock), short wires

VDD: lowest suitable voltage f: lowest suitable frequency

Reduce static power

Selectively use ratioed circuits

Selectively use low Vt devices Leakage reduction:

stacked devices, body bias, low temperature


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Chip-to-Package Bonding

Traditionally, chip is surrounded bypadframe

Metal pads on 100 200 Qm pitch

Gold bond wires attach pads to package

Leadfram

e distributes signals in package Metal heatspreaderhelps with cooling


69/71


Bidirectional Pads

Combine input and output pad

Need tristate driver on output

Use enable signal to set direction

Optimized tristate avoids huge series transistorsPAD

Din

Dout

En

Dout

En Y

Dout

NAND

NOR


70/71


Device Scaling


71/71


Interconnect Delay

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23194127 Cmos Vlsi Design

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