5 LOW POWER HARDWARE CHIP IMPLEMENTATION OF TACIT … POWER HARDWA… · 2014-03-05 · Blowfish...

Journal of Electronics and Communication Engineering & Technology (JECET)ISSN

XXX–XXX (Print), ISSN XXX – XXX(Online), Volume 1, Issue 1, July-December(2013)

33

LOW POWER HARDWARE CHIP IMPLEMENTATION OF TACIT

SECURITY ALGORITHM IN TELECOMMUNICATION NETWORKS

USING HDL ENVIRONMENT

Adesh Kumar1, Dr. Sonal Singhal

2, Dr. Piyush Kuchhal

3

1Assistant Professor , Department of Electrical, Electronics & Instrumentation Engineering,

University of Petroleum & Energy Studies, Dehradun, India, 2Assistant Professor, Department of Electronics & Communication Engineering, Shiv Nadar

University, Greater Noida, India 3Associate Professor, Department of Physics, University of Petroleum & Energy Studies,

Dehradun, India,

ABSTRACT

In cryptography, encryption is the process of transforming information (referred to as

plaintext) using an algorithm (called a cipher) to make it unreadable to anyone except those

possessing special knowledge, usually referred to as a key. The result of the process is

encrypted information (in cryptography, referred to as cipher text). The reverse process, i.e.,

to make the encrypted information readable again, is referred to as decryption (i.e., to make it

unencrypted). Encryption is also used to protect data in transit, for example data being

transferred via networks (e.g. the Internet, e-commerce), mobile telephones, wireless

microphones, wireless intercom systems, Bluetooth devices and bank automatic teller

machines. There have been numerous reports of data in transit being intercepted in recent

years. Encrypting data in transit also helps to secure it as it is often difficult to physically

secure all access to networks. In this paper we have introduced a new block cipher

cryptographic symmetric key algorithm named “TACIT Encryption Technique” which has a

unique independent approach by using some suitable mathematical logic along with a new

key distribution system which is being applied on a secure policy based routing. Speed and

size are two important factors while designing the electronic system. It’s Speed of operation

and flexibility to modify, measures the performance of the system operation. Systems based

on microprocessor/microcontroller (MPMC) can handle sequential operations with high

flexibility and use of Complex Programmable Devices (CPLD) can handle concurrent

operations with high speed in small size area. So combined features of both these systems can

enhance the performance of the system by exploiting modern features in Field Programmable

Gate Arrays (FPGA), which allow the modeling of encryption and decryption algorithm on

System-on-Programmable-Chip (SOPC).

Journal of Electronics and Communication Engineering &

Technology (JECET)

ISSN XXX-XXX (Print)

ISSN XXX-XXX (Online)

Volume 1, Issue 1, July-December (2013), pp. 33-45

© IAEME: http://www.iaeme.com/JECET.asp

JECET © I A E M E



34

Keywords: Application Specific Integrated circuits (ASIC), Complex programmable logic

devices (CPLD), Field Programmable Gate Array (FPGA), Network on chip (NOC), System

on chip (SOC), Very Large Scale of Integration (VLSI) , Very High Speed Integrated

Circuit hardware Description language (VHDL).

I. INTRODUCTION

Intellectual property (IP) based networks like the Internet are known for their

scalability and resilience to partial failures. Their reliance on datagram forwarding on a hop-

by-hop basis makes them ideal for the transport of short control messages with little or no

call holding times [22]. Each terminal in the network must have a unique address so

messages or connections can be routed to the correct recipients. Connection-oriented

broadband networks based on asynchronous transfer mode (ATM) technology permit a

much higher degree of predictability to be engineered relatively simply, because of their

inherent resource partitioning capability. They are thus highly suited for transport of streams

with quality of service (QOS) requirements and long call holding times [22]. However, there

is an issue of safe transmission of information when communicating over any untrusted

medium which includes any network particularly the internet (IP based). Cryptography is

being utilized to handle such issues since year. [23] A cryptographic algorithm is considered

to be computationally secured if it cannot be broken with standard resources, either current

or future and apart from the algorithm, distribution of keys is equally important to make an

efficient cryptosystem [23].

Cryptography involves encryption algorithms along with an efficient approach of key

management because there are different algorithms that offer different degree of security [7].

Encryption algorithms are classified according to the type of transformation and keys. In the

broad sense they can be classified as the symmetric and asymmetric approaches. In

symmetric algorithm, the sender and receiver agree on a same (shared) key. In asymmetric

algorithms encryption and decryption of data takes place with two different keys in such a

way that it is difficult to decrypt without the decryption key. Both algorithms were reported

by Tomas and Rene [25] for their application in Third Generation Cellular Networks. Based

upon the algorithm The DES (Data Encryption Standard) and triple DES was implemented in

compliance with the NIST Data Encryption Standard [5, 7]. It processes 64-bit blocks, with

one, two, or three 56-bit keys. However the security and slow processing speed was major

concerns with DES triples respectively. The AES (Advanced Encryption Standard) core

implements Rijndael cipher encoding and decoding in compliance with the NIST Advanced

Encryption Standard [5-6, 11]. AES cipher is specified as a number of repetitions of

transformation rounds that convert the input plaintext into the final output of cipher text.

Each round consists of several processing steps, including one that depends on the encryption

key [7]. Again the processing time was a major concern with AES. Most of today’s

conventional encryption algorithms are implemented in software and their throughputs are

about 10 megabits per second (Mbps) at most if a 128-bit key is used. However, the

explosively growing electronic data transportation often necessitates higher throughput. As a

result, it is desired to implement encryption algorithms into hardware to achieve high-speed

encryption and decryption.

There are many encryption and decryption algorithms which are already proposed. A

comparison [21] of all is shown in table 1 listed below. Table 2 list the comparison of various

encryption algorithms on the basis of Type and Features. It can be seen that from this



35

comparison table that TACIT Encryption Technique has a unique independent approach by

using some suitable mathematical logic along with a new key distribution system which is

being applied on a secure policy based routing [8]. The main advantage of TACIT logic is

that it can processes n-bit blocks and n- bit key size. This approach may be good if the block

size is less than the key size [21]. The algorithm may be implemented in all the languages

support Unicode system facility like Java, C#, .Net, etc.

Table 1 Comparison of various encryption algorithms [21] on the basis of Key size and

Block size. Algorithm Key size(Bits) Block size(Bits)

DES 64 64

Triple DES 192 64

AES Variable (192 or 256) 128

Kasumi Encryption core 128 64

Blowfish 448 64

RSA 1024 128

RC4 Variable(40 or 128) Variable (32,64,128)

X-MODES 32 32

TACIT Encryption n-bit ( n can vary) n-bit

Table 2 Comparison of various encryption algorithms based on Type and Features [21]

Algorithm Type Features

DES Block cipher Most common, Not strong enough

Triple DES Block cipher Modification of DES, Adequate security

AES Block cipher Replacement of DES, Excellent security, limited key

size

Kasumi

Encryption core

Block cipher Designed for Third Generation Partnership

Project(3GPP), used in Universal Mobile

Telecommunication System UMTS, limited to 64-bit

word size

Blowfish Block cipher Excellent security, No. of bits are variable ranging

from 16-448 bits.

RSA Block cipher Asymmetric algorithm, speed is low

RC4 Stream cipher Fast stream chipper in Secured Socket Layer (SSL),

more memory is required since they work on large

chunk of data (stream) instead of block cipher.

X-MODES Block cipher Enhanced security level & faster.

TACIT

Encryption

Block cipher Good for small size of packets

Tools Utilized: Design and FPGA implementation includes the following software

development tools: Project Navigator Application ISE 13.2 of Xilinx Company is a tool to

design the IC and to view their RTL (Register Transfer Logic) schematic. Model SimEE

10.1b students edition of Mentor Graphics Company is used for simulation and debugging the

functionality. The hardware chip implementation is done using VHDL programming

language.

The paper is organized as follows: Section I presents the introduction and the tools

utilized. Section II discusses the NOC Model for the data transfer. Section III presents the



36

data encryption for TACIT logic, section IV presents data decryption for TACIT logic.

Section V describes result and performance evolution and Conclusion is presented in Section

VI.

II. NOC MODEL

Network-on-Chip (NOC) is an approach for designing the telecommunication

subsystem between IP cores in a System-on-a-Chip (SOC). The software and application

layer is a very critical aspect on the NOC communication stack [24]. We mostly focused on

the physical and network layers. Secured transmission among nodes is possible if it is

following the NOC layer protocol. All networked layers follow the pipeline and parallel

processing with coprocessors. This leads to validate the hardware parameters on chip

development: Synthesis Options Summary, VHDL Compilation, VHDL Analysis, Device

utilization summary, Timing report, delay time calculation are the core parameters to design

the chip. A NOC template consists of continuous areas of the chip called regions. Regions are

physically isolated from each other but have special mechanism for communication among

each other. In order to achieve simplicity of interconnections, short cycle time and scalability,

a region of NOC consists of a two dimensional mesh of switches. The computing and other

resources are embedded in the slots within the switches.

Fig. 1 Layered NOC structure for data transmission [24]



37

Fig. 2 Example of NOC architecture [26]

A switch is connected to four other switches. A scalable communication infrastructure

that better supports the trend of SOC integration consists of an on chip packet-switched

micro-network of interconnects generally known as Network-on-Chip (NOC) architecture

[26]. The basic idea is borrowed from tradition a large-scale multi-processors and the wide-

area networks domain, and envisions on-chip router (or switch)-based networks on which

packetized communication takes place, as depicted in Fig. 2 Cores access the network by

means of proper interfaces, and have their packets forwarded to destination through a multi

hop routing path. The scalable and modular nature of NOCs and their support for efficient on-

chip communication [26] potentially leads to NOC-based multi-processor systems

characterized by high structural complexity and functional diversity.

III. DATA ENCRYPTION ALGORITHM FOR TACIT LOGIC

To implement the TACIT Logic for data communication between two nodes of NOC

the following algorithm has been used. The corresponding VHDL coding has been developed

and results are presented in section V.

Step 1: Text file content is read and position of the character is shuffled by using initial

permutation approach using key value.

Step 2: Read the character from the text file corresponding to the text and get the ASCII

value of that character.

Step 3: Perform XOR operation with the specific n-bit key value.

Step 4: A secure tacit logic has been introduced (i.e. nk xor k

k along with some specific

operations; where n is the value computed from step 3).

Step 5: Convert the value into binary one.

Step 6: Perform reverse operation on the binary string.

Step 7: Corresponding decimal value is found.

Step 8: The Unicode character corresponds to the decimal value is formed which is none

other than the cipher text.

Step 9: Continue step 1 to 7 for the next characters of the file until End of File (EOF) is

reached.



38

IV. DATA DECRYPTION ALGORITHM FOR TACIT LOGIC

The decryption algorithm at the receiving end follows the following steps.

Step 1: Read the first character from the cipher text and get the corresponding decimal value

of it.

Step 2: The corresponding binary value is evaluated and make the reverse of it.

Step 3: Inverse of the tacit logic is applied.

Step 4: Perform XOR with n-bit key value.

Step 5: The character corresponds to it is determined.

Step 6: Now reshuffling is done using key value.

Step 7: Repeat the steps (1 to 6) till the end.

4.1 Functional Description

4.1.1 Input value a. Inputs: Keyboard Enter data into system.

Clock: This is the clock used for the core operations.

b. Reset: Asynchronous reset, that sets the device to a known state.

4.1.2. Modes of Operation: a. ASCII Input Mode: The input from the keyboard is considered to be encoded in

ASCII.

b. Hexadecimal Mode: The input from the keyboard is considered to be encoded in

Hexadecimal, thus the only valid characters are 0-9, A-F.

c. Encryption Mode: Device is configured to receive data and output cipher text.

d. Decryption Mode: Device is configured to receive cipher text and output data.

V. RESULTS & PERFORMANCE EVALUTION

5.1 Data Encryption In the screenshots of Fig. 3 text is the input text [0-127] which is encrypted in ASCII

format for each character. Key size is considered as 8 bits and each character is encoded with

key size individually. Key is in integer form and key_value is 8 bits binary value of Key.

Xor_value is the result after XOR of text and key_value. tacit_logic_1 is the value of TACIT

operation nk ( n= no of bits in each character and k= key size). In our case n value is fixed, n

= 8 and k value is variable 0 to 255 in decimal. tacit_logic_2 is the value of TACIT operation

kk. tacit_logic is the actual value of TACIT logic n

k XOR k

k, reverse value is the value of

reverse operation on tacit_value. After it the corresponding decimal value is kept by

intermediate signal decimal_value. ciper_text is the intermediate value of cipher text in

encryption logic and ctext represents the actual cipher text.



39

Fig. 3 Modelsim Simulation (Data Encryption of 128 bits block size

Encryption of plaintext text [ ]= [127 : 0] by the external key k[ ] = [7 : 0] will produce a

cipher text ctext[ ] = [ 127 : 0]. For encryption, RESET is set to high at first but low for the

rest of time RESET is low. Positive clock pulse clk is applied for the synchronization.

Step input 1: reset = 1, positive clock pulse clk ia applied and tenn run in Modelsim

simulator.

Step input 2: reset = 0, positive clock pulse clk , n = 8, Key = input in decimal, text = [127 :

0] block size and run in modelsim simulator. Fig. 3 shows the simulation results of data

Encryption, for a word length of 128 bits.



40

5.2 Data Decryption

Fig. 4: Modelsim Simulation (Data Decryption for 128 bits block size)

In the screen shot of decryption logic Fig.4, ctext is the input cipher text to decryption

logic ctext[0-127] which is decrypted in ASCII format for each character. Key size is

considered same as 8 bit and each character is encoded with key size individually. Key is in

integer form and key_value is 8 bit binary value of Key. Xor_value is the result after XOR of

text and key_value. tacit_logic_1 is the value of TACIT operation nk ( n= no of bits in each

character and k= key size). In our case n value is fixed, n = 8 and k value is variable 0 to 255

in decimal. tacit_logic_2 is the value of TACIT operation kk. tacit_logic is the actual value of

TACIT logic nk XOR k

k, reverse value is the value of reverse operation on tacit_value. After

it the corresponding decimal value is kept by intermediate signal decimal_value. ciper_text is

the intermediate value of cipher text in encryption logic and ctext represents the actual cipher

text.

The decryption of cipher text ctext[127: 0][F823AB657CED ..1894] using the same

key k [7:0] produces the original plaintext text[127:0] = [F413579ABCDE2468..] For

decryption, RESET is set to high at first but low for the rest of time RESET is low. Positive

clock pulse clk is applied for the synchronization.



41

Step input 1: reset = 1, positive clock pulse clk ia applied and tenn run in Modelsim

simulator.

Step input 2: reset = 0, positive clock pulse clk, n = 8, Key = input in decimal, ctext = [127:

0] block size and run in modelsim simulator. Fig. 4 shows the simulation results of data

decryption, for a word length of 128 bits.

5.3 Device Utilization and timing Summary for encryption Device utilization is the hardware and logic circuitry required to implement the

design. It consist of no. of slices, flip flops, gates, combinational logic circuitry and

input/output blocks. Selected Device: 2vp2fg256-6, this is the device for targeting FPGA

with Speed Grade: - 6

Table 3 Device utilization in encryption logic

Device part Device Utilization

8 bit block size 64 bit block size 128 bit block

size

Number of Slices 16 out of 1408 1% 32 out of 1408 2% 72 out of

1408 5%

Number of Slice Flip

Flops

19 out of 2816 0% 55 out of 2816 1% 124 out of

2816 4%

Number of 4 input

LUTs


2816 1%

Number of bonded

IOBs


140 92%

Number of GCLKs 1 out of 16 6% 1 out of 16 6% 1 out of

16 6%

5.4 Device Utilization and timing Summary for decryption Selected Device: 2vp2fg256-6, this is the device for targeting FPGA with Speed

Grade: -6

Table 4 Device utilization in decryption logic

Device part Device Utilization

8 bit block size 64 bit block size 128 bit block size

Number of Slices 10 out of 1408

0%

43 out of 1408

3%

79 out of 1408

5%

Number of Slice Flip

Flops

17 out of 2816

0%

74 out of 2816

2%

138 out of 2816

4%

Number of 4 input

LUTs

13 out of 2816

0%

70 out of 2816

2%

134 out of 2816

4%

Number of bonded

IOBs

17 out of 140

12%

129 out of 140

92%

137 out of 140

97%

Number of GCLKs 1 out of 16

6%

1 out of 16

6%

1 out of 16

6%



42

Fig. 5 Comparison of minimum period in encryption and decryption (for 8, 64 and 128 bits)

The graphs shown in the Fig. 5 shows the percentage change in the minimum period

with respect to number of bits for encryption and decryption. X axis has no of bits and Y axis

has minimum period. In encryption, the percentage change in minimum period is 5.8 % and

1.2 % when the block size changes from 8 bits to 64 bits and 64 bits to 128 bits respectively.

In decryption, the percentage change in minimum period is 10.4 % and 0 % when the block

size changes from 8 bits to 64 bits and 64 bits to 128 bits respectively. The reason in the

drastic increment in the number of IOB’s is larger block size; we are dividing the block size

into 8 bits ASCII character blocks to encrypt the data.

5.5 Timing Summary Timing details provides the information of delay, minimum period, minimum input

arrival time before clock and maximum output required time after clock

Table 5 Timing details for encryption logic

Timing information Utilization

8 bit

block size

64 bit

block size

128 bit

block size

Minimum period

Maximum Frequency

Minimum input arrival time before clock

Maximum output required time after clock

Total Memory usage

1.565ns

638.978MHz

2.725ns

4.483ns

78040 KB

1.507ns

663.350MHz

2.725ns

4.483ns

82136 KB

1.519ns

658.328MHz

2.725ns

4.483ns

87832 KB

Table 6 Timing details for decryption logic

Timing information Utilization

8 bit block

size

64 bit block

size

128 bit block

size

Minimum period

Maximum Frequency

Minimum input arrival time before clock:

Maximum output required time after clock

Total Memory usage

1.588ns

629.723MHz

2.725ns

4.483ns

75992 kB

1.484ns

673.628MHz

2.748ns

4.483ns

77016 kB

1.484ns

673.628MHz

2.748ns

4.483ns

79064 kB



43

The graph shown in the Fig. 6 shows the percentage change in the total memory with

respect to number of bits for encryption and decryption. X axis has no of bits and Y axis has

total memory. In encryption, the percentage change in total memory is 5.8 % and 56.96 %

when the block size changes from 8 bits to 64 bits and 64 bits to 128 bits respectively. In

decryption, the percentage change in total memory is 40.96 % and 20.48 % when the block

size changes from 8 bits to 64 bits and 64 bits to 128 bits respectively. The reason in greater

change in the memory is increment in the number of IOB’s. We are dividing the block size

into 8 bits ASCII character blocks to encrypt/ decrypt the data. Separate memory allocation

and IOBs for each character consumes more memory but it increases the speed due to

pipelining.

Fig. 6 Comparison of total memory in encryption and decryption (for 8, 64 and 128 bits)

VI. CONCLUSION

The hardware chip implementation of TACIT logic for encryption and decryption is

implemented in Xilinx 13.2 and functional simulated in Modelsim 10.1 b. We have

implemented for one character (8 bits), 64 bits, 128 bits and key size was taken 8 bits, and it

means sender and receiver both can enjoy with key range 0 to 255 in (decimal). The main

advantage of the TACIT logic is that we can enhance the block size and key size both. In

future, we can implement the encryption and decryption for larger size of text and key.

Compression techniques could be implemented along with encryption procedure.

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