5G LDPC-V Intel® FPGA IP User Guide · 2020-01-19 · Table 1. 5G LDPC-V IP Device Family Support....

5G LDPC-V Intel® FPGA IP UserGuide

Updated for Intel® Quartus® Prime Design Suite: 19.2

IP Version: 0.1.0

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Contents

1. About the 5G LDPC-V Intel® FPGA IP.............................................................................. 31.1. 5G LDPC-V Intel FPGA IP Features........................................................................... 41.2. 5G LDPC-V Intel FPGA IP Device Family Support........................................................ 41.3. Release Information for the 5G LDPC-V Intel FPGA IP................................................. 5

2. Getting Started with the 5G LDPC-V Intel FPGA IP..........................................................62.1. Installing and Licensing Intel FPGA IP Cores.............................................................. 6

2.1.1. Intel FPGA IP Evaluation Mode.....................................................................72.1.2. 5G LDPC-V IP Timeout Behavior...................................................................9

3. Designing with the 5G LDPC-V Intel FPGA IP................................................................ 103.1. 5G LDPC-V IP Directory Structure.......................................................................... 103.2. Simulating the Transmitter 5G LDPC-V Intel FPGA IP ................................................103.3. Simulating the Receiver 5G LDPC-V Intel FPGA IP ....................................................113.4. 5G LDPC-V Simulation Results............................................................................... 12

4. 5G LDPC-V Intel FPGA IP Functional Description.......................................................... 224.1. 5G LDPC-V Transmitter Functional Description......................................................... 22

4.1.1. 5G LDPC-V Transmitter Signals.................................................................. 224.2. 5G LDPC-V Receiver Functional Description..............................................................27

4.2.1. 5G LDPC-V Receiver Signals...................................................................... 284.3. Avalon Streaming Interfaces in DSP Intel FPGA IP.................................................... 34

5. Document Revision History for the 5G LDPC-V Intel FPGA IP User Guide......................35

Contents

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1. About the 5G LDPC-V Intel® FPGA IPLow-density parity-check (LDPC) codes are linear error correcting codes that help youto transmit and receive messages over noisy channels. The 5G LDPC-V Intel® FPGA IPimplements LDPC codes compliant with the 3rd Generation Partnership Project (3GPP)5G specification for integration in your wireless design. LDPC codes offer betterspectral efficiency than Turbo codes and support the high throughput for 5G new radio(NR).

The 5G LDPC-V IP is a complete channel coding IP that is optimized for virtual radioaccess networks (vRAN). The 5G LDPC-V IP is based on the 5G LDPC Intel FPGA IPand includes a 5G NR LDPC channel coder, which comprises:

• LDPC code block segmentation CRC module

• LDPC encoder and decoder

• LDPC rate matcher and derate matcher

• Hybrid automatic repeat request (HARQ) block (decoder only)

Figure 1. 5G LDPC-V IP

HARQ

EncodingDecoding

5G LPDC IP(De)rate- matcher CRC

Related Information

• 3GPP New Radio SpecificationThe final equivalents are Release 15, 3GPP Technical Specification Group RAN1, NR:

• (1) Multiplexing and channel coding, 3GPP TS 38.212 (v15.3.0)

• (2) Physical layer procedures for data, 3GPP TS 38.214 (v15.3.0)

• 5G LPDC Intel FPGA IP User Guide

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1.1. 5G LDPC-V Intel FPGA IP Features

• 3GPP 5G LDPC specification compliant

• For the transmitter:

— Code block segmentation CRC module

— Rate matcher

— Per-block modifiable code block length and code rate

• For the receiver:

— • Derate matcher

• Hybrid automatic repeat request (HARQ) block

• Code block segmentation CRC module

• Per-block modifiable code block length, code rate, base graph, andmaximum number of iterations

• Configurable input precision

• Layered decoder scheduling architecture to double the speed ofconvergence compared to non-layered architecture

• Early termination based on the syndrome check after each iteration

• No external memory requirement

• MATLAB and C++ models for performance simulation and RTL test vectorgeneration

• Verilog HDL testbench option

Related Information

3GPP New Radio LDPC Specification

1.2. 5G LDPC-V Intel FPGA IP Device Family Support

Intel offers the following device support levels for Intel FPGA IP:

• Advance support—the IP is available for simulation and compilation for this devicefamily. FPGA programming file (.pof) support is not available for Quartus PrimePro Stratix 10 Edition Beta software and as such IP timing closure cannot beguaranteed. Timing models include initial engineering estimates of delays basedon early post-layout information. The timing models are subject to change assilicon testing improves the correlation between the actual silicon and the timingmodels. You can use this IP core for system architecture and resource utilizationstudies, simulation, pinout, system latency assessments, basic timing assessments(pipeline budgeting), and I/O transfer strategy (data-path width, burst depth, I/Ostandards tradeoffs).

• Preliminary support—Intel verifies the IP core with preliminary timing models forthis device family. The IP core meets all functional requirements, but might still beundergoing timing analysis for the device family. You can use it in productiondesigns with caution.

• Final support—Intel verifies the IP with final timing models for this device family.The IP meets all functional and timing requirements for the device family. You canuse it in production designs.

1. About the 5G LDPC-V Intel® FPGA IP

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Table 1. 5G LDPC-V IP Device Family Support

Device Family Support

Intel Stratix® 10 Advance

Intel Arria® 10 Final

Other device families No support

1.3. Release Information for the 5G LDPC-V Intel FPGA IP

IP versions are the same as the Intel Quartus® Prime Design Suite software versionsup to v19.1. From Intel Quartus Prime Design Suite software version 19.2 or later, IPcores have a new IP versioning scheme.

The IP versioning scheme (X.Y.Z) number changes from one software version toanother. A change in:

• X indicates a major revision of the IP. If you update your Intel Quartus Primesoftware, you must regenerate the IP.

• Y indicates the IP includes new features. Regenerate your IP to include these newfeatures.

• Z indicates the IP includes minor changes. Regenerate your IP to include thesechanges.

Table 2. 5G LDPC-V IP Release Information

Item Description

Version 0.1.0

Release Date August 2019

1. About the 5G LDPC-V Intel® FPGA IP

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2. Getting Started with the 5G LDPC-V Intel FPGA IPRelated Information

• Introduction to Intel FPGA IP

• IP Catalog and Parameter EditorThe IP Catalog displays the IP available for your project.

• Generating Intel FPGA IPQuickly configure Intel FPGA IP cores in the Intel Quartus Prime parametereditor. Double-click any component in the IP Catalog to launch the parametereditor. The parameter editor allows you to define a custom variation of the IPcore. The parameter editor generates the IP variation synthesis and optionalsimulation files, and adds the .ip file representing the variation to yourproject automatically.

2.1. Installing and Licensing Intel FPGA IP Cores

The Intel Quartus Prime software installation includes the Intel FPGA IP library. Thislibrary provides many useful IP cores for your production use without the need for anadditional license. Some Intel FPGA IP cores require purchase of a separate license forproduction use. The Intel FPGA IP Evaluation Mode allows you to evaluate theselicensed Intel FPGA IP cores in simulation and hardware, before deciding to purchase afull production IP core license. You only need to purchase a full production license forlicensed Intel IP cores after you complete hardware testing and are ready to use theIP in production.

The Intel Quartus Prime software installs IP cores in the following locations by default:

Figure 2. IP Core Installation Path

intelFPGA(_pro)

quartus - Contains the Intel Quartus Prime softwareip - Contains the Intel FPGA IP library and third-party IP cores

altera - Contains the Intel FPGA IP library source code<IP name> - Contains the Intel FPGA IP source files

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Table 3. IP Core Installation Locations

Location Software Platform

<drive>:\intelFPGA_pro\quartus\ip\altera Intel Quartus Prime Pro Edition Windows*

<drive>:\intelFPGA\quartus\ip\altera Intel Quartus Prime StandardEdition

Windows

<home directory>:/intelFPGA_pro/quartus/ip/altera Intel Quartus Prime Pro Edition Linux*

<home directory>:/intelFPGA/quartus/ip/altera Intel Quartus Prime StandardEdition

Linux

2.1.1. Intel FPGA IP Evaluation Mode

The free Intel FPGA IP Evaluation Mode allows you to evaluate licensed Intel FPGA IPcores in simulation and hardware before purchase. Intel FPGA IP Evaluation Modesupports the following evaluations without additional license:

• Simulate the behavior of a licensed Intel FPGA IP core in your system.

• Verify the functionality, size, and speed of the IP core quickly and easily.

• Generate time-limited device programming files for designs that include IP cores.

• Program a device with your IP core and verify your design in hardware.

Intel FPGA IP Evaluation Mode supports the following operation modes:

• Tethered—Allows running the design containing the licensed Intel FPGA IPindefinitely with a connection between your board and the host computer.Tethered mode requires a serial joint test action group (JTAG) cable connectedbetween the JTAG port on your board and the host computer, which is running theIntel Quartus Prime Programmer for the duration of the hardware evaluationperiod. The Programmer only requires a minimum installation of the Intel QuartusPrime software, and requires no Intel Quartus Prime license. The host computercontrols the evaluation time by sending a periodic signal to the device via theJTAG port. If all licensed IP cores in the design support tethered mode, theevaluation time runs until any IP core evaluation expires. If all of the IP coressupport unlimited evaluation time, the device does not time-out.

• Untethered—Allows running the design containing the licensed IP for a limitedtime. The IP core reverts to untethered mode if the device disconnects from thehost computer running the Intel Quartus Prime software. The IP core also revertsto untethered mode if any other licensed IP core in the design does not supporttethered mode.

When the evaluation time expires for any licensed Intel FPGA IP in the design, thedesign stops functioning. All IP cores that use the Intel FPGA IP Evaluation Mode timeout simultaneously when any IP core in the design times out. When the evaluationtime expires, you must reprogram the FPGA device before continuing hardwareverification. To extend use of the IP core for production, purchase a full productionlicense for the IP core.

You must purchase the license and generate a full production license key before youcan generate an unrestricted device programming file. During Intel FPGA IP EvaluationMode, the Compiler only generates a time-limited device programming file (<projectname>_time_limited.sof) that expires at the time limit.

2. Getting Started with the 5G LDPC-V Intel FPGA IP

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Figure 3. Intel FPGA IP Evaluation Mode Flow

Install the Intel Quartus Prime Software with Intel FPGA IP Library

Parameterize and Instantiate aLicensed Intel FPGA IP Core

Purchase a Full Production IP License

Verify the IP in a Supported Simulator

Compile the Design in theIntel Quartus Prime Software

Generate a Time-Limited DeviceProgramming File

Program the Intel FPGA Deviceand Verify Operation on the Board

No

Yes

IP Ready forProduction Use?

Include Licensed IP in Commercial Products

Note: Refer to each IP core's user guide for parameterization steps and implementationdetails.

Intel licenses IP cores on a per-seat, perpetual basis. The license fee includes first-year maintenance and support. You must renew the maintenance contract to receiveupdates, bug fixes, and technical support beyond the first year. You must purchase afull production license for Intel FPGA IP cores that require a production license, beforegenerating programming files that you may use for an unlimited time. During IntelFPGA IP Evaluation Mode, the Compiler only generates a time-limited deviceprogramming file (<project name>_time_limited.sof) that expires at the timelimit. To obtain your production license keys, visit the Self-Service Licensing Center.

The Intel FPGA Software License Agreements govern the installation and use oflicensed IP cores, the Intel Quartus Prime design software, and all unlicensed IP cores.


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https://www.intel.com/content/www/us/en/my-intel/fpga-sign-in.html

http://dl.altera.com/eula/


Related Information

• Intel Quartus Prime Licensing Site

• Introduction to Intel FPGA Software Installation and Licensing

2.1.2. 5G LDPC-V IP Timeout Behavior

All IP in a device time out simultaneously when the most restrictive evaluation time isreached. If a design has more than one IP, the time-out behavior of the other IP maymask the time-out behavior of a specific IP .

For IP, the untethered time-out is 1 hour; the tethered time-out value is indefinite.Your design stops working after the hardware evaluation time expires. The QuartusPrime software uses Intel FPGA IP Evaluation Mode Files (.ocp) in your projectdirectory to identify your use of the Intel FPGA IP Evaluation Mode evaluationprogram. After you activate the feature, do not delete these files.

When the evaluation time expires, for the transmitter o32_source_data goes low;for the receiver o32_source_data and o8_ldpc_metrics go low.

Related Information

AN 320: OpenCore Plus Evaluation of Megafunctions


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https://www.intel.com/content/www/us/en/my-intel/fpga-sign-in.html

https://www.intel.com/content/www/us/en/programmable/documentation/esc1425946071433.html#esc1426013042774

http://www.altera.com/literature/an/an320.pdf


3. Designing with the 5G LDPC-V Intel FPGA IP

3.1. 5G LDPC-V IP Directory Structure

The IP includes a c_model, rtl, and testbench directory.

Table 4. Files in the c_model Directory

Other .c and .cpp files in c_model are obfuscated models of different blocks.

File Description

ldpc5g_tx_chain.c Clear-text transmitter chain wrapper

ldpc5g_tx_chain_test.c Clear-text transmitter chain testbench

ldpc5g_rx_chain.cpp Clear-text receiver chain wrapper

ldpc5g_rx_chain_test.cpp Clear-text receiver chain testbench

ldpc5g_gen_tc.c Clear-text test cases for transmitter and receiver chain

Table 5. Directories in the rtl Directory

File Description

cleartext Clear-text RTL files

aldec Encrypted RTL files for Aldec

cadence Encrypted RTL files for NCSim

mentor Encrypted RTL files for ModelSim

synopsys Encrypted RTL files for VCS

quartus Encrypted RTL files for Intel Quartus Prime

3.2. Simulating the Transmitter 5G LDPC-V Intel FPGA IP

1. Compile the C code of the transmitter chain.

>> gcc -lm ldpc5g_tx_chain_test.c -o run

2. Run the executable from the c_model\ directory, where the first argument is testcase number, the second argument is to enable or disable HARQ testing.

>>./run 6 0 to run test case 6 with HARQ disabled.

>>./run 10 1 to run test case 10 with HARQ enabled.

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If you enable HARQ, the IP processes two transmissions of the code block, withuse_harq=0 for the first transmission and use_harq=1 for the secondtransmission.

The executable generates tx_param.txt tx_in.txt, and tx_out.txt.

3. Set HARQ to 0 or 1 to enable or disable HARQ testing:

• Either `define HARQ = 0 in the testbench

• Or pass +define+HARQ=0 from the simulation command.

4. Run VCS:

#!/bin/csh -f

set top = ldpc5g_tx_half_test vcs +v2k +vc -sverilog -Mupdate -line -full64 -timescale=1ns/1ps -negdelay +neg_tchk +overlap +multisource_int_delays +memcbk -debug_pp +define+HARQ=1 +define+DEBUG_DRM_DESEL \ -v ./altera_mf.v \ -v ./altera_lnsim.sv \ $top.sv \ -o simv \ | tee compile.log ./simv

Dve &

Related Information

Simulator Support

3.3. Simulating the Receiver 5G LDPC-V Intel FPGA IP

Simulate the transmitter before you simulate the receiver.

1. Compile the C code of the receiver chain.

>> g++ -lm ldpc5g_rx_chain_test.cpp -o run

2. Run the executable from the c_model\ directory, where the first argument is testcase number, the second argument is to enable or disable HARQ testing.

>>./run 6 0 to run test case 6 with HARQ disabled.

>>./run 10 1 to run test case 10 with HARQ enabled.

The executable takes tx_out.txt and generates rx_in.txt, rx_param.txt,and rx_out.txt.

3. Set HARQ to 0 or 1 to enable or disable HARQ testing:

• Either `define HARQ = 0 in the testbench

• Or pass +define+HARQ=0 from the simulation command.

4. Run VCS:

#!/bin/csh -f set top = ldpc5g_rx_half_test vcs +v2k +vc -sverilog -Mupdate -line -full64 -timescale=1ns/1ps -negdelay +neg_tchk +overlap +multisource_int_delays +memcbk -debug_pp +define+HARQ=1 +define+DEBUG_DRM_DESEL \ -v ./altera_mf.v \ -v ./altera_lnsim.sv \


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$top.sv \ -o simv \ | tee compile.log

./simv

Dve &

Related Information

Simulator Support

3.4. 5G LDPC-V Simulation Results

Figure 4. Transmitter Top-level Simulation Results

Figure 5. Transmitter Top-level Simulation Results: Detailed Part 1


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Figure 6. Transmitter Top-level Simulation Results: Detailed Part 2

Figure 7. Transmitter Encoder Simulation Results

Figure 8. Transmitter Encoder Simulation Results: Detailed Part 1


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Figure 9. Transmitter Encoder Simulation Results: Detailed Part 2

Figure 10. Transmitter CRC Encoder Simulation Results

Figure 11. Transmitter CRC Encoder Simulation Results: Detailed Part 1


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Figure 12. Transmitter CRC Encoder Simulation Results: Detailed Part 2

Figure 13. Transmitter Rate Matcher Simulation Results

Figure 14. Transmitter Rate Matcher Simulation Results: Detailed Part 1


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Figure 15. Receiver Top-level Simulation Results

Figure 16. Receiver Top-level Simulation Results: Detailed Part 1


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Figure 17. Receiver Top-level Simulation Results: Detailed Part 2

Figure 18. Receiver CRC Simulation Results

Figure 19. Receiver HARQ Simulation Results


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Figure 20. Receiver Decoder 0 Simulation Results

Figure 21. Receiver Decoder 0 Simulation Results: Detailed Part 1


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Figure 23. Receiver Decoder 1 Simulation Results


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Figure 26. Receiver Derate Matcher Simulation Results


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4. 5G LDPC-V Intel FPGA IP Functional DescriptionThe 5G LDPC-V Intel FPGA IP comprises an encoder and a decoder.

5G LDPC-V Transmitter Functional Description on page 22

5G LDPC-V Receiver Functional Description on page 27

Avalon Streaming Interfaces in DSP Intel FPGA IP on page 34

4.1. 5G LDPC-V Transmitter Functional Description

The LDPC code block segmentation CRC module attaches the CRC for each code blockand inserts null bit refer to 3GPP TS 38.212. Also, the LDPC code block segmentationCRC module controls its input pace.

The LDPC encoder takes code block data from LDPC code block segmentation CRCmodule and produces the encoded code block LDPC for the rate matcher.

The LDPC rate matcher implements the rate matching processing (refer to 3GPP TS38.212) and concatenates the rate matched code block for its output.

All the submodules’ interfaces are based on Avalon streaming interface specification.

Related Information

Avalon Interface Specifications

4.1.1. 5G LDPC-V Transmitter Signals

All signals are synchronous to clk.

Figure 27. Transmitter SignalsThis figure does not show the Avalon streaming interface signals

i32_sink_data

i70_Idpc_paras

clk rstn

CodeBlock CRC Rate matcher

o32_source_data

LDPCEncoder 3843232 32

Top-level Design

Table 6. Transmitter Top-Level Signals

Name I/O Description

clk Input Clock. All signals are synchronous to clk.

rstn Input Reset, active-low. Assert for at least for 10 clock cycles.

continued...

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i70_ldpc_paras Input Aligns with i_sink_cb_sop[0] is base graph (BG) (1 bit), where: 0:BG1, 1:BG2[6:1] is Zc_idx (6 bits)BG is the index of the lifting factor Zc. Choose Zc from Table 5.3.2-1 of TS 38.212. Look upthe index of Zc in Table 10 on page 26.[7] is use_crc (1 bit), where 0: not use code block CRC; 1: use code block CRC (CRC24B).[17:8] is the number of null bits (10 bits). Plug in the value of K-K’, where K=22Zc(BG1) or10Zc(BG2). Check the definition of K and K’ in 5.2.2 in TS 38.212.[20:18] is the code rate index (3 bits). The Table 11 on page 27 table shows the code ratechoices supported by the LDPC encoder and decoder IP. The code rate is not target coderate.[23:21] is Qm_idx (3 bits):• 0:BPSK• 1:QPSK• 2:16QAM• 3: 64QAM• 4:256QAM[39:24] is E (16 bits), the output length of the rate matcher, or equivalently, input length ofthe derate matcher. E should be larger than 32.[54:40] is k0, the position (15 bits). Calculate k0 based on Table 5.4.2.1-2 of TS 38.212.[69:55] is Ncb (15 bits), the limited circular buffer size.

i32_sink_data Input 32 message bits.• [0]: msg seq# 0• [1]: msg seq# 1• …• [31]: msg seq# 31Total number of input bits is K’ if CRC is not used; K’-24 if CRC is used

i_sink_valid Input Qualifies the i32_sink_data signalWhen i_sink_valid is not asserted, the IP stops processing input until i_sink_valid signal isreasserted. Assert when o_sink_ready is asserted.

i_sink_cb_sop Input Indicates the start of an incoming packetYou cannot have two valid SOPs in any five consecutive clock cycles

i_sink_cb_eop Input Indicates the end of an incoming packet

o_sink_ready Output Indicates that the receiver is ready to receive data in the next clock cycle. Ignore when rstis asserted.The IP can backpressure incoming data by deasserting this signal. When o_sink_ready==0is observed, deassert i_sink_valid in the next clock cycle.

o32_source_data Output 32 output bits from rate matcher• data[0] -> bit0• data[1] -> bit1• …• data[31] -> bit31Total number of output bits is E.

o_source_valid Output The transmitter asserts this signal when o32_source_data holds valid data.

o_source_cb_sop Output The transmitter asserts this signal to mark the start of a packet.

o_source_cb_eop Output The transmitter asserts this signal to mark the end of a packet

4. 5G LDPC-V Intel FPGA IP Functional Description

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Table 7. Code block CRC Module Signals

Signal Direction Description

rstn Input Active-low reset. Assert for at least for10 clock cycles.

clk Input Positive-edge triggered clock.

i_param_wren Input Parameter interface write enable.

i_param_wrdata[34:0] Input Parameter interface write data:• [34:25]: number of nulls• [24:11]: Kp• [10:2]: Zc (Table 10 on page 26)• [1]: base graph• [0]: use CRC

sink_data[31:0] Input Sink data:• [0]: data seq# 0• [1]: data seq# 1• ...

sink_eop Input Sink EOP

sink_sop Input Sink SOP

sink_valid Input Sink valid

sink_ready Output Sink ready

source_ready Input Source ready.

source_data[31:0] Output Source data:• [0]: data seq# 0• [1]: data seq# 1• ...For BG=0, the block needs 22*12clocks to generate all data; for BG=1,10*12 clocks to generate all data. Eachgroup of 12 clocks generates Zc bits. IfZc is less than 384, pad 0s.

source_eop Output Source EOP

source_sop Output Source SOP

source_valid Output Source valid

Figure 28. Code Block CRC Module Source Data PaddingFor BG = 0 and Zc = 40

cyc | source_data----+-------------0 | b31 ........... b01 | 0 ... 0 b39 ... b32... | ...11 | 0 ............. 0----+-------------12 | b71 ........... b4013 | 0 ... 0 b79 ... b72... | ...23 | 0 ............. 0----+--------------... | ...


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Table 8. Encoder Signals


rst_n Input Active-low reset. Assert for at least for10 clock cycles.


i_param_wren Input Parameter interface write enable.

i_param_wrdata[19:0] Input Parameter interface write data:• [0]: Base Graph [3:1]: Zj• [7:4]: Zmin• [16:8]: Zc lifting factor values

(Table 10 on page 26)• [19:17]: Code rate (Table 11 on

page 27)where: Zc = Zmin * 2^Zj

sink_data[31:0] Input Sink data (refer to CRC modulesource_data format).





source_ready Input Source ready. Assert to indicate thesource interface can accept new data.Assert for one cycle as the sourceignores until one cycle aftersource_sop is asserted.

source_data[383:0] Output Source data:• [0]: data seq# 0• [1]: data seq# 1• ...




Table 9. Rate Matcher Signals




cfg_vld_in Input Configuration interface write enable.Requires four cycles to program.

cfg_data_in[31:0] Input Configuration interface write data:

continued...


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• Clock cycle 0:— [31:16]: Ncb— [15:0]: E—

• Clock cycle 1:— [28:20]: Zc (Table 10 on page

26)— [18]: base graph— [17:12]: Number of rows in PCM

(Table 11 on page 27)— [11:8] Qm

• Clock cycle 2:— [31:16]: E/Qm— [14:0]: K0

• Clock cycle 3:— [29:16]: (K-2)*Zc— [13:0]: (Kp-2)*Zc

sink_data[383:0] Input Sink data









Table 10. Lifting Factor Index

Zc Zc_idx Zc Zc_idx Zc Zc_idx Zc Zc_idx

– – 20 16 80 32 320 48

– – 22 17 88 33 352 49

4 2 24 18 96 34 384 50

5 3 26 19 104 35 – –

6 4 28 20 112 36 – –

7 5 30 21 120 37 – –

8 6 32 22 128 38 – –

9 7 36 23 144 39 – –

10 8 40 24 160 40 – –

11 9 44 25 176 41 – –

12 10 48 26 192 42 – –

continued...


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13 11 52 27 208 43 – –

14 12 56 28 224 44 – –

15 13 60 29 240 45 – –

16 14 64 30 256 46 – –

18 15 72 31 288 47 – –

Table 11. Code Rate Index

Code RateIndex

Code Rate Base Graph 1 Base Graph 2

Number of Rows inParity Check

Matrix

Number of Columnsin Parity Check

Matrix


Matrix


Matrix

000 1/5 NA NA 42 52

001 1/3 46 68 22 32

010 2/5 35 57 17 27

011 1/2 24 46 12 22

100 2/3 13 35 7 17

101 22/30 (~3/4) 10 32 NA NA

110 22/27 (~5/6) 7 29 NA NA

111 22/25 (~8/9) 5 27 NA NA

4.2. 5G LDPC-V Receiver Functional Description

The receiver comprises: a LDPC derate matcher, HARQ block, LDPC decoder, and LDPCcode block segmentation CRC module.

LDPC derate matcher implements the rate recovery process, which is to reverse ratematching process. Refer to 3GPP Specification 38.212.

The HARQ block stores and combines derate matcher outputs from previous andcurrent transmissions for LDPC decoder.

LDPC decoder implements the LDPC decode process, which is to reverse the LDPCencode process. Refer to 3GPP Specification 38.212.

The LDPC code block segmentation CRC module checks the 24-bit CRC embedded inthe LDPC decoded bits. The LDPC code block segmentation CRC module. Refer to 3GPPSpecification 38.212.

Table 12. Receiver Parameters

Parameter Value

DUAL_DECODER • 0: one LDPC decoder in receiver chain• 1: two LDPC decoders in receiver chain

LLR_W Log-likelihood ratio (LLR) bit width, can be either 5 or 6


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4.2.1. 5G LDPC-V Receiver Signals

All signals are synchronous to clk.

Figure 29. Receiver Top-level Block DiagramThis figure does not show the Avalon streaming interface signals

.

i80_sink_data

i103_Idpc_paras

clkrstn

Deratematcher

Code Block CRC

AvalonStreaming

o32_source_data

3232xLLR_W

32xLLR_W

16xLLR_W

32

Top-level Designo8_ldpc_metrics

LDPCDecoder 0

LDPCDecoder 1

Avalon Memory-Mapped InterfaceDDRSDRAM

HARQ(Cleartext)

Table 13. Receiver Top-level Signals


clk Input Clock. All signals are synchronous to clk.

rstn Input Reset, active-low. Assert for at least for 10 clock cycles.

i103_ldpc_paras Input Align with i_sink_cb_sop.[0] is base graph (BG) (1 bit):• 0:BG1• 1:BG2[6:1] is Zc_idx (6 bits), the index of lifting factor Zc. Choose Zc from Table 5.3.2-1of TS38.212. Look up the index of Zc using Lifting Factor.[7] is use_crc (1 bit)• 0: not use code block CRC• 1: use code block CRC (CRC24B)[17:8] is the number of null bits (10 bits). Plug in the value of K-K’, whereK=22Zc(BG1) or 10Zc(BG2). Check the definition of K and K’ in section 5.2.2 in TS38.212[20:18] is the code rate index (3 bits). The Code Rate Index table shows the coderate choices supported by the LDPC encoder and decoder IP. The code rate is notthe target code rate.[23:21] is Qm_idx (3 bits):• 0:BPSK• 1:QPSK• 2:16QAM• 3: 64QAM• 4:256QAM[39:24] is E (16 bits), the output length of the rate matcher, or equivalently, theinput length of the derate matcher.[54:40] is k0 position (15 bits). Calculate k0 based on Table 5.4.2.1-2 of TS38.212.[60:55] is max_iter (6 bits), the maximum number of iterations of LDPC decoding.[61] is use_harq (1 bit):• 0: not use HARQ,• 1: use HARQ[76:62] is cb_old_len (15 bit), the length of the previously combined code blockalready stored in DRR.

continued...


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[102:77] is cb_ddr_addr (26 bit), the base address to DDR for the combined codeblock.[103] is et_dis (1 bit), the decoder early termination disable.

i80_sink_data Input 16 LLRs x 5 bits per LLR[LLR_W-1:0]: LLR seq# 0, [LLR_W*2-1:LLR_W]: LLR seq #1,...

i_sink_valid Input Qualifies the i80_sink_data signalWhen i_sink_valid is not asserted, the IP stops processing input until i_sink_validsignal is reasserted. Asserted when o_sink_ready is asserted.

i_sink_cb_sop Input Indicates the start of an incoming packetYou cannot have two valid SOPs in any four consecutive clock cycles

i_sink_cb_eop Input Indicates the end of an incoming packet

o_sink_ready Output Indicates that the receiver is ready to receive data in the next clock cycle. Ignorewhen rstn is asserted.The IP can backpressure incoming data by deasserting this signal: when you seeo_sink_ready==0, deassert i_sink_valid in the next clock cycle

o32_source_data Output LDPC decoded hard bits, including code block CRC bit, not including NULL padding(K-K').data[0] -> bit0, data[1] -> bit1,…,data[31] -> bit31

o_source_valid Output The receiver asserts this signal when o32_source_data holds valid data

o_source_cb_sop Output The receiver asserts this signal to indicate the start of a packet

o_source_cb_eop Output The receiver asserts this signal to indicate the end of a packet

o8_ldpc _metrics Output [0] is source_crc_pass (1 bit)• 1:pass• 0:fail or not checked, align with EOP[1] is source_et_pass (1 bit): refer to 5G LDPC Intel FPGA IP User Guide, align withSOP[7:2] is source_iter (6 bits): refer to 5G LDPC Intel FPGA IP User Guide, align withSOP.

avmm_address[25:0] Output DDR SDRAM address (Avalon memory-mapped master)

avmm_read Output DDR read request (Avalon memory-mapped master)

avmm_readdata[191:0] Input DDR read data (Avalon memory-mapped master)

avmm_readdatavalid Input DDR read data valid (Avalon memory-mapped master)

avmm_write Output DDR write request (Avalon memory-mapped master)

avmm_writedata[191:0] Output DDR write data (Avalon memory-mapped master)

avmm_waitrequest Input DDR wait request (Avalon memory-mapped master)

Table 14. Derate Matcher Signals



reset_n Input Active-low reset. Assert for at least for10 clock cycles.

i32_cfg_wrdata[31:] Input Configuration interface write data:

continued...


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• Clock cycle 0:— [31:16]: E/Qm— [15:0]: E

• Clock cycle 1:— [31:16]: codeword length, equal

to (number of cols in PCM (CodeRate Index) - 2) * Zc (LiftingFactor)

— [15:0]: codeword length,number of nulls.

• Clock cycle 2:— [30:28]: Qm index. 0: Qm = 1.

1-4: Qm = Qm index * 2 .— [27:14]: Number of nulls

• Clock cycle 3:— [27:16]: Start of nulls— [15:0]: K0

i_cfg_wren Input Configuration interface write enable.Needs four cycles to program.

o_cfg_afull Output Configuration interface almost full.

drm_sink_wren Input Sink write enable.

drm_sink_sop Input Sink SOP.

drm_sink_eop Input Sink EOP.

drm_sink_wrdata[16*LLR_W-1:0] Input Sink write data:• [LLR_W-1:0]: data seq# 0• [LLR_W*2-1:LLR_W]: data seq# 1• ...

drm_sink_aful Output Sink almost full.

drm_fifo_rden Input Source read enable.

drm_fifo_sop Output Source SOP.

drm_fifo_eop Output Source EOP.

drm_fifo_avail Output Source available. When de-asserted,do not assert drm_fifo_rden) .

drm_fifo_data[32*LLR_W-1:0] Output Source data:• [LLR_W-1:0]: data seq# 0• [LLR_W*2-1:LLR_W]: data seq# 1• ...

Table 15. HARQ Signals


rst_n Input Reset, active-low. Assert for at least for 10 clock cycles.

clk Input Clock, positive-edge triggered

i_param_wren Input Parameter interface write enable. Requires two cycles to program.

continued...


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i_param_wrdata[31:0] Input Parameter interface write data• Cycle 0:

— [31]: do not use HARQ— [25:0] DDR SDRAM base address

• Cycle 1— [14:0]: CB old length, num of LLRs to read from DDR and to combine

with derate matcher’s output.— [30:16]: codeword length (refer to Derate Matcher Signals).

i_drm_available Input Derate matcher data available

o_drm_rden Output Derate matcher read enable

i_drm_sop Input Derate matcher start-of-packet

i_drm_eop Input Derate matcher end-of-packet

i_drm_data[32*LLR_W-1:0] Input Derate matcher data:• [LLR_W-1:0]: data seq# 0• [LLR_W*2-1:LLR_W]: data seq# 1• ...

i_dec0_afull Input Decoder (stream 0) full, i.e. backpressure

o_dec0_wren Output Decoder (stream 0) write enable

o_dec0_sop Output Decoder (stream 0) start-of-packet

o_dec0_eop Output Decoder (stream 0) end-of-packet

o_dec0_data[32*LLR_W-1:0] Output Decoder (stream 0) data:• [LLR_W-1:0]: data seq# 0• [LLR_W*2-1:LLR_W]: data seq# 1• ...

i_dec1_afull Input Decoder (stream 1) full, i.e. backpressure

o_dec1_wren Output Decoder (stream 1) write enable

o_dec1_sop Output Decoder (stream 1) start-of-packet

o_dec1_eop Output Decoder (stream 1) end-of-packet

o_dec1_data[32*LLR_W-1:0] Output Decoder (stream 1) data:• [LLR_W-1:0]: data seq# 0• [LLR_W*2-1:LLR_W]: data seq# 1• ...

avmm_address[25:0] Output DDR address (Avalon memory-mapped master)

avmm_read Output DDR read request (Avalon memory-mapped master)

avmm_readdata[191:0] Input DDR read data (Avalon memory-mapped master)

avmm_readdatavalid Input DDR read data valid (Avalon memory-mapped master)

avmm_write Output DDR write request (Avalon memory-mapped master)

avmm_writedata[191:0] Output DDR write data (Avalon memory-mapped master)

avmm_waitrequest Input DDR wait request (Avalon memory-mapped master)


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Table 16. Decoder Signals




i_param_wren Input Parameter interface write enable.Needs two clock cycles to program.

i_param_wrdata[31:0] Input Parameter interface write data:• Clock cycle 0

— [31]: early termination disable— [29:24]: number of rows in PCM

(Code Rate Index)— [13:8]: maximum iterations— [7]: Base Graph— [6:0] number of rows in PCM

(Code Rate Index)• Clock cycle 1

— [27:25]: code rate index (CodeRate Index)

— [23:18]: Zc index (LiftingFactor)

— [16:8]: Zc (Lifting Factor)

o_param_afull Output Parameter interface almost ful.

o_fifo_afull Output HARQ interface almost full.

i_fifo_wren Input HARQ interface write enable.

i_fifo_wrsop Input HARQ interface SOP.

i_fifo_wreop Input HARQ interface EOP.

i_fifo_wrdata[32*LLR_W-1:0] Input HARQ interface data:• [LLR_W-1:0]: data seq# 0• [LLR_W*2-1:LLR_W]: data seq# 1

source_ready Input Source ready.

source_pass Output Source early termination pass.

source_iter_num Output Source number of iterations.

source_valid Output Source valid.

source_sop Output Source SOP.




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Table 17. Code Block CRC Module Signals



rstn Input Active-low reset. Assert for at least for10 clock cycles.

i_param_wren Input Parameter interface write enable.Requires two cycles to program.

i_param_wrdata[15:0] Input Parameter interface write data:• [13:0]: Kp• [14]: use CRC

sink_valid Input Sink valid.

sink_sop Input Sink SOP.

sink_eop Input Sink EOP.

sink_data[31:0] Input Sink data:• [0]: data seq# 0• [1]: data seq# 1• ...

source_valid Output Source valid.

source_sop Output Source SOP.



crc_pass Output CRC pass.

Table 18. Lifting Factor Index


– – 20 16 80 32 320 48

– – 22 17 88 33 352 49

4 2 24 18 96 34 384 50

5 3 26 19 104 35 – –

6 4 28 20 112 36 – –

7 5 30 21 120 37 – –

8 6 32 22 128 38 – –

9 7 36 23 144 39 – –

10 8 40 24 160 40 – –

11 9 44 25 176 41 – –

12 10 48 26 192 42 – –

13 11 52 27 208 43 – –

14 12 56 28 224 44 – –

continued...


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15 13 60 29 240 45 – –

16 14 64 30 256 46 – –

18 15 72 31 288 47 – –

Table 19. Code Rate Index

Code RateIndex

Code Rate Base Graph 1 Base Graph 2


Matrix


Matrix


Matrix


Matrix

000 1/5 NA NA 42 52

001 1/3 46 68 22 32

010 2/5 35 57 17 27

011 1/2 24 46 12 22

100 2/3 13 35 7 17

101 22/30 (~3/4) 10 32 NA NA

110 22/27 (~5/6) 7 29 NA NA

111 22/25 (~8/9) 5 27 NA NA

4.3. Avalon Streaming Interfaces in DSP Intel FPGA IP

Avalon streaming interfaces define a standard, flexible, and modular protocol for datatransfers from a source interface to a sink interface.

The input interface is an Avalon streaming sink and the output interface is an Avalonstreaming source. The Avalon streaming interface supports packet transfers withpackets interleaved across multiple channels.

Avalon streaming interface signals can describe traditional streaming interfacessupporting a single stream of data without knowledge of channels or packetboundaries. Such interfaces typically contain data, ready, and valid signals. Avalonstreaming interfaces can also support more complex protocols for burst and packettransfers with packets interleaved across multiple channels. The Avalon streaminginterface inherently synchronizes multichannel designs, which allows you to achieveefficient, time-multiplexed implementations without having to implement complexcontrol logic.

Avalon streaming interfaces support backpressure, which is a flow control mechanismwhere a sink can signal to a source to stop sending data. The sink typically usesbackpressure to stop the flow of data when its FIFO buffers are full or when it hascongestion on its output.

Related Information

Avalon Interface Specifications


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http://www.altera.com/literature/manual/mnl_avalon_spec.pdf


5. Document Revision History for the 5G LDPC-V IntelFPGA IP User Guide

Date IP Version Intel Quartus Prime SoftwareVersion

Changes

2019.09.02 0.1.0 19.2 Corrected 5G LDPC-V blockdiagram.

2019.08.30 0.1.0 19.2 Initial release.

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