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8086
Software & Hardware
Architecture
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INTRODUCTION
It is a multipurpose programmable clock
drive register based integrated electronic device,
that reads binary instructions from a storage
device called memory as input & process the
data according to those instructions and provides
results as output. It has decision making
capability & it do operations in micro seconds.
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Topics to be covered
1. Software Architecture of the INTEL 8086.
2. Hardware Architecture of INTEL 8086.
3. 8086 Programming and program development.
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Software architecture of the INTEL
8086
� Memory segmentation and addressing
� Block diagram of 8086
� Address space & Data organization
� Data Types
� Registers
� Stack
� I/O space
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Hardware Architecture of INTEL 8086
� Pin Diagram and Pin Details
� min/max mode
� Coprocessor and Multiprocessor configuration
� Hardware organization of address space
� Control signals
� I/O interfaces
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8086 programming and program
development.
� Assembly Language Programming.
� Instruction Set.
� Assembler Directives.
� Programming Exercises.
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Software Architecture
of
INTEL 8086
Microprocessor & Microcontroller 7
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Features Features
� It is a 16-bit μp.
� 8086 has a 20 bit address bus can access up to 220
memory locations (1 MB).
� It can support up to 64K I/O ports.
� It provides 14, 16 -bit registers.
� Word size is 16 bits.
� It has multiplexed address and data bus AD0-AD15 and A16 – A19.
� It requires single phase clock with 33% duty cycle to provide internal timing.
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� 8086 is designed to operate in two modes, Minimum
and Maximum.
� It can prefetches up to 6 instruction bytes from
memory and queues them in order to speed up
instruction execution.
� It requires +5V power supply.
� A 40 pin dual in line package.
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Intel 8086 Internal ArchitectureIntel 8086 Internal Architecture
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Internal architecture of 8086Internal architecture of 8086
• 8086 has two blocks BIU and EU.
• The BIU handles all transactions of data and addresses on the buses for EU.
• The BIU performs all bus operations such as instructionfetching, reading and writing operands for memory andcalculating the addresses of the memory operands. Theinstruction bytes are transferred to the instructionqueue.
• EU executes instructions from the instruction system byte queue.
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• Both units operate asynchronously to give the 8086 an overlapping instruction fetch and execution mechanism which is called as Pipelining. This results in efficient use of the system bus and system performance.
• BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder.
• EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag register.
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EXECUTION UNITEXECUTION UNIT
• Decodes instructions fetched by the BIU
• Generate control signals,
• Executes instructions.
The main parts are:
• Control Circuitry
• Instruction decoder
• ALU
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EXECUTION UNIT – General Purpose RegistersEXECUTION UNIT – General Purpose Registers
Register PurposeAX Word multiply, word divide, word I /O
AL Byte multiply, byte divide, byte I/O, decimal arithmetic
AH Byte multiply, byte divide
BX Store address information
CX String operation, loops
CL Variable shift and rotate
DX Word multiply, word divide, indirect I/O(Used to hold I/O address during I/O instructions. If the result is more than 16-bits, the lower order 16-bits are stored in accumulator and higher order 16-bits are stored in DX register)
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Pointer And Index RegistersPointer And Index Registers
• used to keep offset addresses.
• Used in various forms of memory addressing.
• In the case of SP and BP the default reference to form a physical address is the Stack Segment (SS-will be discussed under the BIU)
• The index registers (SI & DI) and the BX generally default to the Data segment register (DS).
SP: Stack pointer– Used with SS to access the stack segment
BP: Base Pointer– Primarily used to access data on the stack– Can be used to access data in other segments
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• SI: Source Index register
– is required for some string operations
– When string operations are performed, the SI register points to memory locations in the data segment which is addressed by the DS register. Thus, SI is associated with the DS in string operations.
• DI: Destination Index register
– is also required for some string operations.
– When string operations are performed, the DI register points to memory locations in the data segment which is addressed by the ES register. Thus, DI is associated with the ES in string 16
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EXECUTION UNIT – Flag RegisterEXECUTION UNIT – Flag Register
Flag Purpose
Carry (CF) Holds the carry after addition or the borrow after subtraction.
Also indicates some error conditions, as dictated by some programs and procedures .
Parity (PF) PF=0;odd parity, PF=1;even parity.
Auxiliary (AF) Holds the carry (half – carry) after addition or borrow after
subtraction between bit positions 3 and 4 of the result (for example, in BCD addition or subtraction.)
Zero (ZF) Shows the result of the arithmetic or logic operation.
Z=1; result is zero. Z=0; The result is 0
Sign (SF) Holds the sign of the result after an arithmetic/logic instruction
execution. S=1; negative, S=017
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Flag Purpose
Trap (TF)
A control flag.
Enables the trapping through an on-chip debugging feature.
Interrupt (IF)
A control flag.
Controls the operation of the INTR (interrupt request)I=0; INTR pin disabled. I=1; INTR pin enabled.
Direction (DF)
A control flag.
It selects either the increment or decrement mode for DI and /or SI registers during the string instructions.
Overflow (OF)
Overflow occurs when signed numbers are added or
subtracted. An overflow indicates the result has exceeded the capacity of the Machine
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Execution unit – Flag RegisterExecution unit – Flag Register
• Six of the flags are status indicators reflecting properties of the last arithmetic or logical instruction.
• For example, if register AL = 7Fh and the instruction ADD AL,1 is executed then the following happen
AL = 80h
CF = 0; there is no carry out of bit 7
PF = 0; 80h has an odd number of ones
AF = 1; there is a carry out of bit 3 into bit 4
ZF = 0; the result is not zero
SF = 1; bit seven is one
OF = 1; the sign bit has changed
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BUS INTERFACE UNIT (BIU)BUS INTERFACE UNIT (BIU)
Contains
• 6-byte Instruction Queue (Q)
• The Segment Registers (CS, DS, ES, SS).
• The Instruction Pointer (IP).
• The Address Summing block (Σ)
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Segmented
Memory
Segmented
Memory
Code segment (64KB)
Data segment (64KB)
Extra segment (64KB)
Stack segment (64KB)
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1 MB
�The memory in an 8086/88 based system is organized as segmented memory.
�The CPU 8086 is able to address 1Mbyte of memory.
�The Complete physically available memory may be divided into a number of logical segments.
00000
FFFFF
Physical Memory
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• The 4 segments are Code, Data, Extra and Stack segments.
• A Segment is a 64kbyte block of memory.
• The 16 bit contents of the segment registers in the BIU actually point to the starting locationcular segment.
• Segments may be overlapped or non-overlapped
Advantages of Segmented memory Scheme
• Allows the memory capacity to be 1Mb although the actual addresses to be
handled are of 16 bit size.
• Allows the placing of code, data and stack portions of the same program in different parts (segments) of the m/y, for data and code protection.
• Permits a program and/or its data to be put into different areas of memory each time program is executed, i.e. provision for relocation may be done .
• The segment registers are used to allow the instruction, data or stack portion of 22
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Segment registersSegment registers
• In 8086/88 the processors have 4 segments registers
• Code Segment register (CS), Data Segment register (DS), Extra Segment register (ES) and Stack Segment (SS) register.
• All are 16 bit registers.
• Each of the Segment registers store the upper 16 bit address of the starting address of the corresponding segments.
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34BA
44EB
54EB
695E
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CSR
DSR
ESR
SSR
Segment Registers
BIU
CODE (64k)
DATA (64K)
EXTRA (64K)
STACK (64K)
1 MB
00000
34BA0
44B9F
44EB0
54EAF54EB0
64EAF
695E0
795DF
Each segment register store the upper 16 bit of the starting address of the segments
MEMORY
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Segment and Address register
combination
Segment and Address register
combination
• CS:IP
• SS:SP SS:BP
• DS:BX DS:SI
• DS:DI (for other than string operations)
• ES:DI (for string operations)
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Block diagram of 8086
RCET Microprocessor & Microcontroller 28
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Block diagram of 8086
RCET Microprocessor & Microcontroller 29
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General Purpose Registers
• Normally used for storing temporary results
• Each of the registers is 16 bits wide (AX, BX, CX, DX)
• Can be accessed as either 16 or 8 bits AX, AH, AL
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AX - the AccumulatorBX - the Base RegisterCX - the Count RegisterDX - the Data Register
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General Purpose Registers
• AX
– Accumulator Register
– Preferred register to use in arithmetic, logic and data transfer instructions because it generates the shortest Machine Language Code
– Must be used in multiplication and division operations
– Must also be used in I/O operations
• BX
– Base Register
– Also serves as an address register
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General Purpose Registers
• CX
– Count register
– Used as a loop counter
– Used in shift and rotate operations
• DX
– Data register
– Used in multiplication and division
– Also used in I/O operations
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Pointer and Index Registers
• All 16 bits wide, L/H bytes are not accessible
• Used as memory pointers
– Example: MOV AH, [SI]
• Move the byte stored in memory location whose address is contained in register SI to register AH
• IP is not under direct control of the programmer
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Flag Register
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Carry
Parity
Auxiliary Carry
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags
3 are control flag
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8086 Programmer’s Model
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ES
CS
SS
DS
IP
AH
BH
CH
DH
AL
BL
CL
DL
SP
BP
SI
DI
FLAGS
AX
BX
CX
DX
Extra Segment
Code Segment
Stack Segment
Data Segment
Instruction Pointer
Accumulator
Base Register
Count Register
Data Register
Stack Pointer
Base Pointer
Source Index Register
Destination Index Register
BIU registers(20 bit adder)
EU registers
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The Stack
• The stack is used for temporary storage of information
such as data or addresses.
• When a CALL is executed, the 8086 automatically PUSHes
the current value of CS and IP onto the stack.
• Other registers can also be pushed
• Before return from the subroutine, POP instructions can
be used to pop values back from the stack into the
corresponding registers.
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The Stack
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Hardware Architecture
of
INTEL 8086
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Hardware Architecture of INTEL 8086
� Pin Diagram and Pin Details
� min/max mode
� Hardware organization of address space
� Control signals
� Coprocessor and Multiprocessor configuration
� I/O interfaces
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INTEL 8086 - Pin Diagram
Microprocessor & Microcontroller 40
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INTEL 8086 - Pin Details
Microprocessor & Microcontroller 41
Ground
Clock
Duty cycle: 33%
Power Supply
5V ± 10%
Reset
Registers, seg
regs, flags
CS: FFFFH, IP:
0000H
If high for
minimum 4
clks
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INTEL 8086 - Pin Details
Microprocessor & Microcontroller 42
Address/Data Bus:
Contains address
bits A15-A0 when ALE
is 1 & data bits D15 –
D0 when ALE is 0.
Address Latch Enable:
When high,
multiplexed
address/data bus
contains address
information.
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INTEL 8086 - Pin Details
Microprocessor & Microcontroller 43
INTERRUPT
Non - maskable
interrupt
Interrupt request
Interrupt
acknowledge
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INTEL 8086 - Pin Details
Microprocessor & Microcontroller 44
Direct
Memory
Access
Hold
acknowledge
Hold
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INTEL 8086 - Pin Details
Microprocessor & Microcontroller 45
Address/Status Bus
Address bits A19 –
A16 & Status bits S6
– S3
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INTEL 8086 - Pin Details
Microprocessor & Microcontroller 46
Bus High Enable/S7
Enables most
significant data bits
D15 – D8 during read
or write operation.
S7: Always 1.
BHE#, A0:
0,0: Whole word (16-bits)
0,1: High byte to/from odd address
1,0: Low byte to/from even address
1,1: No selection
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INTEL 8086 - Pin Details
Microprocessor & Microcontroller 47
Min/Max mode
Minimum Mode: +5V
Maximum Mode: 0V
Minimum Mode Pins
Maximum Mode
Pins
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Microprocessor & Microcontroller
Minimum Mode- Pin Details
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Read Signal
Write Signal
Memory or I/0
Data Bus Enable
Data
Transmit/Receive
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Maximum Mode - Pin Details
Microprocessor & Microcontroller 49
Status Signal
Inputs to 8288 to
generate eliminated
signals due to max
mode.
S2 S1 S0
000: INTA
001: read I/O port
010: write I/O port
011: halt
100: code access
101: read memory
110: write memory
111: none -passive
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Maximum Mode - Pin Details
Microprocessor & Microcontroller 50
DMA
Request/Grant
Lock Output
Lock Output
Used to lock peripherals
off the system
Activated by using the
LOCK: prefix on any
instruction
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Maximum Mode - Pin Details
Microprocessor & Microcontroller 51
Queue Status
Used by numeric
coprocessor (8087)
QS1 QS0
00: Queue is idle
01: First byte of opcode
10: Queue is empty
11: Subsequent byte of
opcode
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Minimum Mode 8086 System
Microprocessor & Microcontroller 52
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Maximum Mode 8086 System
Microprocessor & Microcontroller 53
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Flow Control Instructions - Cont.• Single-flag jumps
– JS jump if sign negative
– JNS jump if nonnegative sign
– JP/JPE jump if parity even
– JNP/JPO jump if parity odd
• Jump based on CX
– JCXZ
• Loop Instructions
– Loop
– Loopnz/Loopne
– Loopz/Loope
• All jump instructions have no effect on the flags.
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Branching Structures: IF-Then
• Example:
If AX < 0 Then
Replace AX by –AX
ENDIF
; if AX < 0
CMP AX, 0
JNL END_IF
;then
NEG AX
END_IF:
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IF-Then-Else
• Example:If AL <= BL Then
Display character in ALElse
Display character in BLENDIF
MOV AH, 2; if AL<=BL
CMP AL, BLJNBE ELSE_
;thenMOV DL, ALJMP DISPLAY
ELSE_:MOV DL, BL
DISPLAY:INT 21H
END_IF:
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CASE
• Example:
CASE AX<0: put –1 in BX=0: put 0 in BX>0: put 1 in BX
END_CASE
; case AXCMP AX, 0JL NEGATIVEJE ZEROJG POSITIVE
NEGATIVE: MOV BX, -1JMP END_CASE
ZERO: MOV BX, 0JMP END_CASE
POSITIVE: MOV BX, 1END_CASE:
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CASE – Cont.
• Example:
CASE AL1,3: display ‘o’2,4: display ‘e’
END_CASE; case AL
CMP AL, 1 ; 1, 3:JE ODDCMP AL, 3JE ODDCMP AL, 2 ; 2, 4:JE EVENCMP AL, 4JE EVENJMP END_CASE
ODD: MOV DL, ‘o’JMP DISPLAY
EVEN: MOV DL, ‘e’DISPLAY: MOV AH, 2
INT 21HEND_CASE:
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Loop Instructions
• Loop Next
– Dec Cx
– If CX<>0 JMP Next
• Loopz/loope Next
– Dec Cx
– If (CX<>0) AND (ZF=1) JMP Next
• Loopnz/loopne Next
– Dec Cx
– If (CX<>0) AND (ZF=0) JMP Next
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FOR LOOP
• Example:
For 80 times DO
Display ‘*’
END_IFMOV CX, 80
MOV AH, 2
MOV DL, ‘*’
Next: INT 21H
Loop Next