8086 SOFTWARE ASPECTS OBJECTIVE Draw the Architecture of 8086 Explain the various instructions and the addressing modes corresponds to them Brief out the assembler directives and their functions and write ALP with appropriate directives FEATURES : The 8086 is a 16-bit microprocessor chip designed by Intel and introduced on the market in 1978, which gave rise to the x86 architecture. Intel 8088, released in 1979, was essentially the same chip, but with an external 8-bit data bus (allowing the use of cheaper and fewer supporting logic chips), and is notable as the processor used in the original IBM PC. The first multi-chip 16-bit microprocessor was the National Semiconductor IMP-16, introduced in early 1973. An 8-bit version of the chipset was introduced in 1974 as the IMP-8. During the same year, National introduced the first 16-bit single-chip microprocessor, the National Semiconductor PACE, which was later followed by an NMOS version, the INS8900. Intel followed a different path, having no minicomputers to emulate, and instead "upsized" their 8080 design into the 16-bit Intel 8086, the first member of the x86 family which powers most modern PC type computers. Intel introduced the 8086 as a cost effective way of porting software from the 8080 lines, and succeeded in winning much business on that premise. The 8088, a version of the 8086 that used an external 8-bit data bus, was the microprocessor in the first IBM PC, the model 5150. Following up their 8086 and 8088, Intel released the 80186, 80286 and, in 1985, the 32-bit 80386, cementing their PC market dominance with the processor family's backwards compatibility. The integrated microprocessor memory management unit (MMU) was developed by Childs et al. of Intel, and awarded US patent number 4,442,484.
Transcript
8086 SOFTWARE ASPECTS OBJECTIVE Draw the Architecture of 8086 Explain the various instructions and the addressing modes corresponds to them Brief out the assembler directives and their functions and write ALP with appropriate directives FEATURES : The 8086 is a 16-bit microprocessor chip designed by Intel and introduced on the market in 1978, which gave rise to the x86 architecture.
� Intel 8088, released in 1979, was essentially the same chip, but with an external 8-bit data bus (allowing the use of cheaper and fewer supporting logic chips), and is notable as the processor used in the original IBM PC.
� The first multi-chip 16-bit microprocessor was the National Semiconductor IMP-16,
introduced in early 1973. � An 8-bit version of the chipset was introduced in 1974 as the IMP-8. During the same year,
National introduced the first 16-bit single-chip microprocessor, the National Semiconductor PACE, which was later followed by an NMOS version, the INS8900.
� Intel followed a different path, having no minicomputers to emulate, and instead "upsized"
their 8080 design into the 16-bit Intel 8086, the first member of the x86 family which powers most modern PC type computers.
� Intel introduced the 8086 as a cost effective way of porting software from the 8080 lines,
and succeeded in winning much business on that premise. � The 8088, a version of the 8086 that used an external 8-bit data bus, was the
microprocessor in the first IBM PC, the model 5150. � Following up their 8086 and 8088, Intel released the 80186, 80286 and, in 1985, the 32-bit
80386, cementing their PC market dominance with the processor family's backwards compatibility.
� The integrated microprocessor memory management unit (MMU) was developed by
Childs et al. of Intel, and awarded US patent number 4,442,484.
PIN DIAGRAM
AD15±AD0
ADDRESS DATA BUS: These lines constitute the time multiplexed memory/IO address and data bus. ALE
Address Latch Enable. A HIGH on this line causes the lower order 16bit address bus to be latched that stores the addresses and then, the lower order 16bit of the address bus can be used as data bus. READY
READY is the acknowledgement from the addressed memory or I/O device that it will complete the data transfer. INTR
INTERRUPT REQUEST: is a level triggered input which is sampled during the last clock cycle of each instruction to determine if the processor should enter into an interrupt acknowledge operation. A subroutine is vectored to via an interrupt vector lookup table located in system memory. It can be internally masked by software resetting the interrupt enable bit. INTR is internally synchronized. This signal is active HIGH.
INTA Interrupt Acknowledge from the MP
NMI NON-MASKABLE INTERRUPT: an edge triggered input which causes
an interrupt request to the MP. A subroutine is vectored to via an interrupt vector lookup table located in system memory. NMI is not maskable internally by software. RESET:
causes the processor to immediately terminate its present activity. The signal must be active HIGH for at least four clock cycles. It restarts execution MN/MX
MINIMUM/MAXIMUM: indicates what mode the processor is to operate in. The two modes are discussed in the following sections. M/IO :
Differentiate between the Memory and I/O operation. A LOW on this pin indicated I/O operation and a HIGH indicated a Memory Operation HOLD :
The 8086 has a pin called HOLD. This pin is used by external devices to gain control of the busses. HLDA :
When the HOLD signal is activated by an external device, the 8086 stops executing instructions and stops using the busses. This would allow external devices to control the information on the 8086 MINIMUM AND MAXIMUM MODES of operation MN/MX Minimum mode The 8086 processor works in a single processor environment.
All control signals for memory and I/O are generated by the microprocessor. Maximum mode is designed to be used when a coprocessor exists in the system. 8086 works in a multiprocessor environment. Control signals for memory and
I/O are generated by an external BUS Controller 8086 CPU ARCHITECTURE
The microprocessors functions as the CPU in the stored program model of the digital computer. Its job is to generate all system timing signals and synchronize the transfer of data between memory, I/O, and itself. It accomplishes this task via the three-bus system architecture previously discussed. The microprocessor also has a S/W function. It must recognize, decode, and execute program instructions fetched from the memory unit. This requires an Arithmetic-Logic Unit (ALU) within the CPU to perform arithmetic and logical (AND, OR, NOT, compare, etc) functions. The 8086 CPU is organized as two separate processors, called the Bus Interface Unit (BIU) and the Execution Unit (EU).
� The BIU provides H/W functions, including generation of the memory and I/O addresses for the transfer of data between the outside world -outside the CPU, that is- and the EU.
� The EU receives program instruction codes and data from the BIU, executes these instructions, and store the results in the general registers.
� By passing the data back to the BIU, data can also be stored in a memory location or written to an output device.
� The important point to note, however, is that because the EU is the same for each processor, the programming instructions are exactly the same for each. Programs written for the 8086 can be run on the 8088 without any changes
BUS INTERFACE UNIT:
It provides a full 16 bit bidirectional data bus and 20 bit address bus.
The bus interface unit is responsible for performing all external bus operations.
Specifically it has the following functions:
Instruction fetch, Instruction queuing, Operand fetch and storage, Address relocation and Bus control.
The BIU uses a mechanism known as an instruction stream queue to implement a pipeline architecture.
This queue permits prefetch of up to six bytes of instruction code. When ever the queue of the BIU is not full, it has room for at least two more bytes and at the same time the EU is not requesting it to read or write operands from memory, the BIU is free to look ahead in the program by prefetching the next sequential instruction.
These prefetching instructions are held in its FIFO queue. With its 16 bit data bus, the BIU fetches two instruction bytes in a single memory cycle.
After a byte is loaded at the input end of the queue, it automatically shifts up through the FIFO to the empty location nearest the output.
The EU accesses the queue from the output end. It reads one instruction byte after the other from the output of the queue. If the queue is full and the EU is not requesting access to operand in memory.
These intervals of no bus activity, which may occur between bus cycles are known as Idle state.
If the BIU is already in the process of fetching an instruction when the EU request it to read or write operands from memory or I/O, the BIU first completes the instruction fetch bus cycle before initiating the operand read / write cycle.
The BIU also contains a dedicated adder which is used to generate the 20bit physical address that is output on the address bus. This address is formed by adding an appended 16 bit segment address and a 16 bit offset address.
For example: The physical address of the next instruction to be fetched is formed by combining the current contents of the code segment CS register and the current contents of the instruction pointer IP register.
The BIU is also responsible for generating bus control signals such as those for memory read or write and I/O read or write.
EXECUTION UNIT
The Execution unit is responsible for decoding and executing all instructions.
The EU extracts instructions from the top of the queue in the BIU, decodes them, generates operands if necessary, passes them to the BIU and requests it to perform the read or write bys cycles to memory or I/O and perform the operation specified by the instruction on the operands.
During the execution of the instruction, the EU tests the status and control flags and updates them based on the results of executing the instruction.
If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted to top of the queue.
When the EU executes a branch or jump instruction, it transfers control to a location corresponding to another set of sequential instructions.
Whenever this happens, the BIU automatically resets the queue and then begins to fetch instructions from this new location to refill the queue.
FETCH AND EXECUTE
Although the 8086/88 still functions as a stored program computer, organization of the CPU into a separate BIU and EU allows the fetch and execute cycles to overlap. To see this, consider what happens when the 8086 or 8088 is first started. 1. The BIU outputs the contents of the instruction pointer register (IP) onto the address bus, causing the selected byte or word to be read into the BIU. 2. Register IP is incremented by 1 to prepare for the next instruction fetch. 3. Once inside the BIU,the instruction is passed to the queue. This is a first-in, first-out storage register sometimes likened to a "pipeline". 4. Assuming that the queue is initially empty, the EU immediately draws this instruction from the queue and begins execution. 5. While the EU is executing this instruction, the BIU proceeds to fetch a new instruction. Depending on the execution time of the first instruction, the BIU may fill the queue with several new instructions before the EU is ready to draw its next instruction.
The BIU is programmed to fetch a new instruction whenever the queue has room for one (with the 8088) or two (with the 8086) additional bytes.The advantage of this pipelined architecture is that the EU can execute instructions almost continually instead of having to wait for the BIU to fetch a new instruction.
GENERAL BUS OPERATIONS:
The 8086 has a combined address and data bus commonly referred as a time multiplexed address and data bus.
The main reason behind multiplexing address and data over the same pins is the maximum utilisation of processor pins and it facilitates the use of 40 pin standard DIP package.
The bus can be demultiplexed using a few latches and transreceivers, when ever required.
Basically, all the processor bus cycles consist of at least four clock cycles. These are referred to as T1, T2, T3, T4. The address is transmitted by the processor during T1. It is present on the bus only for one cycle.
The negative edge of this ALE pulse is used to separate the address and the data or status information. In maximum mode, the status lines S0, S1 and S2 are used to indicate the type of operation.
Status bits S3 to S7 are multiplexed with higher order address bits and the BHE signal. Address is valid during T1 while status bits S3 to S7 are valid during T2 through T4.
Maximum mode
In the maximum mode, the 8086 is operated by strapping the MN/MX pin to ground.
In this mode, the processor derives the status signal S2, S1, S0. Another chip called bus controller derives the control signal using this status information .
In the maximum mode, there may be more than one microprocessor in the system configuration.
Minimum mode
In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by strapping its MN/MX pin to logic 1.
In this mode, all the control signals are given out by the microprocessor chip itself.
There is a single microprocessor in the minimum mode system.
In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by strapping its MN/MX pin to logic 1.
In this mode, all the control signals are given out by the microprocessor chip itself.There is a single microprocessor in the minimum mode system.
The remaining components in the system are latches, transreceivers, clock generator, memory and I/O devices. Some type of chip selection logic may be required for selecting memory or I/O devices, depending upon the address map of the system.
Latches are generally buffered output D-type flip-flops like 74LS373 or 8282. They are used for separating the valid address from the multiplexed address/data signals and are controlled by the ALE signal generated by 8086.
Transreceivers are the bidirectional buffers and some times they are called as data amplifiers. They are required to separate the valid data from the time multiplexed address/data signals.
They are controlled by two signals namely, DEN and DT/R.
The DEN signal indicates the direction of data, i.e. from or to the processor. The system contains memory for the monitor and users program storage.
Usually, EPROM are used for monitor storage, while RAM for users program storage. A system may contain I/O devices.
PROGRAMING MODEL
� As a programmer of the 8086 or 8088 you must become familiar with the various registers in the EU and BIU. The data group consists of the accumulator and the BX, CX, and DX registers
� The data registers are normally used for storing temporary results that will be acted on by subsequent instructions.
� The pointer and index group are all 16-bit registers (you cannot access the low or high bytes alone). These registers are used as memory pointers.
Register IP could be considered in the previous group, but this register has only one function -to point to the next instruction to be fetched to the BIU. Register IP is physically part of the BIU and not under direct control of the programmer as are the other pointer registers.
� Six of the flags are status indicators, reflecting properties of the result of the last arithmetic or logical instructions.
� Three of the flags can be set or reset directly by the programmer and are used to control the operation of the processor. These are TF, IF, and DF.
� The final group of registers is called the segment group. These registers are used by the BIU to determine the memory address output by the CPU when it is reading or writing from the memory unit. To fully understand these registers, we must first study the way the 8086/88 divides its memory into segments ll general registers of the 8086 microprocessor can be used for arithmetic and logic operations. The general registers are:
Accumulator register consists of 2 8-bit registers AL and AH, which can be
combined together and used as a 16-bit register AX. AL in this case contains the low-order byte of the word, and AH contains the high-order byte. Accumulator can be used for I/O operations and string manipulation.
Base register consists of 2 8-bit registers BL and BH, which can be combined
together and used as a 16-bit register BX. BL in this case contains the low-order byte of the word, and BH contains the high-order byte. BX register usually contains a data pointer used for based, based indexed or register indirect
addressing. Count register
consists of 2 8-bit registers CL and CH, which can be combined together and used as a 16-bit register CX. When combined, CL register contains the low-order byte of the word, and CH contains the high-order byte. Count register can be used as a counter in string manipulation and shift/rotate instructions.
Data register consists of 2 8-bit registers DL and DH, which can be combined
together and used as a 16-bit register DX. When combined, DL register contains the low-order byte of the word, and DH contains the high-order byte. Data register can be used as a port number in I/O operations. In integer 32-bit multiply and divide instruction the DX register contains high-order word of the initial or resulting number. The following registers are both general and index registers:
Stack Pointer (SP) is a 16-bit register pointing to program stack.
Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usually used for based, based indexed or register indirect addressing.
Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and
register indirect addressing, as well as a source data address in string manipulation instructions.
Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed
and register indirect addressing, as well as a destination data address in string manipulation instructions. Other registers:
Instruction Pointer (IP) is a 16-bit register. Flags is a 16-bit register containing 9 1-bit flags:
� Overflow Flag (OF) - set if the result is too large positive number, or is too small negative number to fit into destination operand.
� Direction Flag (DF) - if set then string manipulation instructions will autodecrement index registers. If cleared then the index registers will be autoincremented.
� Interrupt-enable Flag (IF) - setting this bit enables maskable interrupts. � Single-step Flag (TF) - if set then single-step interrupt will occur after the
next instruction. � Sign Flag (SF) - set if the most significant bit of the result is set. � Zero Flag (ZF) - set if the result is zero.
� Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bits 0-3 in the AL register.
� Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of the result is even.
� Carry Flag (CF) - set if there was a carry from or borrow to the most significant bit during last result calculation. Memories of 8086
� Program, data and stack memories occupy the same memory space. � The total addressable memory size is 1MB KB. As the most of the processor
instructions use 16-bit pointers the processor can effectively address only 64 KB of memory.
� To access memory outside of 64 KB the CPU uses special segment registers to specify where the code, stack and data 64 KB segments are positioned within 1 MB of memory (see the "Registers" section below).
16-bit pointers and data are stored as: address: low-order byte address+1: high-order byte
32-bit addresses are stored in "segment:offset" format as: address: low-order byte of segment address+1: high-order byte of segment address+2: low-order byte of offset address+3: high-order byte of offset
Physical memory address pointed by segment:offset pair is calculated as: address = (<segment> * 16) + <offset> Program memory
� program can be located anywhere in memory. � Jump and call instructions can be used for short jumps within currently
selected 64 KB code segment, as well as for far jumps anywhere within 1 MB of memory.
� All conditional jump instructions can be used to jump within approximately +127 - -127 bytes from current instruction. Data memory
• The processor can access data in any one out of 4 available segments, which limits the size of accessible memory to 256 KB (if all four segments point to different 64 KB blocks).
• Accessing data from the Data, Code, Stack or Extra segments can be usually done by prefixing instructions with the DS:, CS:, SS: or ES: (some registers and instructions by default may use the ES or SS segments instead of DS segment).
• Word data can be located at odd or even byte boundaries. • The processor uses two memory accesses to read 16-bit word located at
odd byte boundaries. Reading word data from even byte boundaries requires only one memory access. Stack memory can be placed anywhere in memory. The stack can be located at odd memory addresses, but it is not recommended for performance reasons (see "Data Memory" above). Reserved locations:
� 0000h - 03FFh are reserved for interrupt vectors. Each interrupt vector is a 32-bit pointer in format segment:offset.
� FFFF0h - FFFFFh - after RESET the processor always starts program execution at the FFFF0h address. MEMORY MAP
Still another view of the 8086/88 memory space could be as 16 64K-byte blocks beginning at hex address 000000h and ending at address 0FFFFFh. This division into 64K-byte blocks is an arbitrary but convenient choice. This is because the most significant hex digit increments by 1 with each additional block. That is, address 20000h is 65.536 bytes higher in memory than address 10000h. Be sure to note that five hex digits are required to represent a memory address.
The diagram is called a memory map. This is because, like a road map, it is a guide showing how the system memory is allocated.
low-oder hex digit must be 0. Also note that the four segments need not be defined separately. Indeed, it is allowable for all four segments to completely overlap (CS = DS = ES = SS). LOGICAL AND PHYSICAL ADDRESS Addresses within a segment can range from address 00000h to address 0FFFFh. This corresponds to the 64K-byte length of the segment. An address within a segment is called an offset or logical address. A logical address gives the displacement from the address base of the segment to the desired location within it, as opposed to its "real" address, which maps directly anywhere into the 1 MB memory space. This "real" address is called the physical address. What is the difference between the physical and the logical address?
The physical address is 20 bits long and corresponds to the actual binary code output by the BIU on the address bus lines. The logical address is an offset from location 0 of a given segment. When two segments overlap it is certainly possible for two different logical addresses to map to the same physical address. This can have disastrous results when the data begins to overwrite the subroutine stack area, or vice versa. For this reason you must be very careful when segments are allowed to overlap. You should also be careful when writing addresses on paper to do so clearly. To specify the
logical address XXXX in the stack segment, use the convention SS:XXXX, which is equal to [SS] * 16 + XXXX. ADDRESSING MODES OF 8086: The 8086 has 12 basic addressing modes(AM) and can be classified into 5 groups
I. Addressing modes for accessing immediate & register data II. Addressing modes for accessing data in memory III. Addressing modes for accessing I/O ports IV. Relative Addressing modes V. Implied Addressing modes
Addressing modes for accessing Immediate & Register data 1.Register AM
In this mode the source operand,destination operand or both are to be contained in the 8086 register.
eg:- MOV DX,CX MOV CL,DL
2.Immediate AM In this mode a 8 or 16 bit data can be specified as part of the instruction
eg:- MOV CL,03H MOV DX,0502H
Addressing modes for data in memory (Memory mode) 3.Direct AM
In this mode the 16 bit effective address (EA) is taken directly from the displacement field of the instruction.This EA or displacement is the distance of the memory location from the current value in the data segment (DS) register in which the data are stored.
The BIU shifts the [DS] 4 times to left & adds the EA to generate the 20 bit physical address.
eg:- MOV CX,START MOV START,BL START can be defined as an address by using the assembler DB(Define Byte) or
DW(Define Word) pseudoinstructions.
Suppose if START=0040(16) &[DS]=3050(16) then 3 0 5 0 SHIFT LEFT 0 0 4 0 (EA) 3 0 5 0 4 20 BIT PHYSICAL
ADDRESS 4.Register Indirect AM
In this mode the EA is specified in either a pointer register or an index register.The pointer register can be either base register(BX) or base pointer(BP) and Index register can either be Source index(SI) or Destination index(DI) register
eg:- MOV [DI],BX The instruction moves the 16 bit content of BX into a memory location offset by
the value of EA (EA is specified in DI) from the current contents in DS. If [DS]=5004(16)
the contents of BX (2456) is moved into memory locations 50060(16) & 50061(16)
5.Based AM In this mode EA is obtained by adding a displacement (signed 8 bit or unsigned
16 bit) value to the contents of BX or BP.The segment registers used are DS & SS. When Memory is accessed,the 20 bit physical address is computed from BX and
DS.On the other hand,when the stack is accessed,the 20 bit physical address is computed from BP and SS.
eg:- MOV AL,START[BX] or MOV AL,[BX+START] Where START=02H(8 bit displacement),BX=2000H Now the 20 bit Physical address is computed from DS and EA If [DS]=5004(16),then 2000H BX 5 0 0 4 02H Displacement 2 0 0 2 EA 2002H EA 5 2 0 4 0 20 bit Physical Address Here the source operand is in based Addressing Mode.EA is obtained by adding
the value of START and [BX].The 20 bit physical address is produced from DS and EA.The 8 bit content of this memory location is moved to AL register. Therefore the contents of the memory location 52042 is moved in to AL register. 6.Indexed AM
In this mode,the EA is calculated by adding the unsigned 16 bit or signed extended 8 bit displacement and the contents of SI or DI.
eg:- MOV BH,START[SI] moves the contents of the 20 bit address computed from the displacement
START,SI and DS into BH register.The 8 bit displacement is provided by the programmer using the assembler pseudoindtruction such as EQU.For 16 bit displacement,the EU adds this to SI to determine EA.On the other hand,for 8 bit displacement the EU sign extends it to 16 bits and then adds to SI for determining EA. 7.Based Indexed AM
In this mode,the EA is computed by adding a base register(BX or BP),an index register(SI or DI),and a displacement(unsigned 16 bit or sign extended 8 bit) eg:- MOV ALPHA[SI][BX],CL If [BX]=0200H,[SI]=1000H,ALPHA=08H and [DS]=3000H 0200H [BX] 1000H [SI] 3 0 0 0
1 2 0 8 EA 3 1 2 0 8 20 bit Physical address
08H Displacement 1208H EA Based Indexed AM provides a convinient way for a subroutine to address an array allocated on a stack. 8.String AM
This mode uses index registers.The string instructions automatically assume SI to point to the first byte or word of the source operand and DI to point to the first byte or word of the destination operand.
The segment register for the source is DS and may be overridden.The segment register for the destination must be ES and cannot be overridden.
The contents af SI and DI are automatically incremented by clearing DF (Direction Flag) to 0 by CLD instruction or automatically decremented by setting DF to 1 by STD instruction.
Addressing Modes for accessing I/O ports 9.Direct AM
Here the port number is a 8 bit immediate operand.This allows fixed access to ports numbered 0 to 255.
eg:- OUT 05H,AL outputs [AL] to 8 bit port 05H 10.Indirect AM
The port number is taken from DX allowing 64K 8 bit ports or 32K 16 bit ports. eg:- IN AX,DX
If [DX]=5040,Inputs the 8 bit content of port 5040 into AL and 5041 into AH. Relative Addressing Mode 11.
In this mode,the operand is specified as a signed 8 bit displacement,relative to PC(Program Counter).
eg:- JNC START then,if carry=0,PC is loaded with current PC contents plus the 8 bit signed value of START,otherwise the next instruction is executed. Implied Addressing Mode 12.
Instructions using this mode have no operands. eg:- CLC
this clears the carry flag to zero. INSTRUCTION SET &ITS CLASSIFICATION:
The instructions of 8086 are classified into SIX groups. They are:
1. DATA TRANSFER INSTRUCTIONS 2. ARITHMETIC INSTRUCTIONS 3. BIT MANIPULATION INSTRUCTIONS 4. STRING INSTRUCTIONS 5. PROGRAM EXECUTION TRANSFER INSTRUCTIONS
6. PROCESS CONTROL INSTRUCTIONS
DATA TRANSFER INSTRUCTIONS
The DATA TRANSFER INSTRUCTIONS are those, which transfers the DATA from any one source to any one destination.The datas may be of any type. They are again classified into four groups.They are:
GENERAL – PURPOSE BYTE OR WORD TRANSFER INSTRUCTIONS
SIMPLE INPUT AND OUTPUT PORT TRANSFER INSTRUCTION
SPECIAL ADDRESS TRANSFER INSTRUCTION
FLAG TRANSFER INSTRUCTIONS
MOV PUSH POP
XCHG XLAT
IN OUT
LEA LDS LES
LAHF SAHF
PUSHF POPF
2.ARITHMETIC INSTRUCTIONS
These instructions are those which are useful to perform Arithmetic calculations, such as addition, subtraction, multiplication and division.They are again classified into four groups.They are:
ADDITION INSTRUCTIONS
SUBTRACTION INSTRUCTIONS
MULTIPLICATION INSTRUCTIONS
DIVISION INSTRUCTIONS
ADD ADC INC AAA DAA
SUB SBB DEC NEG CMP AAS DAS
MUL IMUL AAM
DIV IDIV AAD CBW CWD
3.BIT MANIPULATION INSTRUCTIONS
These instructions are used to perform Bit wise operations.
LOGICAL INSTRUCTIONS SHIFT INSTRUCTIONS
ROTATE INSTRUCTIONS
NOT AND OR
XOR TEST
SHL / SAL SHR SAR
ROL ROR RCL RCR
4. STRING INSTRUCTIONS
The string instructions function easily on blocks of memory.They are user friendly instructions, which help for easy program writing and execution. They can speed up the manipulating code.They are useful in array handling, tables and records
These instructions transfer the program control from one address to other address. ( Not in a sequence). They are again classified into four groups.They are:
UNCONDITIONAL TRANSFER
INSTRUCTIONS
CONDITIONAL TRANSFER
INSTRUCTIONS
ITERATION CONTROL
INSTRUCTIONS
INTERRUPT INSTRUCTIONS
CALL RET JMP
JA / JNBE JAE / JNB JB /
JNAE JBE / JNA JC
JE / JZ JG /
JNLE JGE / JNL JL /
JNGE
JLE / JNG JNC
JNE / JNZ JNO JNP / JPO JNS JO
JP / JPE JS
LOOP LOOPE / LOOPZ
LOOPNE / LOOPNZ JCXZ
INT INTO IRET
6.PROCESS CONTROL INSTRUCTIONS
These instructions are used to change the process of the Microprocessor. They change the process with the stored information. They are again classified into Two groups.They are:
FLAG SET / CLEAR INSTRUCTIONS
EXTERNAL HARDWARE SYNCHRONIZATION INSTRUCTIONS
STC CLC CMC STD CLD STI CLI
HLT WAIT ESC
LOCK NOP
MULTIPLE CHOICE: 1.A machine cycle refers to ________________ (a) fetching an instruction (b) clock speed (c) fetching, decoding and executing an instruction (d)executing an instruction
2. Cache memory enhances_____________________ (a) memory capacity (b) memory access time (c) secondary storage capacity (d) secondary storage access time 3. 8086 microprocessor is interfaced to 8253 a programmable interval timer. The maximum number by which the clock frequency on one of the timers is divided by______________ a) 2
16 b) 2
8 c) 2
10 d) 2
20
4. The contents of different registers are given below. Form Effective addresses for different addressing modes are as follow : Offset = 5000H [AX]- 1000H, [BX]- 2000H, [SI]- 3000H, [DI]- 4000H, [BP]- 5000H, [SP]- 6000H, [CS]- 0000H, [DS]- 1000H, [SS]- 2000H, [IP]- 7000H.
I. MOV AX, [5000H]
a) 5000Hb) 15000H c) 10500H II. MOV AX, [BX] [SI]
a) 13000H b) 15000H c) 12000H III. MOV AX, 5000H [BX] [SI]
a) 20000H b) 1A000H c) 1A00H
5. The conditional branch instruction JNS performs the operations when if __ a) ZF =0 b) SF=0 c) PF=0 d) CF=0 6.What is the output of the following code SI=10010011 10101101, CF=0 SHR SI, 1 a) 37805, CF=1, OF=1 b) 18902, CF=1, OF=1 c) 19820, CF=1, OF=1 c) 53708, CF=1, OF=1
13. What is the output of the following code BX=23763 CL=8 ROL BX, CL a) 0101110011010011, CF=0 b) 1101001101011100, CF=0 c) 0110100010011101, CF=1 c) 1011100110001100, CF=1 7. In 8086 microprocessor one of the following instructions is executed before an arithmetic operation a) AAM b) AAD c) DAS d) DAA 8.What is the Maximum clock frequency in 8086____________
9. What is the position of the Stack Pointer after the POP instruction______________ 10. Which interrupts are generally used for critical events_______________________ 11. What is internal structure of 8086__________________ 12. Which Segment is used to store interrupt and subroutine return address registers_________________ 13. What are the various segment registers in 8086_______________________
14. The Intel 8086 processor is _______________________
(a) 8-bit
(b) 16-bit
(c) 32-bit
(d) 64-bit
15. A scheme in which the address specifies which memory word contains the address of the operand, is called_______________________
(a) Immediate addressing
(b) Based addressing
(c) Direct addressing
(d) Indirect addressing
16. In which microprocessor does the concept of pipeline first introduced___________________
(a) 8086
(b) 80286
(c) 80386
(d) 80486
QUESTION BANK 1. How many bits does 8086 microprocessor have? 2. What is the size of data bus in 8086? 3. What is the size of address bus in 8086? 4. What is the max memory addressing capacity of 8086? 5. Which are the basic parts of 8086? 6. What are the functions of BIU? 7. What are the functions of EU? 8. How many pin IC 8086 is? 9. What IC8086 is? 10. What is the size of instruction queue in 8086? 11. What is the size of instruction queue in 8088? 12. Which are the registers present in 8086? 13. What is pipelining in 8086? 14. How many 16 bit registers are available in 8086? 15. Specify addressing modes for any instruction? 16. What is assembler directives? 17. What .model small stands for? 18. What is the supply requirement of 8086? 19. What is the relation between 8086 processor frequency & crystal frequency? 20. Functions of Accumulator or AX register? 21. Functions of BX register? 22. Functions of CX register? 23. Functions of DX register? 24. How Physical address is generated? 25. Which are pointers present in this 8086? 26. Which is by default pointer for CS/ES? 27. How many segments present in it? 28. What is the size of each segment? 29. Basic difference between 8085 and 8086? 30. Which operations are not available in 8085? 31. What is the difference between min mode and max mode of 8086? 32. What is the difference between near and far procedure? 33. What is the difference between Macro and procedure? 34. What is the difference between instructions RET & IRET? 35. What is the difference between instructions MUL & IMUL? 36. What is the difference between instructions DIV & IDIV? 37. What is difference between shifts and rotate instructions? 38. Which are strings related instructions? 39. Which are addressing modes and their examples in 8086? 40. What does u mean by directives?
41. What does u mean by Prefix? 42. What .model small means? 43. Difference between small, medium, tiny, huge? 44. What is dd, dw, db? 45. Interrupts in 8086 and there function. 46. What is the function of 01h of Int 21h? 47. What is the function of 02h of Int 21h? 48. What is the function of 09h of Int 21h? 49. What is the function of 0Ah of Int 21h? 50. What is the function of 4ch of Int 21h? 51. What is the reset address of 8086? 52. What is the size of flag register in 8086? Explain all. 53. What is the difference between 08H and 01H functions of INT 21H? 54. Which is faster- Reading word size data whose starting address is at even or at odd address of memory in 8086? 55. Which are the default segment base: offset pairs? 56. Can we use SP as offset address holder with CS? 57. Which are the base registers in 8086? 58. Which is the index registers in 8086? 59. What is segment override prefix? 60. Whether micro reduces memory requirements? 61. What is macro? 62. What is diff between macro and procedure? 63. Types of procedure? 64. What TASM is? 65. What TLINK is? 66. What TD is? 67. What do u mean by assembler? 68. What do u mean by linker? 69. What do u mean by loader? 70. What do u mean by compiler? 71. What do u mean by emulator? 72. Stack related instruction? 73. .stack 100 means? 74. What is 20 dup (0)? 75. Which flags of 8086 are not present in 8085? 76. What is the size of flag register? 77. Can you perform 32 bit operation with 8086? How? 78. Whether 8086 is compatible with Pentium processor? 79. What is 8087? How it is different from 8086? 80. While accepting no. from user why u need to subtract 30 from that? 81. While displaying no. from user why u need to add 30 to that? 82. What are ASCII codes for nos. 0 to F? 83. How does U differentiate between positive and negative numbers? 84. What is range for these numbers? 85. Which no. representation system you have used?
86. What is LEA? 87. What is @data indicates in instruction- MOV ax, @data? 88. What is maximum size of the instruction in 8086? 89. Why we indicate FF as 0FF in program? 90. What is mul BX and div BX? Where result goes? 91. Where queue is present? 92. What is the advantage of using internal registers? 93. What is SI, DI and their functions? 94. Which are the pointers used in 8086 and their functions? 95. What is a type of queue in 8086? 96. What is minimum mode of 8086? 97. What is maximum mode of 8086? 98. Which are string instructions? 99. In string operations which is by default string source pointer? 100. In string operations which is by default string destination pointer? PART –B Q1. Write an algorithm to compute Fibonacci numbers using a recursive procedure. Write 8086 assembly program for the above Q2. Write an algorithm and assembly program to convert an unpacked 4 digit number to Binary number. Q3. Write an algorithm and assembly program to convert a 16 bit number to a maximum of 5 unpacked digits Q4. Write an algorithm and assembly program to convert an unpacked 4 digit number to Binary number. Q5. Write an algorithm and assembly program to find the square root of a 16 bit number using shift and subtract method. Q6. Write an algorithm and assembly program to reverse the bits in a 16 bit number and check whether it is a palindrome. Q7. Write an algorithm and assembly program for a cash bill of n materials. Rupees is a 4 digit and paisa is a 2 digit number which are stored in two different arrays. Find the total amount for the n materials. Subtract 10% discount on the total and give the actual amount to be paid. Hint Shift the total amount by one digit to get the 10% discount and get the actual amount. Q8.Explain EQU directive with example Q9. Explain SEGMENT directives with examples Q10. Explain coding template for 8086 instruction Q11. Briefly explain the maximum mode configuration of 8086.
Q12. What is the difference between minimum and maximum modes of 8086? Q13. How many interrupts are available in 8086? List the predefined software interrupts available in 8086. Q14. Briefly explain the maximum mode configuration of 8086. Q15. What is the purpose of MN/Mx pin? Explain. Q16. Explain the concept of segmented memory? What are its advantages? Q17. Explain the concept of pipelining in 8086. Discuss its advantages and disadvantages Q18. Discuss the interrupt system of Intel 8086. What is interrupt pointer? What is 'type' of an interrupt? Q19.. Discuss the various addressing modes of 8086. What are displacement, base and index? What is an effective address or offset? Q20. What is the difference between minimum and maximum modes of 8086? How are these modes selected? Q21. Draw and explain the architecture of 8086. Q22. Write an 8086 program to add two 16-bit numbers in CX and DX and store the result in location 0500H addressed by DI.
