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96 GHz Static Frequency Divider in SiGe bipolar technology
Alexander Rylyakov and Thomas Zwick
IBM T.J. Watson Research CenterNovember 12, 2003
Outline• Review of previous 0.13 um SiGe results:
– 4.2 ps Ring Oscillators– 100 GHz Dynamic Divider– 62 GHz ECL Static Divider
• Design of the 96 GHz E2CL Static Divider
• Test Setup and Measurement Results
• 0.13 um and 0.18 um SiGe Dividers Performance Summary and Conclusion
SiGe8HP Technology Overview and Ring Oscillators
Cutoff frequency +75% from prior generation: > 200 GHz fT
Power gain cutoff frequency +80% from prior generation: fMAX(MAG) > 180GHz and fMAX(U) > 250 GHz
Record RO delays: < 50% of prior generation
■ Experimental SiGe9HP development wafer achieves 3.9 ps
0
50
100
150
200
250
300
1.E-04 1.E-03 1.E-02 1.E-01
Collector current (A)
Next generation BiCMOS 8HP
Production BiCMOS 7HP
U fMAXVcb=1V, 25C
fT
MAG fMAX
0.5 1 1.5 2 2.5 3 3.5 4Tail current, mA
4.2
4.34.4
4.54.6
4.74.8
4.95
5.15.2
Del
ay p
er s
tage
, ps
R130, E12R130, E16R160, E12R105, E12
VEE = -3.6V
RNOM, WEMIT
InP best reported55% higher power15+% lower swing
fT, fMAX vs. IC RO delay vs. tail current
*
* (2002 data)
SiGe8HP Dynamic Frequency Divider■ Record Performance:
► 100 GHz, 285mW at -3.8V► outputs 260 mVpp single-ended at 50 GHz► packaged and tested by SHF (Electronics Letters, Jan 2003)
■ Competition (published results):► Hitachi: SiGe, 82 GHz, 396mW at -5.2V,
used divide by 4 (ISSCC 2000)► NTT: InP/InGaAs HBTs, 90 GHz, 1.4W total at -5.5V,
used divide by 8, claim 110mW per flip-flop (IPRM 2002)
10 ps/div
100
mV
/div
GND
fINfOUT
VEE
Output 50 GHz signal at 100 GHz inputDynamic divider circuit diagram
SiGe8HP ECL Static Frequency Divider
■ Maximum input frequency: 62 GHz, at -3.8V
■ Close to 2x increase in performance (compared to same design in SiGe7HP)
■ Power dissipation can be traded off for performance
300.4
450.8
491.0
602.8
max frequency ( GHz )
tail current ( mA )
Vee = - 3V, Pin = 0 dBm
Die micrograph Power-speed tradeoff
Design of the 96 GHz E2CL Static Divider
• Motivation:– explore performance limits of 0.13 um SiGe
(“SiGe8HP”)– compare design approaches
(ECL vs E2CL)– develop test equipment (dividers are useful for synchronization)
• Design Overview:– fully static, double emitter follower design– no inductive peaking – input clock signal is not amplified, only down-shifted
using emitter followers– output clock buffer is a Cherry-Hooper amplifier
Block Diagram of the Design
CLOCK/2
LATCHD
DBC CB
Q
QBLATCH
D
DBC CB
Q
QB
Cherry-Hooper
CLOCK
Emitter Followers
Latch SchematicGND
VEE
DATA IN DATA OUT
CLOCK
R1
R2
Die MicrographCLOCK/2
CLOCK
Test Setup Block Diagram
ϕWR10
Magic Tas Balun
ϕWR10
TermWR10
WR10
WR10
WR10
Probe:
GP
PG
SG
SG
PP
G
1 mm CoaxαWR10WR10
Amplifier( 14 dB at 85 GHz)
x6
all on one positioner
SMA CoaxP
robe:G
PP
GS
GS
GP
PG
ProbeNeedles
Variable AttenuatorFrequency Multiplier
( 75 – 110 GHz )
SpectrumAnalyzer
CW Source(12-18 GHz)
~ 1.85 mm Coax DUTProbeNeedlesTrigger
Oscilloscope/2SMA Coax
Phase Shifters
WR10 to 1 mm adapters
Test Setup
Multiplier Amplifier Attenuator
Magic-T
Phase Shifter
WR-10 to 1.0 mm Adapter
1.0 mm Cable
48.3 GHz Output Signal50
mV/
div
10 ps/div
Divider Output Spectrum
Divider Output Spectrum( 20 MHz span)
Input Sensitivity of the Divider
-35
-30
-25
-20
-15
-10
-5
0
5
10
0 10 20 30 40 50 60 70 80 90 100
Input Frequency, GHz
Inpu
t Pow
er, d
Bm
-5.5V, differential clock
-5.5V, single-ended clock
-5.0V, single-ended clock
SiGe8HP and 7HP Frequency DividersPerformance Summary
96
35
140 1
-5.5
† Static E2CL
49413362100fCLK(GHz)
1918924nonefSO (GHz)
66280 132 268 175 1IEE (mA)
-5.2-3.6-3.6-3.8-3.8VEE (V)
* StaticE2CL
* Static ECLi
* Static ECL
* Static ECL
* DynamicECL
0.18µm SiGe (7HP)0.13µm SiGe (8HP)
Dividers marked with ‘1’: total current for the whole chipDividers marked with ‘2’: estimate for divider core only
fSO is the frequency of self-oscillationfCLK is the maximum input frequency
■ Static ECL shows ~ 2x speed up (8HP vs 7HP, same design and power dissipation)■ Within same technology, E2CL is faster than plain ECL, but burns more power■ Inductive peaking (ECLi) also improves performance, trading off area( * Electronics Letters, Jan. 2003; † This work )
Conclusion
A 96 GHz Static Frequency Divider was designed and tested in a 210 GHz fT0.13 µm SiGe bipolar technology
To our knowledge, this is the fastest static divider in any Si-based technology